1 /* 2 * Model of Petalogix linux reference design targeting Xilinx Spartan ml605 3 * board. 4 * 5 * Copyright (c) 2011 Michal Simek <monstr@monstr.eu> 6 * Copyright (c) 2011 PetaLogix 7 * Copyright (c) 2009 Edgar E. Iglesias. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 #include "hw/sysbus.h" 29 #include "hw/hw.h" 30 #include "net/net.h" 31 #include "hw/block/flash.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/devices.h" 34 #include "hw/boards.h" 35 #include "sysemu/block-backend.h" 36 #include "hw/char/serial.h" 37 #include "exec/address-spaces.h" 38 #include "hw/ssi/ssi.h" 39 40 #include "boot.h" 41 42 #include "hw/stream.h" 43 44 #define LMB_BRAM_SIZE (128 * 1024) 45 #define FLASH_SIZE (32 * 1024 * 1024) 46 47 #define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb" 48 49 #define NUM_SPI_FLASHES 4 50 51 #define SPI_BASEADDR 0x40a00000 52 #define MEMORY_BASEADDR 0x50000000 53 #define FLASH_BASEADDR 0x86000000 54 #define INTC_BASEADDR 0x81800000 55 #define TIMER_BASEADDR 0x83c00000 56 #define UART16550_BASEADDR 0x83e00000 57 #define AXIENET_BASEADDR 0x82780000 58 #define AXIDMA_BASEADDR 0x84600000 59 60 #define AXIDMA_IRQ1 0 61 #define AXIDMA_IRQ0 1 62 #define TIMER_IRQ 2 63 #define AXIENET_IRQ 3 64 #define SPI_IRQ 4 65 #define UART16550_IRQ 5 66 67 static void 68 petalogix_ml605_init(MachineState *machine) 69 { 70 ram_addr_t ram_size = machine->ram_size; 71 MemoryRegion *address_space_mem = get_system_memory(); 72 DeviceState *dev, *dma, *eth0; 73 Object *ds, *cs; 74 MicroBlazeCPU *cpu; 75 SysBusDevice *busdev; 76 DriveInfo *dinfo; 77 int i; 78 MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1); 79 MemoryRegion *phys_ram = g_new(MemoryRegion, 1); 80 qemu_irq irq[32]; 81 82 /* init CPUs */ 83 cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); 84 object_property_set_str(OBJECT(cpu), "8.10.a", "version", &error_abort); 85 /* Use FPU but don't use floating point conversion and square 86 * root instructions 87 */ 88 object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort); 89 object_property_set_bool(OBJECT(cpu), true, "dcache-writeback", 90 &error_abort); 91 object_property_set_bool(OBJECT(cpu), true, "endianness", &error_abort); 92 object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort); 93 94 /* Attach emulated BRAM through the LMB. */ 95 memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram", 96 LMB_BRAM_SIZE, &error_fatal); 97 vmstate_register_ram_global(phys_lmb_bram); 98 memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram); 99 100 memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size, 101 &error_fatal); 102 vmstate_register_ram_global(phys_ram); 103 memory_region_add_subregion(address_space_mem, MEMORY_BASEADDR, phys_ram); 104 105 dinfo = drive_get(IF_PFLASH, 0, 0); 106 /* 5th parameter 2 means bank-width 107 * 10th paremeter 0 means little-endian */ 108 pflash_cfi01_register(FLASH_BASEADDR, 109 NULL, "petalogix_ml605.flash", FLASH_SIZE, 110 dinfo ? blk_by_legacy_dinfo(dinfo) : NULL, 111 (64 * 1024), FLASH_SIZE >> 16, 112 2, 0x89, 0x18, 0x0000, 0x0, 0); 113 114 115 dev = qdev_create(NULL, "xlnx.xps-intc"); 116 qdev_prop_set_uint32(dev, "kind-of-intr", 1 << TIMER_IRQ); 117 qdev_init_nofail(dev); 118 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); 119 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 120 qdev_get_gpio_in(DEVICE(cpu), MB_CPU_IRQ)); 121 for (i = 0; i < 32; i++) { 122 irq[i] = qdev_get_gpio_in(dev, i); 123 } 124 125 serial_mm_init(address_space_mem, UART16550_BASEADDR + 0x1000, 2, 126 irq[UART16550_IRQ], 115200, serial_hds[0], 127 DEVICE_LITTLE_ENDIAN); 128 129 /* 2 timers at irq 2 @ 100 Mhz. */ 130 dev = qdev_create(NULL, "xlnx.xps-timer"); 131 qdev_prop_set_uint32(dev, "one-timer-only", 0); 132 qdev_prop_set_uint32(dev, "clock-frequency", 100 * 1000000); 133 qdev_init_nofail(dev); 134 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); 135 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); 136 137 /* axi ethernet and dma initialization. */ 138 qemu_check_nic_model(&nd_table[0], "xlnx.axi-ethernet"); 139 eth0 = qdev_create(NULL, "xlnx.axi-ethernet"); 140 dma = qdev_create(NULL, "xlnx.axi-dma"); 141 142 /* FIXME: attach to the sysbus instead */ 143 object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0), 144 NULL); 145 object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma), 146 NULL); 147 148 ds = object_property_get_link(OBJECT(dma), 149 "axistream-connected-target", NULL); 150 cs = object_property_get_link(OBJECT(dma), 151 "axistream-control-connected-target", NULL); 152 qdev_set_nic_properties(eth0, &nd_table[0]); 153 qdev_prop_set_uint32(eth0, "rxmem", 0x1000); 154 qdev_prop_set_uint32(eth0, "txmem", 0x1000); 155 object_property_set_link(OBJECT(eth0), OBJECT(ds), 156 "axistream-connected", &error_abort); 157 object_property_set_link(OBJECT(eth0), OBJECT(cs), 158 "axistream-control-connected", &error_abort); 159 qdev_init_nofail(eth0); 160 sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR); 161 sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]); 162 163 ds = object_property_get_link(OBJECT(eth0), 164 "axistream-connected-target", NULL); 165 cs = object_property_get_link(OBJECT(eth0), 166 "axistream-control-connected-target", NULL); 167 qdev_prop_set_uint32(dma, "freqhz", 100 * 1000000); 168 object_property_set_link(OBJECT(dma), OBJECT(ds), 169 "axistream-connected", &error_abort); 170 object_property_set_link(OBJECT(dma), OBJECT(cs), 171 "axistream-control-connected", &error_abort); 172 qdev_init_nofail(dma); 173 sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR); 174 sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]); 175 sysbus_connect_irq(SYS_BUS_DEVICE(dma), 1, irq[AXIDMA_IRQ1]); 176 177 { 178 SSIBus *spi; 179 180 dev = qdev_create(NULL, "xlnx.xps-spi"); 181 qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES); 182 qdev_init_nofail(dev); 183 busdev = SYS_BUS_DEVICE(dev); 184 sysbus_mmio_map(busdev, 0, SPI_BASEADDR); 185 sysbus_connect_irq(busdev, 0, irq[SPI_IRQ]); 186 187 spi = (SSIBus *)qdev_get_child_bus(dev, "spi"); 188 189 for (i = 0; i < NUM_SPI_FLASHES; i++) { 190 qemu_irq cs_line; 191 192 dev = ssi_create_slave(spi, "n25q128"); 193 cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0); 194 sysbus_connect_irq(busdev, i+1, cs_line); 195 } 196 } 197 198 /* setup PVR to match kernel settings */ 199 cpu->env.pvr.regs[4] = 0xc56b8000; 200 cpu->env.pvr.regs[5] = 0xc56be000; 201 cpu->env.pvr.regs[10] = 0x0e000000; /* virtex 6 */ 202 203 microblaze_load_kernel(cpu, MEMORY_BASEADDR, ram_size, 204 machine->initrd_filename, 205 BINARY_DEVICE_TREE_FILE, 206 NULL); 207 208 } 209 210 static void petalogix_ml605_machine_init(MachineClass *mc) 211 { 212 mc->desc = "PetaLogix linux refdesign for xilinx ml605 little endian"; 213 mc->init = petalogix_ml605_init; 214 mc->is_default = 0; 215 } 216 217 DEFINE_MACHINE("petalogix-ml605", petalogix_ml605_machine_init) 218