1 /* 2 * Model of Petalogix linux reference design targeting Xilinx Spartan ml605 3 * board. 4 * 5 * Copyright (c) 2011 Michal Simek <monstr@monstr.eu> 6 * Copyright (c) 2011 PetaLogix 7 * Copyright (c) 2009 Edgar E. Iglesias. 8 * 9 * Permission is hereby granted, free of charge, to any person obtaining a copy 10 * of this software and associated documentation files (the "Software"), to deal 11 * in the Software without restriction, including without limitation the rights 12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 13 * copies of the Software, and to permit persons to whom the Software is 14 * furnished to do so, subject to the following conditions: 15 * 16 * The above copyright notice and this permission notice shall be included in 17 * all copies or substantial portions of the Software. 18 * 19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 25 * THE SOFTWARE. 26 */ 27 28 #include "hw/sysbus.h" 29 #include "hw/hw.h" 30 #include "net/net.h" 31 #include "hw/block/flash.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/devices.h" 34 #include "hw/boards.h" 35 #include "hw/xilinx.h" 36 #include "sysemu/blockdev.h" 37 #include "hw/char/serial.h" 38 #include "exec/address-spaces.h" 39 #include "hw/ssi.h" 40 41 #include "boot.h" 42 #include "pic_cpu.h" 43 44 #include "hw/stream.h" 45 46 #define LMB_BRAM_SIZE (128 * 1024) 47 #define FLASH_SIZE (32 * 1024 * 1024) 48 49 #define BINARY_DEVICE_TREE_FILE "petalogix-ml605.dtb" 50 51 #define NUM_SPI_FLASHES 4 52 53 #define MEMORY_BASEADDR 0x50000000 54 #define FLASH_BASEADDR 0x86000000 55 #define INTC_BASEADDR 0x81800000 56 #define TIMER_BASEADDR 0x83c00000 57 #define UART16550_BASEADDR 0x83e00000 58 #define AXIENET_BASEADDR 0x82780000 59 #define AXIDMA_BASEADDR 0x84600000 60 61 static void machine_cpu_reset(MicroBlazeCPU *cpu) 62 { 63 CPUMBState *env = &cpu->env; 64 65 env->pvr.regs[10] = 0x0e000000; /* virtex 6 */ 66 /* setup pvr to match kernel setting */ 67 env->pvr.regs[5] |= PVR5_DCACHE_WRITEBACK_MASK; 68 env->pvr.regs[0] |= PVR0_USE_FPU_MASK | PVR0_ENDI; 69 env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8); 70 env->pvr.regs[2] ^= PVR2_USE_FPU2_MASK; 71 env->pvr.regs[4] = 0xc56b8000; 72 env->pvr.regs[5] = 0xc56be000; 73 } 74 75 static void 76 petalogix_ml605_init(QEMUMachineInitArgs *args) 77 { 78 ram_addr_t ram_size = args->ram_size; 79 const char *cpu_model = args->cpu_model; 80 MemoryRegion *address_space_mem = get_system_memory(); 81 DeviceState *dev, *dma, *eth0; 82 Object *ds, *cs; 83 MicroBlazeCPU *cpu; 84 SysBusDevice *busdev; 85 CPUMBState *env; 86 DriveInfo *dinfo; 87 int i; 88 hwaddr ddr_base = MEMORY_BASEADDR; 89 MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1); 90 MemoryRegion *phys_ram = g_new(MemoryRegion, 1); 91 qemu_irq irq[32], *cpu_irq; 92 93 /* init CPUs */ 94 if (cpu_model == NULL) { 95 cpu_model = "microblaze"; 96 } 97 cpu = cpu_mb_init(cpu_model); 98 env = &cpu->env; 99 100 /* Attach emulated BRAM through the LMB. */ 101 memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram", 102 LMB_BRAM_SIZE); 103 vmstate_register_ram_global(phys_lmb_bram); 104 memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram); 105 106 memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size); 107 vmstate_register_ram_global(phys_ram); 108 memory_region_add_subregion(address_space_mem, ddr_base, phys_ram); 109 110 dinfo = drive_get(IF_PFLASH, 0, 0); 111 /* 5th parameter 2 means bank-width 112 * 10th paremeter 0 means little-endian */ 113 pflash_cfi01_register(FLASH_BASEADDR, 114 NULL, "petalogix_ml605.flash", FLASH_SIZE, 115 dinfo ? dinfo->bdrv : NULL, (64 * 1024), 116 FLASH_SIZE >> 16, 117 2, 0x89, 0x18, 0x0000, 0x0, 0); 118 119 120 cpu_irq = microblaze_pic_init_cpu(env); 121 dev = xilinx_intc_create(INTC_BASEADDR, cpu_irq[0], 4); 122 for (i = 0; i < 32; i++) { 123 irq[i] = qdev_get_gpio_in(dev, i); 124 } 125 126 serial_mm_init(address_space_mem, UART16550_BASEADDR + 0x1000, 2, 127 irq[5], 115200, serial_hds[0], DEVICE_LITTLE_ENDIAN); 128 129 /* 2 timers at irq 2 @ 100 Mhz. */ 130 xilinx_timer_create(TIMER_BASEADDR, irq[2], 0, 100 * 1000000); 131 132 /* axi ethernet and dma initialization. */ 133 qemu_check_nic_model(&nd_table[0], "xlnx.axi-ethernet"); 134 eth0 = qdev_create(NULL, "xlnx.axi-ethernet"); 135 dma = qdev_create(NULL, "xlnx.axi-dma"); 136 137 /* FIXME: attach to the sysbus instead */ 138 object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0), 139 NULL); 140 object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma), 141 NULL); 142 143 ds = object_property_get_link(OBJECT(dma), 144 "axistream-connected-target", NULL); 145 cs = object_property_get_link(OBJECT(dma), 146 "axistream-control-connected-target", NULL); 147 xilinx_axiethernet_init(eth0, &nd_table[0], STREAM_SLAVE(ds), 148 STREAM_SLAVE(cs), 0x82780000, irq[3], 0x1000, 149 0x1000); 150 151 ds = object_property_get_link(OBJECT(eth0), 152 "axistream-connected-target", NULL); 153 cs = object_property_get_link(OBJECT(eth0), 154 "axistream-control-connected-target", NULL); 155 xilinx_axidma_init(dma, STREAM_SLAVE(ds), STREAM_SLAVE(cs), 0x84600000, 156 irq[1], irq[0], 100 * 1000000); 157 158 { 159 SSIBus *spi; 160 161 dev = qdev_create(NULL, "xlnx.xps-spi"); 162 qdev_prop_set_uint8(dev, "num-ss-bits", NUM_SPI_FLASHES); 163 qdev_init_nofail(dev); 164 busdev = SYS_BUS_DEVICE(dev); 165 sysbus_mmio_map(busdev, 0, 0x40a00000); 166 sysbus_connect_irq(busdev, 0, irq[4]); 167 168 spi = (SSIBus *)qdev_get_child_bus(dev, "spi"); 169 170 for (i = 0; i < NUM_SPI_FLASHES; i++) { 171 qemu_irq cs_line; 172 173 dev = ssi_create_slave(spi, "n25q128"); 174 cs_line = qdev_get_gpio_in(dev, 0); 175 sysbus_connect_irq(busdev, i+1, cs_line); 176 } 177 } 178 179 microblaze_load_kernel(cpu, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE, 180 machine_cpu_reset); 181 182 } 183 184 static QEMUMachine petalogix_ml605_machine = { 185 .name = "petalogix-ml605", 186 .desc = "PetaLogix linux refdesign for xilinx ml605 little endian", 187 .init = petalogix_ml605_init, 188 .is_default = 0, 189 DEFAULT_MACHINE_OPTIONS, 190 }; 191 192 static void petalogix_ml605_machine_init(void) 193 { 194 qemu_register_machine(&petalogix_ml605_machine); 195 } 196 197 machine_init(petalogix_ml605_machine_init); 198