1 /* 2 * QEMU Motorla 680x0 Macintosh hardware System Emulator 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a copy 5 * of this software and associated documentation files (the "Software"), to deal 6 * in the Software without restriction, including without limitation the rights 7 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 8 * copies of the Software, and to permit persons to whom the Software is 9 * furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 18 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 19 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 20 * THE SOFTWARE. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "qemu/units.h" 25 #include "qemu/datadir.h" 26 #include "qemu/guest-random.h" 27 #include "sysemu/sysemu.h" 28 #include "cpu.h" 29 #include "hw/boards.h" 30 #include "hw/or-irq.h" 31 #include "hw/nmi.h" 32 #include "elf.h" 33 #include "hw/loader.h" 34 #include "ui/console.h" 35 #include "hw/char/escc.h" 36 #include "hw/sysbus.h" 37 #include "hw/scsi/esp.h" 38 #include "standard-headers/asm-m68k/bootinfo.h" 39 #include "standard-headers/asm-m68k/bootinfo-mac.h" 40 #include "bootinfo.h" 41 #include "hw/misc/mac_via.h" 42 #include "hw/input/adb.h" 43 #include "hw/nubus/mac-nubus-bridge.h" 44 #include "hw/display/macfb.h" 45 #include "hw/block/swim.h" 46 #include "net/net.h" 47 #include "qapi/error.h" 48 #include "sysemu/qtest.h" 49 #include "sysemu/runstate.h" 50 #include "sysemu/reset.h" 51 #include "migration/vmstate.h" 52 53 #define MACROM_ADDR 0x40800000 54 #define MACROM_SIZE 0x00100000 55 56 #define MACROM_FILENAME "MacROM.bin" 57 58 #define IO_BASE 0x50000000 59 #define IO_SLICE 0x00040000 60 #define IO_SIZE 0x04000000 61 62 #define VIA_BASE (IO_BASE + 0x00000) 63 #define SONIC_PROM_BASE (IO_BASE + 0x08000) 64 #define SONIC_BASE (IO_BASE + 0x0a000) 65 #define SCC_BASE (IO_BASE + 0x0c020) 66 #define ESP_BASE (IO_BASE + 0x10000) 67 #define ESP_PDMA (IO_BASE + 0x10100) 68 #define ASC_BASE (IO_BASE + 0x14000) 69 #define SWIM_BASE (IO_BASE + 0x1E000) 70 71 #define SONIC_PROM_SIZE 0x1000 72 73 /* 74 * the video base, whereas it a Nubus address, 75 * is needed by the kernel to have early display and 76 * thus provided by the bootloader 77 */ 78 #define VIDEO_BASE 0xf9000000 79 80 #define MAC_CLOCK 3686418 81 82 /* 83 * Slot 0x9 is reserved for use by the in-built framebuffer whilst only 84 * slots 0xc, 0xd and 0xe physically exist on the Quadra 800 85 */ 86 #define Q800_NUBUS_SLOTS_AVAILABLE (BIT(0x9) | BIT(0xc) | BIT(0xd) | \ 87 BIT(0xe)) 88 89 /* 90 * The GLUE (General Logic Unit) is an Apple custom integrated circuit chip 91 * that performs a variety of functions (RAM management, clock generation, ...). 92 * The GLUE chip receives interrupt requests from various devices, 93 * assign priority to each, and asserts one or more interrupt line to the 94 * CPU. 95 */ 96 97 #define TYPE_GLUE "q800-glue" 98 OBJECT_DECLARE_SIMPLE_TYPE(GLUEState, GLUE) 99 100 struct GLUEState { 101 SysBusDevice parent_obj; 102 M68kCPU *cpu; 103 uint8_t ipr; 104 uint8_t auxmode; 105 qemu_irq irqs[1]; 106 QEMUTimer *nmi_release; 107 }; 108 109 #define GLUE_IRQ_IN_VIA1 0 110 #define GLUE_IRQ_IN_VIA2 1 111 #define GLUE_IRQ_IN_SONIC 2 112 #define GLUE_IRQ_IN_ESCC 3 113 #define GLUE_IRQ_IN_NMI 4 114 115 #define GLUE_IRQ_NUBUS_9 0 116 117 /* 118 * The GLUE logic on the Quadra 800 supports 2 different IRQ routing modes 119 * controlled from the VIA1 auxmode GPIO (port B bit 6) which are documented 120 * in NetBSD as follows: 121 * 122 * A/UX mode (Linux, NetBSD, auxmode GPIO low) 123 * 124 * Level 0: Spurious: ignored 125 * Level 1: Software 126 * Level 2: VIA2 (except ethernet, sound) 127 * Level 3: Ethernet 128 * Level 4: Serial (SCC) 129 * Level 5: Sound 130 * Level 6: VIA1 131 * Level 7: NMIs: parity errors, RESET button, YANCC error 132 * 133 * Classic mode (default: used by MacOS, A/UX 3.0.1, auxmode GPIO high) 134 * 135 * Level 0: Spurious: ignored 136 * Level 1: VIA1 (clock, ADB) 137 * Level 2: VIA2 (NuBus, SCSI) 138 * Level 3: 139 * Level 4: Serial (SCC) 140 * Level 5: 141 * Level 6: 142 * Level 7: Non-maskable: parity errors, RESET button 143 * 144 * Note that despite references to A/UX mode in Linux and NetBSD, at least 145 * A/UX 3.0.1 still uses Classic mode. 146 */ 147 148 static void GLUE_set_irq(void *opaque, int irq, int level) 149 { 150 GLUEState *s = opaque; 151 int i; 152 153 if (s->auxmode) { 154 /* Classic mode */ 155 switch (irq) { 156 case GLUE_IRQ_IN_VIA1: 157 irq = 0; 158 break; 159 160 case GLUE_IRQ_IN_VIA2: 161 irq = 1; 162 break; 163 164 case GLUE_IRQ_IN_SONIC: 165 /* Route to VIA2 instead */ 166 qemu_set_irq(s->irqs[GLUE_IRQ_NUBUS_9], level); 167 return; 168 169 case GLUE_IRQ_IN_ESCC: 170 irq = 3; 171 break; 172 173 case GLUE_IRQ_IN_NMI: 174 irq = 6; 175 break; 176 177 default: 178 g_assert_not_reached(); 179 } 180 } else { 181 /* A/UX mode */ 182 switch (irq) { 183 case GLUE_IRQ_IN_VIA1: 184 irq = 5; 185 break; 186 187 case GLUE_IRQ_IN_VIA2: 188 irq = 1; 189 break; 190 191 case GLUE_IRQ_IN_SONIC: 192 irq = 2; 193 break; 194 195 case GLUE_IRQ_IN_ESCC: 196 irq = 3; 197 break; 198 199 case GLUE_IRQ_IN_NMI: 200 irq = 6; 201 break; 202 203 default: 204 g_assert_not_reached(); 205 } 206 } 207 208 if (level) { 209 s->ipr |= 1 << irq; 210 } else { 211 s->ipr &= ~(1 << irq); 212 } 213 214 for (i = 7; i >= 0; i--) { 215 if ((s->ipr >> i) & 1) { 216 m68k_set_irq_level(s->cpu, i + 1, i + 25); 217 return; 218 } 219 } 220 m68k_set_irq_level(s->cpu, 0, 0); 221 } 222 223 static void glue_auxmode_set_irq(void *opaque, int irq, int level) 224 { 225 GLUEState *s = GLUE(opaque); 226 227 s->auxmode = level; 228 } 229 230 static void glue_nmi(NMIState *n, int cpu_index, Error **errp) 231 { 232 GLUEState *s = GLUE(n); 233 234 /* Hold NMI active for 100ms */ 235 GLUE_set_irq(s, GLUE_IRQ_IN_NMI, 1); 236 timer_mod(s->nmi_release, qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL) + 100); 237 } 238 239 static void glue_nmi_release(void *opaque) 240 { 241 GLUEState *s = GLUE(opaque); 242 243 GLUE_set_irq(s, GLUE_IRQ_IN_NMI, 0); 244 } 245 246 static void glue_reset(DeviceState *dev) 247 { 248 GLUEState *s = GLUE(dev); 249 250 s->ipr = 0; 251 s->auxmode = 0; 252 253 timer_del(s->nmi_release); 254 } 255 256 static const VMStateDescription vmstate_glue = { 257 .name = "q800-glue", 258 .version_id = 0, 259 .minimum_version_id = 0, 260 .fields = (VMStateField[]) { 261 VMSTATE_UINT8(ipr, GLUEState), 262 VMSTATE_UINT8(auxmode, GLUEState), 263 VMSTATE_TIMER_PTR(nmi_release, GLUEState), 264 VMSTATE_END_OF_LIST(), 265 }, 266 }; 267 268 /* 269 * If the m68k CPU implemented its inbound irq lines as GPIO lines 270 * rather than via the m68k_set_irq_level() function we would not need 271 * this cpu link property and could instead provide outbound IRQ lines 272 * that the board could wire up to the CPU. 273 */ 274 static Property glue_properties[] = { 275 DEFINE_PROP_LINK("cpu", GLUEState, cpu, TYPE_M68K_CPU, M68kCPU *), 276 DEFINE_PROP_END_OF_LIST(), 277 }; 278 279 static void glue_finalize(Object *obj) 280 { 281 GLUEState *s = GLUE(obj); 282 283 timer_free(s->nmi_release); 284 } 285 286 static void glue_init(Object *obj) 287 { 288 DeviceState *dev = DEVICE(obj); 289 GLUEState *s = GLUE(dev); 290 291 qdev_init_gpio_in(dev, GLUE_set_irq, 8); 292 qdev_init_gpio_in_named(dev, glue_auxmode_set_irq, "auxmode", 1); 293 294 qdev_init_gpio_out(dev, s->irqs, 1); 295 296 /* NMI release timer */ 297 s->nmi_release = timer_new_ms(QEMU_CLOCK_VIRTUAL, glue_nmi_release, s); 298 } 299 300 static void glue_class_init(ObjectClass *klass, void *data) 301 { 302 DeviceClass *dc = DEVICE_CLASS(klass); 303 NMIClass *nc = NMI_CLASS(klass); 304 305 dc->vmsd = &vmstate_glue; 306 dc->reset = glue_reset; 307 device_class_set_props(dc, glue_properties); 308 nc->nmi_monitor_handler = glue_nmi; 309 } 310 311 static const TypeInfo glue_info = { 312 .name = TYPE_GLUE, 313 .parent = TYPE_SYS_BUS_DEVICE, 314 .instance_size = sizeof(GLUEState), 315 .instance_init = glue_init, 316 .instance_finalize = glue_finalize, 317 .class_init = glue_class_init, 318 .interfaces = (InterfaceInfo[]) { 319 { TYPE_NMI }, 320 { } 321 }, 322 }; 323 324 typedef struct { 325 M68kCPU *cpu; 326 struct bi_record *rng_seed; 327 } ResetInfo; 328 329 static void main_cpu_reset(void *opaque) 330 { 331 ResetInfo *reset_info = opaque; 332 M68kCPU *cpu = reset_info->cpu; 333 CPUState *cs = CPU(cpu); 334 335 if (reset_info->rng_seed) { 336 qemu_guest_getrandom_nofail((void *)reset_info->rng_seed->data + 2, 337 be16_to_cpu(*(uint16_t *)reset_info->rng_seed->data)); 338 } 339 340 cpu_reset(cs); 341 cpu->env.aregs[7] = ldl_phys(cs->as, 0); 342 cpu->env.pc = ldl_phys(cs->as, 4); 343 } 344 345 static uint8_t fake_mac_rom[] = { 346 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 347 348 /* offset: 0xa - mac_reset */ 349 350 /* via2[vDirB] |= VIA2B_vPower */ 351 0x20, 0x7C, 0x50, 0xF0, 0x24, 0x00, /* moveal VIA2_BASE+vDirB,%a0 */ 352 0x10, 0x10, /* moveb %a0@,%d0 */ 353 0x00, 0x00, 0x00, 0x04, /* orib #4,%d0 */ 354 0x10, 0x80, /* moveb %d0,%a0@ */ 355 356 /* via2[vBufB] &= ~VIA2B_vPower */ 357 0x20, 0x7C, 0x50, 0xF0, 0x20, 0x00, /* moveal VIA2_BASE+vBufB,%a0 */ 358 0x10, 0x10, /* moveb %a0@,%d0 */ 359 0x02, 0x00, 0xFF, 0xFB, /* andib #-5,%d0 */ 360 0x10, 0x80, /* moveb %d0,%a0@ */ 361 362 /* while (true) ; */ 363 0x60, 0xFE /* bras [self] */ 364 }; 365 366 static void q800_init(MachineState *machine) 367 { 368 M68kCPU *cpu = NULL; 369 int linux_boot; 370 int32_t kernel_size; 371 uint64_t elf_entry; 372 char *filename; 373 int bios_size; 374 ram_addr_t initrd_base; 375 int32_t initrd_size; 376 MemoryRegion *rom; 377 MemoryRegion *io; 378 MemoryRegion *dp8393x_prom = g_new(MemoryRegion, 1); 379 uint8_t *prom; 380 const int io_slice_nb = (IO_SIZE / IO_SLICE) - 1; 381 int i, checksum; 382 MacFbMode *macfb_mode; 383 ram_addr_t ram_size = machine->ram_size; 384 const char *kernel_filename = machine->kernel_filename; 385 const char *initrd_filename = machine->initrd_filename; 386 const char *kernel_cmdline = machine->kernel_cmdline; 387 const char *bios_name = machine->firmware ?: MACROM_FILENAME; 388 hwaddr parameters_base; 389 CPUState *cs; 390 DeviceState *dev; 391 DeviceState *via1_dev, *via2_dev; 392 DeviceState *escc_orgate; 393 SysBusESPState *sysbus_esp; 394 ESPState *esp; 395 SysBusDevice *sysbus; 396 BusState *adb_bus; 397 NubusBus *nubus; 398 DeviceState *glue; 399 DriveInfo *dinfo; 400 ResetInfo *reset_info; 401 uint8_t rng_seed[32]; 402 403 linux_boot = (kernel_filename != NULL); 404 405 if (ram_size > 1 * GiB) { 406 error_report("Too much memory for this machine: %" PRId64 " MiB, " 407 "maximum 1024 MiB", ram_size / MiB); 408 exit(1); 409 } 410 411 reset_info = g_new0(ResetInfo, 1); 412 413 /* init CPUs */ 414 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 415 reset_info->cpu = cpu; 416 qemu_register_reset(main_cpu_reset, reset_info); 417 418 /* RAM */ 419 memory_region_add_subregion(get_system_memory(), 0, machine->ram); 420 421 /* 422 * Memory from IO_BASE to IO_BASE + IO_SLICE is repeated 423 * from IO_BASE + IO_SLICE to IO_BASE + IO_SIZE 424 */ 425 io = g_new(MemoryRegion, io_slice_nb); 426 for (i = 0; i < io_slice_nb; i++) { 427 char *name = g_strdup_printf("mac_m68k.io[%d]", i + 1); 428 429 memory_region_init_alias(&io[i], NULL, name, get_system_memory(), 430 IO_BASE, IO_SLICE); 431 memory_region_add_subregion(get_system_memory(), 432 IO_BASE + (i + 1) * IO_SLICE, &io[i]); 433 g_free(name); 434 } 435 436 /* IRQ Glue */ 437 glue = qdev_new(TYPE_GLUE); 438 object_property_set_link(OBJECT(glue), "cpu", OBJECT(cpu), &error_abort); 439 sysbus_realize_and_unref(SYS_BUS_DEVICE(glue), &error_fatal); 440 441 /* VIA 1 */ 442 via1_dev = qdev_new(TYPE_MOS6522_Q800_VIA1); 443 dinfo = drive_get(IF_MTD, 0, 0); 444 if (dinfo) { 445 qdev_prop_set_drive(via1_dev, "drive", blk_by_legacy_dinfo(dinfo)); 446 } 447 sysbus = SYS_BUS_DEVICE(via1_dev); 448 sysbus_realize_and_unref(sysbus, &error_fatal); 449 sysbus_mmio_map(sysbus, 1, VIA_BASE); 450 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_VIA1)); 451 /* A/UX mode */ 452 qdev_connect_gpio_out(via1_dev, 0, 453 qdev_get_gpio_in_named(glue, "auxmode", 0)); 454 455 adb_bus = qdev_get_child_bus(via1_dev, "adb.0"); 456 dev = qdev_new(TYPE_ADB_KEYBOARD); 457 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 458 dev = qdev_new(TYPE_ADB_MOUSE); 459 qdev_realize_and_unref(dev, adb_bus, &error_fatal); 460 461 /* VIA 2 */ 462 via2_dev = qdev_new(TYPE_MOS6522_Q800_VIA2); 463 sysbus = SYS_BUS_DEVICE(via2_dev); 464 sysbus_realize_and_unref(sysbus, &error_fatal); 465 sysbus_mmio_map(sysbus, 1, VIA_BASE + VIA_SIZE); 466 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_VIA2)); 467 468 /* MACSONIC */ 469 470 if (nb_nics > 1) { 471 error_report("q800 can only have one ethernet interface"); 472 exit(1); 473 } 474 475 qemu_check_nic_model(&nd_table[0], "dp83932"); 476 477 /* 478 * MacSonic driver needs an Apple MAC address 479 * Valid prefix are: 480 * 00:05:02 Apple 481 * 00:80:19 Dayna Communications, Inc. 482 * 00:A0:40 Apple 483 * 08:00:07 Apple 484 * (Q800 use the last one) 485 */ 486 nd_table[0].macaddr.a[0] = 0x08; 487 nd_table[0].macaddr.a[1] = 0x00; 488 nd_table[0].macaddr.a[2] = 0x07; 489 490 dev = qdev_new("dp8393x"); 491 qdev_set_nic_properties(dev, &nd_table[0]); 492 qdev_prop_set_uint8(dev, "it_shift", 2); 493 qdev_prop_set_bit(dev, "big_endian", true); 494 object_property_set_link(OBJECT(dev), "dma_mr", 495 OBJECT(get_system_memory()), &error_abort); 496 sysbus = SYS_BUS_DEVICE(dev); 497 sysbus_realize_and_unref(sysbus, &error_fatal); 498 sysbus_mmio_map(sysbus, 0, SONIC_BASE); 499 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(glue, GLUE_IRQ_IN_SONIC)); 500 501 memory_region_init_rom(dp8393x_prom, NULL, "dp8393x-q800.prom", 502 SONIC_PROM_SIZE, &error_fatal); 503 memory_region_add_subregion(get_system_memory(), SONIC_PROM_BASE, 504 dp8393x_prom); 505 506 /* Add MAC address with valid checksum to PROM */ 507 prom = memory_region_get_ram_ptr(dp8393x_prom); 508 checksum = 0; 509 for (i = 0; i < 6; i++) { 510 prom[i] = revbit8(nd_table[0].macaddr.a[i]); 511 checksum ^= prom[i]; 512 } 513 prom[7] = 0xff - checksum; 514 515 /* SCC */ 516 517 dev = qdev_new(TYPE_ESCC); 518 qdev_prop_set_uint32(dev, "disabled", 0); 519 qdev_prop_set_uint32(dev, "frequency", MAC_CLOCK); 520 qdev_prop_set_uint32(dev, "it_shift", 1); 521 qdev_prop_set_bit(dev, "bit_swap", true); 522 qdev_prop_set_chr(dev, "chrA", serial_hd(0)); 523 qdev_prop_set_chr(dev, "chrB", serial_hd(1)); 524 qdev_prop_set_uint32(dev, "chnBtype", 0); 525 qdev_prop_set_uint32(dev, "chnAtype", 0); 526 sysbus = SYS_BUS_DEVICE(dev); 527 sysbus_realize_and_unref(sysbus, &error_fatal); 528 529 /* Logically OR both its IRQs together */ 530 escc_orgate = DEVICE(object_new(TYPE_OR_IRQ)); 531 object_property_set_int(OBJECT(escc_orgate), "num-lines", 2, &error_fatal); 532 qdev_realize_and_unref(escc_orgate, NULL, &error_fatal); 533 sysbus_connect_irq(sysbus, 0, qdev_get_gpio_in(escc_orgate, 0)); 534 sysbus_connect_irq(sysbus, 1, qdev_get_gpio_in(escc_orgate, 1)); 535 qdev_connect_gpio_out(DEVICE(escc_orgate), 0, 536 qdev_get_gpio_in(glue, GLUE_IRQ_IN_ESCC)); 537 sysbus_mmio_map(sysbus, 0, SCC_BASE); 538 539 /* SCSI */ 540 541 dev = qdev_new(TYPE_SYSBUS_ESP); 542 sysbus_esp = SYSBUS_ESP(dev); 543 esp = &sysbus_esp->esp; 544 esp->dma_memory_read = NULL; 545 esp->dma_memory_write = NULL; 546 esp->dma_opaque = NULL; 547 sysbus_esp->it_shift = 4; 548 esp->dma_enabled = 1; 549 550 sysbus = SYS_BUS_DEVICE(dev); 551 sysbus_realize_and_unref(sysbus, &error_fatal); 552 /* SCSI and SCSI data IRQs are negative edge triggered */ 553 sysbus_connect_irq(sysbus, 0, qemu_irq_invert(qdev_get_gpio_in(via2_dev, 554 VIA2_IRQ_SCSI_BIT))); 555 sysbus_connect_irq(sysbus, 1, qemu_irq_invert(qdev_get_gpio_in(via2_dev, 556 VIA2_IRQ_SCSI_DATA_BIT))); 557 sysbus_mmio_map(sysbus, 0, ESP_BASE); 558 sysbus_mmio_map(sysbus, 1, ESP_PDMA); 559 560 scsi_bus_legacy_handle_cmdline(&esp->bus); 561 562 /* SWIM floppy controller */ 563 564 dev = qdev_new(TYPE_SWIM); 565 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 566 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, SWIM_BASE); 567 568 /* NuBus */ 569 570 dev = qdev_new(TYPE_MAC_NUBUS_BRIDGE); 571 qdev_prop_set_uint32(dev, "slot-available-mask", 572 Q800_NUBUS_SLOTS_AVAILABLE); 573 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 574 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 575 MAC_NUBUS_FIRST_SLOT * NUBUS_SUPER_SLOT_SIZE); 576 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, NUBUS_SLOT_BASE + 577 MAC_NUBUS_FIRST_SLOT * NUBUS_SLOT_SIZE); 578 qdev_connect_gpio_out(dev, 9, 579 qdev_get_gpio_in_named(via2_dev, "nubus-irq", 580 VIA2_NUBUS_IRQ_INTVIDEO)); 581 for (i = 1; i < VIA2_NUBUS_IRQ_NB; i++) { 582 qdev_connect_gpio_out(dev, 9 + i, 583 qdev_get_gpio_in_named(via2_dev, "nubus-irq", 584 VIA2_NUBUS_IRQ_9 + i)); 585 } 586 587 /* 588 * Since the framebuffer in slot 0x9 uses a separate IRQ, wire the unused 589 * IRQ via GLUE for use by SONIC Ethernet in classic mode 590 */ 591 qdev_connect_gpio_out(glue, GLUE_IRQ_NUBUS_9, 592 qdev_get_gpio_in_named(via2_dev, "nubus-irq", 593 VIA2_NUBUS_IRQ_9)); 594 595 nubus = &NUBUS_BRIDGE(dev)->bus; 596 597 /* framebuffer in nubus slot #9 */ 598 599 dev = qdev_new(TYPE_NUBUS_MACFB); 600 qdev_prop_set_uint32(dev, "slot", 9); 601 qdev_prop_set_uint32(dev, "width", graphic_width); 602 qdev_prop_set_uint32(dev, "height", graphic_height); 603 qdev_prop_set_uint8(dev, "depth", graphic_depth); 604 if (graphic_width == 1152 && graphic_height == 870) { 605 qdev_prop_set_uint8(dev, "display", MACFB_DISPLAY_APPLE_21_COLOR); 606 } else { 607 qdev_prop_set_uint8(dev, "display", MACFB_DISPLAY_VGA); 608 } 609 qdev_realize_and_unref(dev, BUS(nubus), &error_fatal); 610 611 macfb_mode = (NUBUS_MACFB(dev)->macfb).mode; 612 613 cs = CPU(cpu); 614 if (linux_boot) { 615 uint64_t high; 616 void *param_blob, *param_ptr, *param_rng_seed; 617 618 if (kernel_cmdline) { 619 param_blob = g_malloc(strlen(kernel_cmdline) + 1024); 620 } else { 621 param_blob = g_malloc(1024); 622 } 623 624 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, 625 &elf_entry, NULL, &high, NULL, 1, 626 EM_68K, 0, 0); 627 if (kernel_size < 0) { 628 error_report("could not load kernel '%s'", kernel_filename); 629 exit(1); 630 } 631 stl_phys(cs->as, 4, elf_entry); /* reset initial PC */ 632 parameters_base = (high + 1) & ~1; 633 param_ptr = param_blob; 634 635 BOOTINFO1(param_ptr, BI_MACHTYPE, MACH_MAC); 636 BOOTINFO1(param_ptr, BI_FPUTYPE, FPU_68040); 637 BOOTINFO1(param_ptr, BI_MMUTYPE, MMU_68040); 638 BOOTINFO1(param_ptr, BI_CPUTYPE, CPU_68040); 639 BOOTINFO1(param_ptr, BI_MAC_CPUID, CPUB_68040); 640 BOOTINFO1(param_ptr, BI_MAC_MODEL, MAC_MODEL_Q800); 641 BOOTINFO1(param_ptr, 642 BI_MAC_MEMSIZE, ram_size >> 20); /* in MB */ 643 BOOTINFO2(param_ptr, BI_MEMCHUNK, 0, ram_size); 644 BOOTINFO1(param_ptr, BI_MAC_VADDR, 645 VIDEO_BASE + macfb_mode->offset); 646 BOOTINFO1(param_ptr, BI_MAC_VDEPTH, graphic_depth); 647 BOOTINFO1(param_ptr, BI_MAC_VDIM, 648 (graphic_height << 16) | graphic_width); 649 BOOTINFO1(param_ptr, BI_MAC_VROW, macfb_mode->stride); 650 BOOTINFO1(param_ptr, BI_MAC_SCCBASE, SCC_BASE); 651 652 rom = g_malloc(sizeof(*rom)); 653 memory_region_init_ram_ptr(rom, NULL, "m68k_fake_mac.rom", 654 sizeof(fake_mac_rom), fake_mac_rom); 655 memory_region_set_readonly(rom, true); 656 memory_region_add_subregion(get_system_memory(), MACROM_ADDR, rom); 657 658 if (kernel_cmdline) { 659 BOOTINFOSTR(param_ptr, BI_COMMAND_LINE, 660 kernel_cmdline); 661 } 662 663 /* Pass seed to RNG. */ 664 param_rng_seed = param_ptr; 665 qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); 666 BOOTINFODATA(param_ptr, BI_RNG_SEED, 667 rng_seed, sizeof(rng_seed)); 668 669 /* load initrd */ 670 if (initrd_filename) { 671 initrd_size = get_image_size(initrd_filename); 672 if (initrd_size < 0) { 673 error_report("could not load initial ram disk '%s'", 674 initrd_filename); 675 exit(1); 676 } 677 678 initrd_base = (ram_size - initrd_size) & TARGET_PAGE_MASK; 679 load_image_targphys(initrd_filename, initrd_base, 680 ram_size - initrd_base); 681 BOOTINFO2(param_ptr, BI_RAMDISK, initrd_base, 682 initrd_size); 683 } else { 684 initrd_base = 0; 685 initrd_size = 0; 686 } 687 BOOTINFO0(param_ptr, BI_LAST); 688 rom_add_blob_fixed_as("bootinfo", param_blob, param_ptr - param_blob, 689 parameters_base, cs->as); 690 reset_info->rng_seed = rom_ptr_for_as(cs->as, parameters_base, 691 param_ptr - param_blob) + 692 (param_rng_seed - param_blob); 693 g_free(param_blob); 694 } else { 695 uint8_t *ptr; 696 /* allocate and load BIOS */ 697 rom = g_malloc(sizeof(*rom)); 698 memory_region_init_rom(rom, NULL, "m68k_mac.rom", MACROM_SIZE, 699 &error_abort); 700 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 701 memory_region_add_subregion(get_system_memory(), MACROM_ADDR, rom); 702 703 /* Load MacROM binary */ 704 if (filename) { 705 bios_size = load_image_targphys(filename, MACROM_ADDR, MACROM_SIZE); 706 g_free(filename); 707 } else { 708 bios_size = -1; 709 } 710 711 /* Remove qtest_enabled() check once firmware files are in the tree */ 712 if (!qtest_enabled()) { 713 if (bios_size <= 0 || bios_size > MACROM_SIZE) { 714 error_report("could not load MacROM '%s'", bios_name); 715 exit(1); 716 } 717 718 ptr = rom_ptr(MACROM_ADDR, bios_size); 719 assert(ptr != NULL); 720 stl_phys(cs->as, 0, ldl_p(ptr)); /* reset initial SP */ 721 stl_phys(cs->as, 4, 722 MACROM_ADDR + ldl_p(ptr + 4)); /* reset initial PC */ 723 } 724 } 725 } 726 727 static GlobalProperty hw_compat_q800[] = { 728 { "scsi-hd", "quirk_mode_page_vendor_specific_apple", "on"}, 729 { "scsi-hd", "vendor", " SEAGATE" }, 730 { "scsi-hd", "product", " ST225N" }, 731 { "scsi-hd", "ver", "1.0 " }, 732 { "scsi-cd", "quirk_mode_page_apple_vendor", "on"}, 733 { "scsi-cd", "quirk_mode_sense_rom_use_dbd", "on"}, 734 { "scsi-cd", "quirk_mode_page_vendor_specific_apple", "on"}, 735 { "scsi-cd", "quirk_mode_page_truncated", "on"}, 736 { "scsi-cd", "vendor", "MATSHITA" }, 737 { "scsi-cd", "product", "CD-ROM CR-8005" }, 738 { "scsi-cd", "ver", "1.0k" }, 739 }; 740 static const size_t hw_compat_q800_len = G_N_ELEMENTS(hw_compat_q800); 741 742 static void q800_machine_class_init(ObjectClass *oc, void *data) 743 { 744 MachineClass *mc = MACHINE_CLASS(oc); 745 mc->desc = "Macintosh Quadra 800"; 746 mc->init = q800_init; 747 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); 748 mc->max_cpus = 1; 749 mc->block_default_type = IF_SCSI; 750 mc->default_ram_id = "m68k_mac.ram"; 751 compat_props_add(mc->compat_props, hw_compat_q800, hw_compat_q800_len); 752 } 753 754 static const TypeInfo q800_machine_typeinfo = { 755 .name = MACHINE_TYPE_NAME("q800"), 756 .parent = TYPE_MACHINE, 757 .class_init = q800_machine_class_init, 758 }; 759 760 static void q800_machine_register_types(void) 761 { 762 type_register_static(&q800_machine_typeinfo); 763 type_register_static(&glue_info); 764 } 765 766 type_init(q800_machine_register_types) 767