1 /* 2 * NeXT Cube System Driver 3 * 4 * Copyright (c) 2011 Bryce Lanham 5 * 6 * This code is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published 8 * by the Free Software Foundation; either version 2 of the License, 9 * or (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "exec/hwaddr.h" 14 #include "system/system.h" 15 #include "system/qtest.h" 16 #include "hw/irq.h" 17 #include "hw/m68k/next-cube.h" 18 #include "hw/boards.h" 19 #include "hw/loader.h" 20 #include "hw/scsi/esp.h" 21 #include "hw/sysbus.h" 22 #include "qom/object.h" 23 #include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */ 24 #include "hw/block/fdc.h" 25 #include "hw/misc/empty_slot.h" 26 #include "hw/qdev-properties.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "ui/console.h" 30 #include "target/m68k/cpu.h" 31 #include "migration/vmstate.h" 32 33 /* #define DEBUG_NEXT */ 34 #ifdef DEBUG_NEXT 35 #define DPRINTF(fmt, ...) \ 36 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0) 37 #else 38 #define DPRINTF(fmt, ...) do { } while (0) 39 #endif 40 41 #define ENTRY 0x0100001e 42 #define RAM_SIZE 0x4000000 43 #define ROM_FILE "Rev_2.5_v66.bin" 44 45 typedef struct NeXTRTC { 46 int8_t phase; 47 uint8_t ram[32]; 48 uint8_t command; 49 uint8_t value; 50 uint8_t status; 51 uint8_t control; 52 uint8_t retval; 53 } NeXTRTC; 54 55 #define TYPE_NEXT_SCSI "next-scsi" 56 OBJECT_DECLARE_SIMPLE_TYPE(NeXTSCSI, NEXT_SCSI) 57 58 /* NeXT SCSI Controller */ 59 struct NeXTSCSI { 60 SysBusDevice parent_obj; 61 62 MemoryRegion scsi_mem; 63 64 SysBusESPState sysbus_esp; 65 66 MemoryRegion scsi_csr_mem; 67 uint8_t scsi_csr_1; 68 uint8_t scsi_csr_2; 69 }; 70 71 #define TYPE_NEXT_PC "next-pc" 72 OBJECT_DECLARE_SIMPLE_TYPE(NeXTPC, NEXT_PC) 73 74 /* NeXT Peripheral Controller */ 75 struct NeXTPC { 76 SysBusDevice parent_obj; 77 78 M68kCPU *cpu; 79 80 MemoryRegion floppy_mem; 81 MemoryRegion timer_mem; 82 MemoryRegion dummyen_mem; 83 MemoryRegion mmiomem; 84 MemoryRegion scrmem; 85 86 uint32_t scr1; 87 uint32_t scr2; 88 uint32_t old_scr2; 89 uint32_t int_mask; 90 uint32_t int_status; 91 uint32_t led; 92 93 NeXTSCSI next_scsi; 94 95 qemu_irq scsi_reset; 96 qemu_irq scsi_dma; 97 98 ESCCState escc; 99 100 NeXTRTC rtc; 101 qemu_irq rtc_power_irq; 102 }; 103 104 typedef struct next_dma { 105 uint32_t csr; 106 107 uint32_t saved_next; 108 uint32_t saved_limit; 109 uint32_t saved_start; 110 uint32_t saved_stop; 111 112 uint32_t next; 113 uint32_t limit; 114 uint32_t start; 115 uint32_t stop; 116 117 uint32_t next_initbuf; 118 uint32_t size; 119 } next_dma; 120 121 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube") 122 OBJECT_DECLARE_SIMPLE_TYPE(NeXTState, NEXT_MACHINE) 123 124 struct NeXTState { 125 MachineState parent; 126 127 MemoryRegion rom; 128 MemoryRegion rom2; 129 MemoryRegion dmamem; 130 MemoryRegion bmapm1; 131 MemoryRegion bmapm2; 132 133 next_dma dma[10]; 134 }; 135 136 /* Thanks to NeXT forums for this */ 137 /* 138 static const uint8_t rtc_ram3[32] = { 139 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 140 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00, 141 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00, 142 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13 143 }; 144 */ 145 static const uint8_t rtc_ram2[32] = { 146 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00, 147 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00, 148 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 149 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e, 150 }; 151 152 #define SCR2_RTCLK 0x2 153 #define SCR2_RTDATA 0x4 154 #define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10)) 155 156 static void next_scr2_led_update(NeXTPC *s) 157 { 158 if (s->scr2 & 0x1) { 159 DPRINTF("fault!\n"); 160 s->led++; 161 if (s->led == 10) { 162 DPRINTF("LED flashing, possible fault!\n"); 163 s->led = 0; 164 } 165 } 166 } 167 168 static bool next_rtc_cmd_is_write(uint8_t cmd) 169 { 170 return (cmd >= 0x80 && cmd <= 0x9f) || 171 (cmd == 0xb1); 172 } 173 174 static void next_scr2_rtc_update(NeXTPC *s) 175 { 176 uint8_t old_scr2, scr2_2; 177 NeXTRTC *rtc = &s->rtc; 178 179 old_scr2 = extract32(s->old_scr2, 8, 8); 180 scr2_2 = extract32(s->scr2, 8, 8); 181 182 if (scr2_2 & 0x1) { 183 /* DPRINTF("RTC %x phase %i\n", scr2_2, rtc->phase); */ 184 if (rtc->phase == -1) { 185 rtc->phase = 0; 186 } 187 /* If we are in going down clock... do something */ 188 if (((old_scr2 & SCR2_RTCLK) != (scr2_2 & SCR2_RTCLK)) && 189 ((scr2_2 & SCR2_RTCLK) == 0)) { 190 if (rtc->phase < 8) { 191 rtc->command = (rtc->command << 1) | 192 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 193 194 if (rtc->phase == 7 && !next_rtc_cmd_is_write(rtc->command)) { 195 if (rtc->command <= 0x1f) { 196 /* RAM registers */ 197 rtc->retval = rtc->ram[rtc->command]; 198 } 199 if ((rtc->command >= 0x20) && (rtc->command <= 0x2F)) { 200 /* RTC */ 201 time_t time_h = time(NULL); 202 struct tm *info = localtime(&time_h); 203 rtc->retval = 0; 204 205 switch (rtc->command) { 206 case 0x20: 207 rtc->retval = SCR2_TOBCD(info->tm_sec); 208 break; 209 case 0x21: 210 rtc->retval = SCR2_TOBCD(info->tm_min); 211 break; 212 case 0x22: 213 rtc->retval = SCR2_TOBCD(info->tm_hour); 214 break; 215 case 0x24: 216 rtc->retval = SCR2_TOBCD(info->tm_mday); 217 break; 218 case 0x25: 219 rtc->retval = SCR2_TOBCD((info->tm_mon + 1)); 220 break; 221 case 0x26: 222 rtc->retval = SCR2_TOBCD((info->tm_year - 100)); 223 break; 224 } 225 } 226 if (rtc->command == 0x30) { 227 /* read the status 0x30 */ 228 rtc->retval = rtc->status; 229 } 230 if (rtc->command == 0x31) { 231 /* read the control 0x31 */ 232 rtc->retval = rtc->control; 233 } 234 } 235 } 236 if (rtc->phase >= 8 && rtc->phase < 16) { 237 if (next_rtc_cmd_is_write(rtc->command)) { 238 /* Shift in value to write */ 239 rtc->value = (rtc->value << 1) | 240 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 241 } else { 242 /* Shift out value to read */ 243 qemu_irq rtc_data_in_irq = qdev_get_gpio_in_named( 244 DEVICE(s), "pc-rtc-data-in", 0); 245 246 if (rtc->retval & (0x80 >> (rtc->phase - 8))) { 247 qemu_irq_raise(rtc_data_in_irq); 248 } else { 249 qemu_irq_lower(rtc_data_in_irq); 250 } 251 } 252 } 253 254 rtc->phase++; 255 if (rtc->phase == 16 && next_rtc_cmd_is_write(rtc->command)) { 256 if (rtc->command >= 0x80 && rtc->command <= 0x9f) { 257 /* RAM registers */ 258 rtc->ram[rtc->command - 0x80] = rtc->value; 259 } 260 if (rtc->command == 0xb1) { 261 /* write to 0x30 register */ 262 if (rtc->value & 0x04) { 263 /* clear FTU */ 264 rtc->status = rtc->status & (~0x18); 265 qemu_irq_lower(s->rtc_power_irq); 266 } 267 } 268 } 269 } 270 } else { 271 /* else end or abort */ 272 rtc->phase = -1; 273 rtc->command = 0; 274 rtc->value = 0; 275 } 276 } 277 278 static uint64_t next_mmio_read(void *opaque, hwaddr addr, unsigned size) 279 { 280 NeXTPC *s = NEXT_PC(opaque); 281 uint64_t val; 282 283 switch (addr) { 284 case 0x2000: /* 0x2007000 */ 285 /* DPRINTF("Read INT status: %x\n", s->int_status); */ 286 val = s->int_status; 287 break; 288 289 case 0x2800: /* 0x2007800 */ 290 DPRINTF("MMIO Read INT mask: %x\n", s->int_mask); 291 val = s->int_mask; 292 break; 293 294 case 0x7000 ... 0x7003: /* 0x200c000 */ 295 val = extract32(s->scr1, (4 - (addr - 0x7000) - size) << 3, 296 size << 3); 297 break; 298 299 case 0x8000 ... 0x8003: /* 0x200d000 */ 300 val = extract32(s->scr2, (4 - (addr - 0x8000) - size) << 3, 301 size << 3); 302 break; 303 304 default: 305 val = 0; 306 DPRINTF("MMIO Read @ 0x%"HWADDR_PRIx" size %d\n", addr, size); 307 break; 308 } 309 310 return val; 311 } 312 313 static void next_mmio_write(void *opaque, hwaddr addr, uint64_t val, 314 unsigned size) 315 { 316 NeXTPC *s = NEXT_PC(opaque); 317 318 switch (addr) { 319 case 0x2000: /* 0x2007000 */ 320 DPRINTF("INT Status old: %x new: %x\n", s->int_status, 321 (unsigned int)val); 322 s->int_status = val; 323 break; 324 325 case 0x2800: /* 0x2007800 */ 326 DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, (unsigned int)val); 327 s->int_mask = val; 328 break; 329 330 case 0x7000 ... 0x7003: /* 0x200c000 */ 331 DPRINTF("SCR1 Write: %x\n", (unsigned int)val); 332 s->scr1 = deposit32(s->scr1, (4 - (addr - 0x7000) - size) << 3, 333 size << 3, val); 334 break; 335 336 case 0x8000 ... 0x8003: /* 0x200d000 */ 337 s->scr2 = deposit32(s->scr2, (4 - (addr - 0x8000) - size) << 3, 338 size << 3, val); 339 next_scr2_led_update(s); 340 next_scr2_rtc_update(s); 341 s->old_scr2 = s->scr2; 342 break; 343 344 default: 345 DPRINTF("MMIO Write @ 0x%"HWADDR_PRIx " with 0x%x size %u\n", addr, 346 (unsigned int)val, size); 347 } 348 } 349 350 static const MemoryRegionOps next_mmio_ops = { 351 .read = next_mmio_read, 352 .write = next_mmio_write, 353 .valid.min_access_size = 1, 354 .valid.max_access_size = 4, 355 .endianness = DEVICE_BIG_ENDIAN, 356 }; 357 358 #define SCSICSR_ENABLE 0x01 359 #define SCSICSR_RESET 0x02 /* reset scsi dma */ 360 #define SCSICSR_FIFOFL 0x04 361 #define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */ 362 #define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */ 363 #define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */ 364 365 #define NEXTDMA_SCSI(x) (0x10 + x) 366 #define NEXTDMA_FD(x) (0x10 + x) 367 #define NEXTDMA_ENTX(x) (0x110 + x) 368 #define NEXTDMA_ENRX(x) (0x150 + x) 369 #define NEXTDMA_CSR 0x0 370 #define NEXTDMA_NEXT 0x4000 371 #define NEXTDMA_LIMIT 0x4004 372 #define NEXTDMA_START 0x4008 373 #define NEXTDMA_STOP 0x400c 374 #define NEXTDMA_NEXT_INIT 0x4200 375 #define NEXTDMA_SIZE 0x4204 376 377 static void next_dma_write(void *opaque, hwaddr addr, uint64_t val, 378 unsigned int size) 379 { 380 NeXTState *next_state = NEXT_MACHINE(opaque); 381 382 switch (addr) { 383 case NEXTDMA_ENRX(NEXTDMA_CSR): 384 if (val & DMA_DEV2M) { 385 next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M; 386 } 387 388 if (val & DMA_SETENABLE) { 389 /* DPRINTF("SCSI DMA ENABLE\n"); */ 390 next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE; 391 } 392 if (val & DMA_SETSUPDATE) { 393 next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE; 394 } 395 if (val & DMA_CLRCOMPLETE) { 396 next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE; 397 } 398 399 if (val & DMA_RESET) { 400 next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 401 DMA_ENABLE | DMA_DEV2M); 402 } 403 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 404 break; 405 406 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 407 next_state->dma[NEXTDMA_ENRX].next_initbuf = val; 408 break; 409 410 case NEXTDMA_ENRX(NEXTDMA_NEXT): 411 next_state->dma[NEXTDMA_ENRX].next = val; 412 break; 413 414 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 415 next_state->dma[NEXTDMA_ENRX].limit = val; 416 break; 417 418 case NEXTDMA_SCSI(NEXTDMA_CSR): 419 if (val & DMA_DEV2M) { 420 next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M; 421 } 422 if (val & DMA_SETENABLE) { 423 /* DPRINTF("SCSI DMA ENABLE\n"); */ 424 next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE; 425 } 426 if (val & DMA_SETSUPDATE) { 427 next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE; 428 } 429 if (val & DMA_CLRCOMPLETE) { 430 next_state->dma[NEXTDMA_SCSI].csr &= ~DMA_COMPLETE; 431 } 432 433 if (val & DMA_RESET) { 434 next_state->dma[NEXTDMA_SCSI].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 435 DMA_ENABLE | DMA_DEV2M); 436 /* DPRINTF("SCSI DMA RESET\n"); */ 437 } 438 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 439 break; 440 441 case NEXTDMA_SCSI(NEXTDMA_NEXT): 442 next_state->dma[NEXTDMA_SCSI].next = val; 443 break; 444 445 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 446 next_state->dma[NEXTDMA_SCSI].limit = val; 447 break; 448 449 case NEXTDMA_SCSI(NEXTDMA_START): 450 next_state->dma[NEXTDMA_SCSI].start = val; 451 break; 452 453 case NEXTDMA_SCSI(NEXTDMA_STOP): 454 next_state->dma[NEXTDMA_SCSI].stop = val; 455 break; 456 457 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 458 next_state->dma[NEXTDMA_SCSI].next_initbuf = val; 459 break; 460 461 default: 462 DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)val); 463 } 464 } 465 466 static uint64_t next_dma_read(void *opaque, hwaddr addr, unsigned int size) 467 { 468 NeXTState *next_state = NEXT_MACHINE(opaque); 469 uint64_t val; 470 471 switch (addr) { 472 case NEXTDMA_SCSI(NEXTDMA_CSR): 473 DPRINTF("SCSI DMA CSR READ\n"); 474 val = next_state->dma[NEXTDMA_SCSI].csr; 475 break; 476 477 case NEXTDMA_ENRX(NEXTDMA_CSR): 478 val = next_state->dma[NEXTDMA_ENRX].csr; 479 break; 480 481 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 482 val = next_state->dma[NEXTDMA_ENRX].next_initbuf; 483 break; 484 485 case NEXTDMA_ENRX(NEXTDMA_NEXT): 486 val = next_state->dma[NEXTDMA_ENRX].next; 487 break; 488 489 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 490 val = next_state->dma[NEXTDMA_ENRX].limit; 491 break; 492 493 case NEXTDMA_SCSI(NEXTDMA_NEXT): 494 val = next_state->dma[NEXTDMA_SCSI].next; 495 break; 496 497 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 498 val = next_state->dma[NEXTDMA_SCSI].next_initbuf; 499 break; 500 501 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 502 val = next_state->dma[NEXTDMA_SCSI].limit; 503 break; 504 505 case NEXTDMA_SCSI(NEXTDMA_START): 506 val = next_state->dma[NEXTDMA_SCSI].start; 507 break; 508 509 case NEXTDMA_SCSI(NEXTDMA_STOP): 510 val = next_state->dma[NEXTDMA_SCSI].stop; 511 break; 512 513 default: 514 DPRINTF("DMA read @ %x\n", (unsigned int)addr); 515 val = 0; 516 } 517 518 /* 519 * once the csr's are done, subtract 0x3FEC from the addr, and that will 520 * normalize the upper registers 521 */ 522 523 return val; 524 } 525 526 static const MemoryRegionOps next_dma_ops = { 527 .read = next_dma_read, 528 .write = next_dma_write, 529 .impl.min_access_size = 4, 530 .valid.min_access_size = 4, 531 .valid.max_access_size = 4, 532 .endianness = DEVICE_BIG_ENDIAN, 533 }; 534 535 static void next_irq(void *opaque, int number, int level) 536 { 537 NeXTPC *s = NEXT_PC(opaque); 538 M68kCPU *cpu = s->cpu; 539 int shift = 0; 540 541 /* first switch sets interrupt status */ 542 /* DPRINTF("IRQ %i\n",number); */ 543 switch (number) { 544 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 545 case NEXT_FD_I: 546 shift = 7; 547 break; 548 case NEXT_KBD_I: 549 shift = 3; 550 break; 551 case NEXT_PWR_I: 552 shift = 2; 553 break; 554 case NEXT_ENRX_I: 555 shift = 9; 556 break; 557 case NEXT_ENTX_I: 558 shift = 10; 559 break; 560 case NEXT_SCSI_I: 561 shift = 12; 562 break; 563 case NEXT_CLK_I: 564 shift = 5; 565 break; 566 567 /* level 5 - scc (serial) */ 568 case NEXT_SCC_I: 569 shift = 17; 570 break; 571 572 /* level 6 - audio etherrx/tx dma */ 573 case NEXT_ENTX_DMA_I: 574 shift = 28; 575 break; 576 case NEXT_ENRX_DMA_I: 577 shift = 27; 578 break; 579 case NEXT_SCSI_DMA_I: 580 shift = 26; 581 break; 582 case NEXT_SND_I: 583 shift = 23; 584 break; 585 case NEXT_SCC_DMA_I: 586 shift = 21; 587 break; 588 589 } 590 /* 591 * this HAS to be wrong, the interrupt handlers in mach and together 592 * int_status and int_mask and return if there is a hit 593 */ 594 if (s->int_mask & (1 << shift)) { 595 DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc); 596 /* return; */ 597 } 598 599 /* second switch triggers the correct interrupt */ 600 if (level) { 601 s->int_status |= 1 << shift; 602 603 switch (number) { 604 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 605 case NEXT_FD_I: 606 case NEXT_KBD_I: 607 case NEXT_PWR_I: 608 case NEXT_ENRX_I: 609 case NEXT_ENTX_I: 610 case NEXT_SCSI_I: 611 case NEXT_CLK_I: 612 m68k_set_irq_level(cpu, 3, 27); 613 break; 614 615 /* level 5 - scc (serial) */ 616 case NEXT_SCC_I: 617 m68k_set_irq_level(cpu, 5, 29); 618 break; 619 620 /* level 6 - audio etherrx/tx dma */ 621 case NEXT_ENTX_DMA_I: 622 case NEXT_ENRX_DMA_I: 623 case NEXT_SCSI_DMA_I: 624 case NEXT_SND_I: 625 case NEXT_SCC_DMA_I: 626 m68k_set_irq_level(cpu, 6, 30); 627 break; 628 } 629 } else { 630 s->int_status &= ~(1 << shift); 631 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); 632 } 633 } 634 635 static void nextdma_write(void *opaque, uint8_t *buf, int size, int type) 636 { 637 uint32_t base_addr; 638 int irq = 0; 639 uint8_t align = 16; 640 NeXTState *next_state = NEXT_MACHINE(qdev_get_machine()); 641 642 if (type == NEXTDMA_ENRX || type == NEXTDMA_ENTX) { 643 align = 32; 644 } 645 /* Most DMA is supposedly 16 byte aligned */ 646 if ((size % align) != 0) { 647 size -= size % align; 648 size += align; 649 } 650 651 /* 652 * prom sets the dma start using initbuf while the bootloader uses next 653 * so we check to see if initbuf is 0 654 */ 655 if (next_state->dma[type].next_initbuf == 0) { 656 base_addr = next_state->dma[type].next; 657 } else { 658 base_addr = next_state->dma[type].next_initbuf; 659 } 660 661 cpu_physical_memory_write(base_addr, buf, size); 662 663 next_state->dma[type].next_initbuf = 0; 664 665 /* saved limit is checked to calculate packet size by both, rom and netbsd */ 666 next_state->dma[type].saved_limit = (next_state->dma[type].next + size); 667 next_state->dma[type].saved_next = (next_state->dma[type].next); 668 669 /* 670 * 32 bytes under savedbase seems to be some kind of register 671 * of which the purpose is unknown as of yet 672 */ 673 /* stl_phys(s->rx_dma.base-32,0xFFFFFFFF); */ 674 675 if (!(next_state->dma[type].csr & DMA_SUPDATE)) { 676 next_state->dma[type].next = next_state->dma[type].start; 677 next_state->dma[type].limit = next_state->dma[type].stop; 678 } 679 680 /* Set dma registers and raise an irq */ 681 next_state->dma[type].csr |= DMA_COMPLETE; /* DON'T CHANGE THIS! */ 682 683 switch (type) { 684 case NEXTDMA_SCSI: 685 irq = NEXT_SCSI_DMA_I; 686 break; 687 } 688 689 next_irq(opaque, irq, 1); 690 next_irq(opaque, irq, 0); 691 } 692 693 static void nextscsi_read(void *opaque, uint8_t *buf, int len) 694 { 695 DPRINTF("SCSI READ: %x\n", len); 696 abort(); 697 } 698 699 static void nextscsi_write(void *opaque, uint8_t *buf, int size) 700 { 701 DPRINTF("SCSI WRITE: %i\n", size); 702 nextdma_write(opaque, buf, size, NEXTDMA_SCSI); 703 } 704 705 static void next_scsi_csr_write(void *opaque, hwaddr addr, uint64_t val, 706 unsigned size) 707 { 708 NeXTSCSI *s = NEXT_SCSI(opaque); 709 NeXTPC *pc = NEXT_PC(container_of(s, NeXTPC, next_scsi)); 710 711 switch (addr) { 712 case 0: 713 if (val & SCSICSR_FIFOFL) { 714 DPRINTF("SCSICSR FIFO Flush\n"); 715 /* will have to add another irq to the esp if this is needed */ 716 /* esp_puflush_fifo(esp_g); */ 717 } 718 719 if (val & SCSICSR_ENABLE) { 720 DPRINTF("SCSICSR Enable\n"); 721 /* 722 * qemu_irq_raise(s->scsi_dma); 723 * s->scsi_csr_1 = 0xc0; 724 * s->scsi_csr_1 |= 0x1; 725 * qemu_irq_pulse(s->scsi_dma); 726 */ 727 } 728 /* 729 * else 730 * s->scsi_csr_1 &= ~SCSICSR_ENABLE; 731 */ 732 733 if (val & SCSICSR_RESET) { 734 DPRINTF("SCSICSR Reset\n"); 735 /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */ 736 qemu_irq_raise(pc->scsi_reset); 737 s->scsi_csr_1 &= ~(SCSICSR_INTMASK | 0x80 | 0x1); 738 qemu_irq_lower(pc->scsi_reset); 739 } 740 if (val & SCSICSR_DMADIR) { 741 DPRINTF("SCSICSR DMAdir\n"); 742 } 743 if (val & SCSICSR_CPUDMA) { 744 DPRINTF("SCSICSR CPUDMA\n"); 745 /* qemu_irq_raise(s->scsi_dma); */ 746 pc->int_status |= 0x4000000; 747 } else { 748 /* fprintf(stderr,"SCSICSR CPUDMA disabled\n"); */ 749 pc->int_status &= ~(0x4000000); 750 /* qemu_irq_lower(s->scsi_dma); */ 751 } 752 if (val & SCSICSR_INTMASK) { 753 DPRINTF("SCSICSR INTMASK\n"); 754 /* 755 * int_mask &= ~0x1000; 756 * s->scsi_csr_1 |= val; 757 * s->scsi_csr_1 &= ~SCSICSR_INTMASK; 758 * if (s->scsi_queued) { 759 * s->scsi_queued = 0; 760 * next_irq(s, NEXT_SCSI_I, level); 761 * } 762 */ 763 } else { 764 /* int_mask |= 0x1000; */ 765 } 766 if (val & 0x80) { 767 /* int_mask |= 0x1000; */ 768 /* s->scsi_csr_1 |= 0x80; */ 769 } 770 DPRINTF("SCSICSR1 Write: %"PRIx64 "\n", val); 771 s->scsi_csr_1 = val; 772 break; 773 774 case 1: 775 DPRINTF("SCSICSR2 Write: %"PRIx64 "\n", val); 776 s->scsi_csr_2 = val; 777 break; 778 779 default: 780 g_assert_not_reached(); 781 } 782 } 783 784 static uint64_t next_scsi_csr_read(void *opaque, hwaddr addr, unsigned size) 785 { 786 NeXTSCSI *s = NEXT_SCSI(opaque); 787 uint64_t val; 788 789 switch (addr) { 790 case 0: 791 DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1); 792 val = s->scsi_csr_1; 793 break; 794 795 case 1: 796 DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2); 797 val = s->scsi_csr_2; 798 break; 799 800 default: 801 g_assert_not_reached(); 802 } 803 804 return val; 805 } 806 807 static const MemoryRegionOps next_scsi_csr_ops = { 808 .read = next_scsi_csr_read, 809 .write = next_scsi_csr_write, 810 .valid.min_access_size = 1, 811 .valid.max_access_size = 1, 812 .endianness = DEVICE_BIG_ENDIAN, 813 }; 814 815 static void next_scsi_init(Object *obj) 816 { 817 NeXTSCSI *s = NEXT_SCSI(obj); 818 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 819 820 object_initialize_child(obj, "esp", &s->sysbus_esp, TYPE_SYSBUS_ESP); 821 822 memory_region_init_io(&s->scsi_csr_mem, obj, &next_scsi_csr_ops, 823 s, "csrs", 2); 824 825 memory_region_init(&s->scsi_mem, obj, "next.scsi", 0x40); 826 sysbus_init_mmio(sbd, &s->scsi_mem); 827 } 828 829 static void next_scsi_realize(DeviceState *dev, Error **errp) 830 { 831 NeXTSCSI *s = NEXT_SCSI(dev); 832 SysBusESPState *sysbus_esp; 833 SysBusDevice *sbd; 834 ESPState *esp; 835 NeXTPC *pcdev; 836 837 pcdev = NEXT_PC(container_of(s, NeXTPC, next_scsi)); 838 839 /* ESP */ 840 sysbus_esp = SYSBUS_ESP(&s->sysbus_esp); 841 esp = &sysbus_esp->esp; 842 esp->dma_memory_read = nextscsi_read; 843 esp->dma_memory_write = nextscsi_write; 844 esp->dma_opaque = pcdev; 845 sysbus_esp->it_shift = 0; 846 esp->dma_enabled = 1; 847 sbd = SYS_BUS_DEVICE(sysbus_esp); 848 if (!sysbus_realize(sbd, errp)) { 849 return; 850 } 851 memory_region_add_subregion(&s->scsi_mem, 0x0, 852 sysbus_mmio_get_region(sbd, 0)); 853 854 /* SCSI CSRs */ 855 memory_region_add_subregion(&s->scsi_mem, 0x20, &s->scsi_csr_mem); 856 857 scsi_bus_legacy_handle_cmdline(&s->sysbus_esp.esp.bus); 858 } 859 860 static const VMStateDescription next_scsi_vmstate = { 861 .name = "next-scsi", 862 .version_id = 0, 863 .minimum_version_id = 0, 864 .fields = (const VMStateField[]) { 865 VMSTATE_UINT8(scsi_csr_1, NeXTSCSI), 866 VMSTATE_UINT8(scsi_csr_2, NeXTSCSI), 867 VMSTATE_END_OF_LIST() 868 }, 869 }; 870 871 static void next_scsi_class_init(ObjectClass *klass, void *data) 872 { 873 DeviceClass *dc = DEVICE_CLASS(klass); 874 875 dc->desc = "NeXT SCSI Controller"; 876 dc->realize = next_scsi_realize; 877 dc->vmsd = &next_scsi_vmstate; 878 } 879 880 static const TypeInfo next_scsi_info = { 881 .name = TYPE_NEXT_SCSI, 882 .parent = TYPE_SYS_BUS_DEVICE, 883 .instance_init = next_scsi_init, 884 .instance_size = sizeof(NeXTSCSI), 885 .class_init = next_scsi_class_init, 886 }; 887 888 static void next_floppy_write(void *opaque, hwaddr addr, uint64_t val, 889 unsigned size) 890 { 891 switch (addr) { 892 case 0: 893 DPRINTF("FDCSR Write: %"PRIx64 "\n", val); 894 if (val == 0x0) { 895 /* qemu_irq_raise(s->fd_irq[0]); */ 896 } 897 break; 898 899 default: 900 g_assert_not_reached(); 901 } 902 } 903 904 static uint64_t next_floppy_read(void *opaque, hwaddr addr, unsigned size) 905 { 906 uint64_t val; 907 908 switch (addr) { 909 case 0: 910 DPRINTF("FD read @ %x\n", (unsigned int)addr); 911 val = 0x40 | 0x04 | 0x2 | 0x1; 912 break; 913 914 default: 915 g_assert_not_reached(); 916 } 917 918 return val; 919 } 920 921 static const MemoryRegionOps next_floppy_ops = { 922 .read = next_floppy_read, 923 .write = next_floppy_write, 924 .valid.min_access_size = 1, 925 .valid.max_access_size = 4, 926 .endianness = DEVICE_BIG_ENDIAN, 927 }; 928 929 static void next_timer_write(void *opaque, hwaddr addr, uint64_t val, 930 unsigned size) 931 { 932 switch (addr) { 933 case 0 ... 3: 934 /* Hardware timer latch - not implemented yet */ 935 break; 936 937 default: 938 g_assert_not_reached(); 939 } 940 } 941 942 static uint64_t next_timer_read(void *opaque, hwaddr addr, unsigned size) 943 { 944 uint64_t val; 945 946 switch (addr) { 947 case 0 ... 3: 948 /* 949 * These 4 registers are the hardware timer, not sure which register 950 * is the latch instead of data, but no problems so far. 951 * 952 * Hack: We need to have the LSB change consistently to make it work 953 */ 954 val = extract32(clock(), (4 - addr - size) << 3, 955 size << 3); 956 break; 957 958 default: 959 g_assert_not_reached(); 960 } 961 962 return val; 963 } 964 965 static const MemoryRegionOps next_timer_ops = { 966 .read = next_timer_read, 967 .write = next_timer_write, 968 .valid.min_access_size = 1, 969 .valid.max_access_size = 4, 970 .endianness = DEVICE_BIG_ENDIAN, 971 }; 972 973 static void next_dummy_en_write(void *opaque, hwaddr addr, uint64_t val, 974 unsigned size) 975 { 976 /* Do nothing */ 977 return; 978 } 979 980 static uint64_t next_dummy_en_read(void *opaque, hwaddr addr, unsigned size) 981 { 982 uint64_t val; 983 984 switch (addr) { 985 case 0: 986 /* For now return dummy byte to allow the Ethernet test to timeout */ 987 val = 0xff; 988 break; 989 990 default: 991 val = 0; 992 } 993 994 return val; 995 } 996 997 static const MemoryRegionOps next_dummy_en_ops = { 998 .read = next_dummy_en_read, 999 .write = next_dummy_en_write, 1000 .valid.min_access_size = 1, 1001 .valid.max_access_size = 4, 1002 .endianness = DEVICE_BIG_ENDIAN, 1003 }; 1004 1005 static void next_pc_rtc_data_in_irq(void *opaque, int n, int level) 1006 { 1007 NeXTPC *s = NEXT_PC(opaque); 1008 uint8_t scr2_2 = extract32(s->scr2, 8, 8); 1009 1010 if (level) { 1011 scr2_2 |= SCR2_RTDATA; 1012 } else { 1013 scr2_2 &= ~SCR2_RTDATA; 1014 } 1015 1016 s->scr2 = deposit32(s->scr2, 8, 8, scr2_2); 1017 } 1018 1019 static void next_pc_reset_hold(Object *obj, ResetType type) 1020 { 1021 NeXTPC *s = NEXT_PC(obj); 1022 1023 /* Set internal registers to initial values */ 1024 /* 0x0000XX00 << vital bits */ 1025 s->scr1 = 0x00011102; 1026 s->scr2 = 0x00ff0c80; 1027 s->old_scr2 = s->scr2; 1028 1029 s->rtc.status = 0x90; 1030 1031 /* Load RTC RAM - TODO: provide possibility to load contents from file */ 1032 memcpy(s->rtc.ram, rtc_ram2, 32); 1033 } 1034 1035 static void next_pc_realize(DeviceState *dev, Error **errp) 1036 { 1037 NeXTPC *s = NEXT_PC(dev); 1038 SysBusDevice *sbd; 1039 DeviceState *d; 1040 1041 /* SCSI */ 1042 sbd = SYS_BUS_DEVICE(&s->next_scsi); 1043 if (!sysbus_realize(sbd, errp)) { 1044 return; 1045 } 1046 1047 d = DEVICE(object_resolve_path_component(OBJECT(&s->next_scsi), "esp")); 1048 sysbus_connect_irq(SYS_BUS_DEVICE(d), 0, 1049 qdev_get_gpio_in(DEVICE(s), NEXT_SCSI_I)); 1050 1051 s->scsi_reset = qdev_get_gpio_in(d, 0); 1052 s->scsi_dma = qdev_get_gpio_in(d, 1); 1053 1054 /* ESCC */ 1055 d = DEVICE(&s->escc); 1056 qdev_prop_set_uint32(d, "disabled", 0); 1057 qdev_prop_set_uint32(d, "frequency", 9600 * 384); 1058 qdev_prop_set_uint32(d, "it_shift", 0); 1059 qdev_prop_set_bit(d, "bit_swap", true); 1060 qdev_prop_set_chr(d, "chrB", serial_hd(1)); 1061 qdev_prop_set_chr(d, "chrA", serial_hd(0)); 1062 qdev_prop_set_uint32(d, "chnBtype", escc_serial); 1063 qdev_prop_set_uint32(d, "chnAtype", escc_serial); 1064 1065 sbd = SYS_BUS_DEVICE(d); 1066 if (!sysbus_realize(sbd, errp)) { 1067 return; 1068 } 1069 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(dev, NEXT_SCC_I)); 1070 sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(dev, NEXT_SCC_DMA_I)); 1071 } 1072 1073 static void next_pc_init(Object *obj) 1074 { 1075 NeXTPC *s = NEXT_PC(obj); 1076 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1077 1078 qdev_init_gpio_in(DEVICE(obj), next_irq, NEXT_NUM_IRQS); 1079 1080 memory_region_init_io(&s->mmiomem, OBJECT(s), &next_mmio_ops, s, 1081 "next.mmio", 0x9000); 1082 sysbus_init_mmio(sbd, &s->mmiomem); 1083 1084 memory_region_init_io(&s->dummyen_mem, OBJECT(s), &next_dummy_en_ops, s, 1085 "next.en", 0x20); 1086 sysbus_init_mmio(sbd, &s->dummyen_mem); 1087 1088 object_initialize_child(obj, "next-scsi", &s->next_scsi, TYPE_NEXT_SCSI); 1089 sysbus_init_mmio(sbd, 1090 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->next_scsi), 0)); 1091 1092 memory_region_init_io(&s->floppy_mem, OBJECT(s), &next_floppy_ops, s, 1093 "next.floppy", 4); 1094 sysbus_init_mmio(sbd, &s->floppy_mem); 1095 1096 object_initialize_child(obj, "escc", &s->escc, TYPE_ESCC); 1097 sysbus_init_mmio(sbd, 1098 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->escc), 0)); 1099 1100 memory_region_init_io(&s->timer_mem, OBJECT(s), &next_timer_ops, s, 1101 "next.timer", 4); 1102 sysbus_init_mmio(sbd, &s->timer_mem); 1103 1104 s->rtc_power_irq = qdev_get_gpio_in(DEVICE(obj), NEXT_PWR_I); 1105 qdev_init_gpio_in_named(DEVICE(obj), next_pc_rtc_data_in_irq, 1106 "pc-rtc-data-in", 1); 1107 } 1108 1109 /* 1110 * If the m68k CPU implemented its inbound irq lines as GPIO lines 1111 * rather than via the m68k_set_irq_level() function we would not need 1112 * this cpu link property and could instead provide outbound IRQ lines 1113 * that the board could wire up to the CPU. 1114 */ 1115 static const Property next_pc_properties[] = { 1116 DEFINE_PROP_LINK("cpu", NeXTPC, cpu, TYPE_M68K_CPU, M68kCPU *), 1117 }; 1118 1119 static const VMStateDescription next_rtc_vmstate = { 1120 .name = "next-rtc", 1121 .version_id = 2, 1122 .minimum_version_id = 2, 1123 .fields = (const VMStateField[]) { 1124 VMSTATE_INT8(phase, NeXTRTC), 1125 VMSTATE_UINT8_ARRAY(ram, NeXTRTC, 32), 1126 VMSTATE_UINT8(command, NeXTRTC), 1127 VMSTATE_UINT8(value, NeXTRTC), 1128 VMSTATE_UINT8(status, NeXTRTC), 1129 VMSTATE_UINT8(control, NeXTRTC), 1130 VMSTATE_UINT8(retval, NeXTRTC), 1131 VMSTATE_END_OF_LIST() 1132 }, 1133 }; 1134 1135 static const VMStateDescription next_pc_vmstate = { 1136 .name = "next-pc", 1137 .version_id = 3, 1138 .minimum_version_id = 3, 1139 .fields = (const VMStateField[]) { 1140 VMSTATE_UINT32(scr1, NeXTPC), 1141 VMSTATE_UINT32(scr2, NeXTPC), 1142 VMSTATE_UINT32(old_scr2, NeXTPC), 1143 VMSTATE_UINT32(int_mask, NeXTPC), 1144 VMSTATE_UINT32(int_status, NeXTPC), 1145 VMSTATE_UINT32(led, NeXTPC), 1146 VMSTATE_STRUCT(rtc, NeXTPC, 0, next_rtc_vmstate, NeXTRTC), 1147 VMSTATE_END_OF_LIST() 1148 }, 1149 }; 1150 1151 static void next_pc_class_init(ObjectClass *klass, void *data) 1152 { 1153 DeviceClass *dc = DEVICE_CLASS(klass); 1154 ResettableClass *rc = RESETTABLE_CLASS(klass); 1155 1156 dc->desc = "NeXT Peripheral Controller"; 1157 dc->realize = next_pc_realize; 1158 device_class_set_props(dc, next_pc_properties); 1159 dc->vmsd = &next_pc_vmstate; 1160 rc->phases.hold = next_pc_reset_hold; 1161 } 1162 1163 static const TypeInfo next_pc_info = { 1164 .name = TYPE_NEXT_PC, 1165 .parent = TYPE_SYS_BUS_DEVICE, 1166 .instance_init = next_pc_init, 1167 .instance_size = sizeof(NeXTPC), 1168 .class_init = next_pc_class_init, 1169 }; 1170 1171 static void next_cube_init(MachineState *machine) 1172 { 1173 NeXTState *m = NEXT_MACHINE(machine); 1174 M68kCPU *cpu; 1175 CPUM68KState *env; 1176 MemoryRegion *sysmem = get_system_memory(); 1177 const char *bios_name = machine->firmware ?: ROM_FILE; 1178 DeviceState *pcdev; 1179 1180 /* Initialize the cpu core */ 1181 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 1182 if (!cpu) { 1183 error_report("Unable to find m68k CPU definition"); 1184 exit(1); 1185 } 1186 env = &cpu->env; 1187 1188 /* Initialize CPU registers. */ 1189 env->vbr = 0; 1190 env->sr = 0x2700; 1191 1192 /* Peripheral Controller */ 1193 pcdev = qdev_new(TYPE_NEXT_PC); 1194 object_property_set_link(OBJECT(pcdev), "cpu", OBJECT(cpu), &error_abort); 1195 sysbus_realize_and_unref(SYS_BUS_DEVICE(pcdev), &error_fatal); 1196 1197 /* 64MB RAM starting at 0x04000000 */ 1198 memory_region_add_subregion(sysmem, 0x04000000, machine->ram); 1199 1200 /* Framebuffer */ 1201 sysbus_create_simple(TYPE_NEXTFB, 0x0B000000, NULL); 1202 1203 /* MMIO */ 1204 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02005000); 1205 1206 /* BMAP IO - acts as a catch-all for now */ 1207 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02100000); 1208 1209 /* en network (dummy) */ 1210 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02106000); 1211 1212 /* unknown: Brightness control register? */ 1213 empty_slot_init("next.unknown.0", 0x02110000, 0x10); 1214 /* unknown: Magneto-Optical drive controller? */ 1215 empty_slot_init("next.unknown.1", 0x02112000, 0x10); 1216 1217 /* SCSI */ 1218 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 2, 0x02114000); 1219 /* Floppy */ 1220 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 3, 0x02114108); 1221 /* ESCC */ 1222 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 4, 0x02118000); 1223 1224 /* unknown: Serial clock configuration register? */ 1225 empty_slot_init("next.unknown.2", 0x02118004, 0x10); 1226 1227 /* Timer */ 1228 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 5, 0x0211a000); 1229 1230 /* BMAP memory */ 1231 memory_region_init_ram_flags_nomigrate(&m->bmapm1, NULL, "next.bmapmem", 1232 64, RAM_SHARED, &error_fatal); 1233 memory_region_add_subregion(sysmem, 0x020c0000, &m->bmapm1); 1234 /* The Rev_2.5_v66.bin firmware accesses it at 0x820c0020, too */ 1235 memory_region_init_alias(&m->bmapm2, NULL, "next.bmapmem2", &m->bmapm1, 1236 0x0, 64); 1237 memory_region_add_subregion(sysmem, 0x820c0000, &m->bmapm2); 1238 1239 /* KBD */ 1240 sysbus_create_simple(TYPE_NEXTKBD, 0x0200e000, NULL); 1241 1242 /* Load ROM here */ 1243 memory_region_init_rom(&m->rom, NULL, "next.rom", 0x20000, &error_fatal); 1244 memory_region_add_subregion(sysmem, 0x01000000, &m->rom); 1245 memory_region_init_alias(&m->rom2, NULL, "next.rom2", &m->rom, 0x0, 1246 0x20000); 1247 memory_region_add_subregion(sysmem, 0x0, &m->rom2); 1248 if (load_image_targphys(bios_name, 0x01000000, 0x20000) < 8) { 1249 if (!qtest_enabled()) { 1250 error_report("Failed to load firmware '%s'.", bios_name); 1251 } 1252 } else { 1253 uint8_t *ptr; 1254 /* Initial PC is always at offset 4 in firmware binaries */ 1255 ptr = rom_ptr(0x01000004, 4); 1256 g_assert(ptr != NULL); 1257 env->pc = ldl_be_p(ptr); 1258 if (env->pc >= 0x01020000) { 1259 error_report("'%s' does not seem to be a valid firmware image.", 1260 bios_name); 1261 exit(1); 1262 } 1263 } 1264 1265 /* DMA */ 1266 memory_region_init_io(&m->dmamem, NULL, &next_dma_ops, machine, 1267 "next.dma", 0x5000); 1268 memory_region_add_subregion(sysmem, 0x02000000, &m->dmamem); 1269 } 1270 1271 static void next_machine_class_init(ObjectClass *oc, void *data) 1272 { 1273 MachineClass *mc = MACHINE_CLASS(oc); 1274 1275 mc->desc = "NeXT Cube"; 1276 mc->init = next_cube_init; 1277 mc->block_default_type = IF_SCSI; 1278 mc->default_ram_size = RAM_SIZE; 1279 mc->default_ram_id = "next.ram"; 1280 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); 1281 mc->no_cdrom = true; 1282 } 1283 1284 static const TypeInfo next_typeinfo = { 1285 .name = TYPE_NEXT_MACHINE, 1286 .parent = TYPE_MACHINE, 1287 .class_init = next_machine_class_init, 1288 .instance_size = sizeof(NeXTState), 1289 }; 1290 1291 static void next_register_type(void) 1292 { 1293 type_register_static(&next_typeinfo); 1294 type_register_static(&next_pc_info); 1295 type_register_static(&next_scsi_info); 1296 } 1297 1298 type_init(next_register_type) 1299