1 /* 2 * NeXT Cube System Driver 3 * 4 * Copyright (c) 2011 Bryce Lanham 5 * 6 * This code is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published 8 * by the Free Software Foundation; either version 2 of the License, 9 * or (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "exec/hwaddr.h" 14 #include "system/system.h" 15 #include "system/qtest.h" 16 #include "hw/irq.h" 17 #include "hw/m68k/next-cube.h" 18 #include "hw/boards.h" 19 #include "hw/loader.h" 20 #include "hw/scsi/esp.h" 21 #include "hw/sysbus.h" 22 #include "qom/object.h" 23 #include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */ 24 #include "hw/block/fdc.h" 25 #include "hw/misc/empty_slot.h" 26 #include "hw/qdev-properties.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "ui/console.h" 30 #include "target/m68k/cpu.h" 31 #include "migration/vmstate.h" 32 33 /* #define DEBUG_NEXT */ 34 #ifdef DEBUG_NEXT 35 #define DPRINTF(fmt, ...) \ 36 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0) 37 #else 38 #define DPRINTF(fmt, ...) do { } while (0) 39 #endif 40 41 #define ENTRY 0x0100001e 42 #define RAM_SIZE 0x4000000 43 #define ROM_FILE "Rev_2.5_v66.bin" 44 45 46 #define TYPE_NEXT_RTC "next-rtc" 47 OBJECT_DECLARE_SIMPLE_TYPE(NeXTRTC, NEXT_RTC) 48 49 struct NeXTRTC { 50 SysBusDevice parent_obj; 51 52 int8_t phase; 53 uint8_t ram[32]; 54 uint8_t command; 55 uint8_t value; 56 uint8_t status; 57 uint8_t control; 58 uint8_t retval; 59 60 qemu_irq data_out_irq; 61 }; 62 63 #define TYPE_NEXT_SCSI "next-scsi" 64 OBJECT_DECLARE_SIMPLE_TYPE(NeXTSCSI, NEXT_SCSI) 65 66 /* NeXT SCSI Controller */ 67 struct NeXTSCSI { 68 SysBusDevice parent_obj; 69 70 MemoryRegion scsi_mem; 71 72 SysBusESPState sysbus_esp; 73 74 MemoryRegion scsi_csr_mem; 75 uint8_t scsi_csr_1; 76 uint8_t scsi_csr_2; 77 }; 78 79 #define TYPE_NEXT_PC "next-pc" 80 OBJECT_DECLARE_SIMPLE_TYPE(NeXTPC, NEXT_PC) 81 82 /* NeXT Peripheral Controller */ 83 struct NeXTPC { 84 SysBusDevice parent_obj; 85 86 M68kCPU *cpu; 87 88 MemoryRegion floppy_mem; 89 MemoryRegion timer_mem; 90 MemoryRegion dummyen_mem; 91 MemoryRegion mmiomem; 92 MemoryRegion scrmem; 93 94 uint32_t scr1; 95 uint32_t scr2; 96 uint32_t old_scr2; 97 uint32_t int_mask; 98 uint32_t int_status; 99 uint32_t led; 100 101 NeXTSCSI next_scsi; 102 103 qemu_irq scsi_reset; 104 qemu_irq scsi_dma; 105 106 ESCCState escc; 107 108 NeXTRTC rtc; 109 qemu_irq rtc_power_irq; 110 qemu_irq rtc_data_irq; 111 qemu_irq rtc_cmd_reset_irq; 112 }; 113 114 typedef struct next_dma { 115 uint32_t csr; 116 117 uint32_t saved_next; 118 uint32_t saved_limit; 119 uint32_t saved_start; 120 uint32_t saved_stop; 121 122 uint32_t next; 123 uint32_t limit; 124 uint32_t start; 125 uint32_t stop; 126 127 uint32_t next_initbuf; 128 uint32_t size; 129 } next_dma; 130 131 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube") 132 OBJECT_DECLARE_SIMPLE_TYPE(NeXTState, NEXT_MACHINE) 133 134 struct NeXTState { 135 MachineState parent; 136 137 MemoryRegion rom; 138 MemoryRegion rom2; 139 MemoryRegion dmamem; 140 MemoryRegion bmapm1; 141 MemoryRegion bmapm2; 142 143 next_dma dma[10]; 144 }; 145 146 /* Thanks to NeXT forums for this */ 147 /* 148 static const uint8_t rtc_ram3[32] = { 149 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 150 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00, 151 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00, 152 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13 153 }; 154 */ 155 static const uint8_t rtc_ram2[32] = { 156 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00, 157 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00, 158 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 159 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e, 160 }; 161 162 #define SCR2_RTCLK 0x2 163 #define SCR2_RTDATA 0x4 164 #define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10)) 165 166 static void next_scr2_led_update(NeXTPC *s) 167 { 168 if (s->scr2 & 0x1) { 169 DPRINTF("fault!\n"); 170 s->led++; 171 if (s->led == 10) { 172 DPRINTF("LED flashing, possible fault!\n"); 173 s->led = 0; 174 } 175 } 176 } 177 178 static bool next_rtc_cmd_is_write(uint8_t cmd) 179 { 180 return (cmd >= 0x80 && cmd <= 0x9f) || 181 (cmd == 0xb1); 182 } 183 184 static void next_rtc_data_in_irq(void *opaque, int n, int level) 185 { 186 NeXTRTC *rtc = NEXT_RTC(opaque); 187 NeXTPC *s = NEXT_PC(container_of(rtc, NeXTPC, rtc)); 188 189 if (rtc->phase < 8) { 190 rtc->command = (rtc->command << 1) | level; 191 192 if (rtc->phase == 7 && !next_rtc_cmd_is_write(rtc->command)) { 193 if (rtc->command <= 0x1f) { 194 /* RAM registers */ 195 rtc->retval = rtc->ram[rtc->command]; 196 } 197 if ((rtc->command >= 0x20) && (rtc->command <= 0x2f)) { 198 /* RTC */ 199 time_t time_h = time(NULL); 200 struct tm *info = localtime(&time_h); 201 rtc->retval = 0; 202 203 switch (rtc->command) { 204 case 0x20: 205 rtc->retval = SCR2_TOBCD(info->tm_sec); 206 break; 207 case 0x21: 208 rtc->retval = SCR2_TOBCD(info->tm_min); 209 break; 210 case 0x22: 211 rtc->retval = SCR2_TOBCD(info->tm_hour); 212 break; 213 case 0x24: 214 rtc->retval = SCR2_TOBCD(info->tm_mday); 215 break; 216 case 0x25: 217 rtc->retval = SCR2_TOBCD((info->tm_mon + 1)); 218 break; 219 case 0x26: 220 rtc->retval = SCR2_TOBCD((info->tm_year - 100)); 221 break; 222 } 223 } 224 if (rtc->command == 0x30) { 225 /* read the status 0x30 */ 226 rtc->retval = rtc->status; 227 } 228 if (rtc->command == 0x31) { 229 /* read the control 0x31 */ 230 rtc->retval = rtc->control; 231 } 232 } 233 } 234 if (rtc->phase >= 8 && rtc->phase < 16) { 235 if (next_rtc_cmd_is_write(rtc->command)) { 236 /* Shift in value to write */ 237 rtc->value = (rtc->value << 1) | level; 238 } else { 239 /* Shift out value to read */ 240 if (rtc->retval & (0x80 >> (rtc->phase - 8))) { 241 qemu_irq_raise(rtc->data_out_irq); 242 } else { 243 qemu_irq_lower(rtc->data_out_irq); 244 } 245 } 246 } 247 248 rtc->phase++; 249 if (rtc->phase == 16 && next_rtc_cmd_is_write(rtc->command)) { 250 if (rtc->command >= 0x80 && rtc->command <= 0x9f) { 251 /* RAM registers */ 252 rtc->ram[rtc->command - 0x80] = rtc->value; 253 } 254 if (rtc->command == 0xb1) { 255 /* write to 0x30 register */ 256 if (rtc->value & 0x04) { 257 /* clear FTU */ 258 rtc->status = rtc->status & (~0x18); 259 qemu_irq_lower(s->rtc_power_irq); 260 } 261 } 262 } 263 } 264 265 static void next_scr2_rtc_update(NeXTPC *s) 266 { 267 uint8_t old_scr2, scr2_2; 268 269 old_scr2 = extract32(s->old_scr2, 8, 8); 270 scr2_2 = extract32(s->scr2, 8, 8); 271 272 if (scr2_2 & 0x1) { 273 /* DPRINTF("RTC %x phase %i\n", scr2_2, rtc->phase); */ 274 /* If we are in going down clock... do something */ 275 if (((old_scr2 & SCR2_RTCLK) != (scr2_2 & SCR2_RTCLK)) && 276 ((scr2_2 & SCR2_RTCLK) == 0)) { 277 if (scr2_2 & SCR2_RTDATA) { 278 qemu_irq_raise(s->rtc_data_irq); 279 } else { 280 qemu_irq_lower(s->rtc_data_irq); 281 } 282 } 283 } else { 284 /* else end or abort */ 285 qemu_irq_raise(s->rtc_cmd_reset_irq); 286 } 287 } 288 289 static uint64_t next_mmio_read(void *opaque, hwaddr addr, unsigned size) 290 { 291 NeXTPC *s = NEXT_PC(opaque); 292 uint64_t val; 293 294 switch (addr) { 295 case 0x2000: /* 0x2007000 */ 296 /* DPRINTF("Read INT status: %x\n", s->int_status); */ 297 val = s->int_status; 298 break; 299 300 case 0x2800: /* 0x2007800 */ 301 DPRINTF("MMIO Read INT mask: %x\n", s->int_mask); 302 val = s->int_mask; 303 break; 304 305 case 0x7000 ... 0x7003: /* 0x200c000 */ 306 val = extract32(s->scr1, (4 - (addr - 0x7000) - size) << 3, 307 size << 3); 308 break; 309 310 case 0x8000 ... 0x8003: /* 0x200d000 */ 311 val = extract32(s->scr2, (4 - (addr - 0x8000) - size) << 3, 312 size << 3); 313 break; 314 315 default: 316 val = 0; 317 DPRINTF("MMIO Read @ 0x%"HWADDR_PRIx" size %d\n", addr, size); 318 break; 319 } 320 321 return val; 322 } 323 324 static void next_mmio_write(void *opaque, hwaddr addr, uint64_t val, 325 unsigned size) 326 { 327 NeXTPC *s = NEXT_PC(opaque); 328 329 switch (addr) { 330 case 0x2000: /* 0x2007000 */ 331 DPRINTF("INT Status old: %x new: %x\n", s->int_status, 332 (unsigned int)val); 333 s->int_status = val; 334 break; 335 336 case 0x2800: /* 0x2007800 */ 337 DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, (unsigned int)val); 338 s->int_mask = val; 339 break; 340 341 case 0x7000 ... 0x7003: /* 0x200c000 */ 342 DPRINTF("SCR1 Write: %x\n", (unsigned int)val); 343 s->scr1 = deposit32(s->scr1, (4 - (addr - 0x7000) - size) << 3, 344 size << 3, val); 345 break; 346 347 case 0x8000 ... 0x8003: /* 0x200d000 */ 348 s->scr2 = deposit32(s->scr2, (4 - (addr - 0x8000) - size) << 3, 349 size << 3, val); 350 next_scr2_led_update(s); 351 next_scr2_rtc_update(s); 352 s->old_scr2 = s->scr2; 353 break; 354 355 default: 356 DPRINTF("MMIO Write @ 0x%"HWADDR_PRIx " with 0x%x size %u\n", addr, 357 (unsigned int)val, size); 358 } 359 } 360 361 static const MemoryRegionOps next_mmio_ops = { 362 .read = next_mmio_read, 363 .write = next_mmio_write, 364 .valid.min_access_size = 1, 365 .valid.max_access_size = 4, 366 .endianness = DEVICE_BIG_ENDIAN, 367 }; 368 369 #define SCSICSR_ENABLE 0x01 370 #define SCSICSR_RESET 0x02 /* reset scsi dma */ 371 #define SCSICSR_FIFOFL 0x04 372 #define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */ 373 #define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */ 374 #define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */ 375 376 #define NEXTDMA_SCSI(x) (0x10 + x) 377 #define NEXTDMA_FD(x) (0x10 + x) 378 #define NEXTDMA_ENTX(x) (0x110 + x) 379 #define NEXTDMA_ENRX(x) (0x150 + x) 380 #define NEXTDMA_CSR 0x0 381 #define NEXTDMA_NEXT 0x4000 382 #define NEXTDMA_LIMIT 0x4004 383 #define NEXTDMA_START 0x4008 384 #define NEXTDMA_STOP 0x400c 385 #define NEXTDMA_NEXT_INIT 0x4200 386 #define NEXTDMA_SIZE 0x4204 387 388 static void next_dma_write(void *opaque, hwaddr addr, uint64_t val, 389 unsigned int size) 390 { 391 NeXTState *next_state = NEXT_MACHINE(opaque); 392 393 switch (addr) { 394 case NEXTDMA_ENRX(NEXTDMA_CSR): 395 if (val & DMA_DEV2M) { 396 next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M; 397 } 398 399 if (val & DMA_SETENABLE) { 400 /* DPRINTF("SCSI DMA ENABLE\n"); */ 401 next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE; 402 } 403 if (val & DMA_SETSUPDATE) { 404 next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE; 405 } 406 if (val & DMA_CLRCOMPLETE) { 407 next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE; 408 } 409 410 if (val & DMA_RESET) { 411 next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 412 DMA_ENABLE | DMA_DEV2M); 413 } 414 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 415 break; 416 417 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 418 next_state->dma[NEXTDMA_ENRX].next_initbuf = val; 419 break; 420 421 case NEXTDMA_ENRX(NEXTDMA_NEXT): 422 next_state->dma[NEXTDMA_ENRX].next = val; 423 break; 424 425 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 426 next_state->dma[NEXTDMA_ENRX].limit = val; 427 break; 428 429 case NEXTDMA_SCSI(NEXTDMA_CSR): 430 if (val & DMA_DEV2M) { 431 next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M; 432 } 433 if (val & DMA_SETENABLE) { 434 /* DPRINTF("SCSI DMA ENABLE\n"); */ 435 next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE; 436 } 437 if (val & DMA_SETSUPDATE) { 438 next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE; 439 } 440 if (val & DMA_CLRCOMPLETE) { 441 next_state->dma[NEXTDMA_SCSI].csr &= ~DMA_COMPLETE; 442 } 443 444 if (val & DMA_RESET) { 445 next_state->dma[NEXTDMA_SCSI].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 446 DMA_ENABLE | DMA_DEV2M); 447 /* DPRINTF("SCSI DMA RESET\n"); */ 448 } 449 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 450 break; 451 452 case NEXTDMA_SCSI(NEXTDMA_NEXT): 453 next_state->dma[NEXTDMA_SCSI].next = val; 454 break; 455 456 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 457 next_state->dma[NEXTDMA_SCSI].limit = val; 458 break; 459 460 case NEXTDMA_SCSI(NEXTDMA_START): 461 next_state->dma[NEXTDMA_SCSI].start = val; 462 break; 463 464 case NEXTDMA_SCSI(NEXTDMA_STOP): 465 next_state->dma[NEXTDMA_SCSI].stop = val; 466 break; 467 468 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 469 next_state->dma[NEXTDMA_SCSI].next_initbuf = val; 470 break; 471 472 default: 473 DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)val); 474 } 475 } 476 477 static uint64_t next_dma_read(void *opaque, hwaddr addr, unsigned int size) 478 { 479 NeXTState *next_state = NEXT_MACHINE(opaque); 480 uint64_t val; 481 482 switch (addr) { 483 case NEXTDMA_SCSI(NEXTDMA_CSR): 484 DPRINTF("SCSI DMA CSR READ\n"); 485 val = next_state->dma[NEXTDMA_SCSI].csr; 486 break; 487 488 case NEXTDMA_ENRX(NEXTDMA_CSR): 489 val = next_state->dma[NEXTDMA_ENRX].csr; 490 break; 491 492 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 493 val = next_state->dma[NEXTDMA_ENRX].next_initbuf; 494 break; 495 496 case NEXTDMA_ENRX(NEXTDMA_NEXT): 497 val = next_state->dma[NEXTDMA_ENRX].next; 498 break; 499 500 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 501 val = next_state->dma[NEXTDMA_ENRX].limit; 502 break; 503 504 case NEXTDMA_SCSI(NEXTDMA_NEXT): 505 val = next_state->dma[NEXTDMA_SCSI].next; 506 break; 507 508 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 509 val = next_state->dma[NEXTDMA_SCSI].next_initbuf; 510 break; 511 512 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 513 val = next_state->dma[NEXTDMA_SCSI].limit; 514 break; 515 516 case NEXTDMA_SCSI(NEXTDMA_START): 517 val = next_state->dma[NEXTDMA_SCSI].start; 518 break; 519 520 case NEXTDMA_SCSI(NEXTDMA_STOP): 521 val = next_state->dma[NEXTDMA_SCSI].stop; 522 break; 523 524 default: 525 DPRINTF("DMA read @ %x\n", (unsigned int)addr); 526 val = 0; 527 } 528 529 /* 530 * once the csr's are done, subtract 0x3FEC from the addr, and that will 531 * normalize the upper registers 532 */ 533 534 return val; 535 } 536 537 static const MemoryRegionOps next_dma_ops = { 538 .read = next_dma_read, 539 .write = next_dma_write, 540 .impl.min_access_size = 4, 541 .valid.min_access_size = 4, 542 .valid.max_access_size = 4, 543 .endianness = DEVICE_BIG_ENDIAN, 544 }; 545 546 static void next_irq(void *opaque, int number, int level) 547 { 548 NeXTPC *s = NEXT_PC(opaque); 549 M68kCPU *cpu = s->cpu; 550 int shift = 0; 551 552 /* first switch sets interrupt status */ 553 /* DPRINTF("IRQ %i\n",number); */ 554 switch (number) { 555 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 556 case NEXT_FD_I: 557 shift = 7; 558 break; 559 case NEXT_KBD_I: 560 shift = 3; 561 break; 562 case NEXT_PWR_I: 563 shift = 2; 564 break; 565 case NEXT_ENRX_I: 566 shift = 9; 567 break; 568 case NEXT_ENTX_I: 569 shift = 10; 570 break; 571 case NEXT_SCSI_I: 572 shift = 12; 573 break; 574 case NEXT_CLK_I: 575 shift = 5; 576 break; 577 578 /* level 5 - scc (serial) */ 579 case NEXT_SCC_I: 580 shift = 17; 581 break; 582 583 /* level 6 - audio etherrx/tx dma */ 584 case NEXT_ENTX_DMA_I: 585 shift = 28; 586 break; 587 case NEXT_ENRX_DMA_I: 588 shift = 27; 589 break; 590 case NEXT_SCSI_DMA_I: 591 shift = 26; 592 break; 593 case NEXT_SND_I: 594 shift = 23; 595 break; 596 case NEXT_SCC_DMA_I: 597 shift = 21; 598 break; 599 600 } 601 /* 602 * this HAS to be wrong, the interrupt handlers in mach and together 603 * int_status and int_mask and return if there is a hit 604 */ 605 if (s->int_mask & (1 << shift)) { 606 DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc); 607 /* return; */ 608 } 609 610 /* second switch triggers the correct interrupt */ 611 if (level) { 612 s->int_status |= 1 << shift; 613 614 switch (number) { 615 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 616 case NEXT_FD_I: 617 case NEXT_KBD_I: 618 case NEXT_PWR_I: 619 case NEXT_ENRX_I: 620 case NEXT_ENTX_I: 621 case NEXT_SCSI_I: 622 case NEXT_CLK_I: 623 m68k_set_irq_level(cpu, 3, 27); 624 break; 625 626 /* level 5 - scc (serial) */ 627 case NEXT_SCC_I: 628 m68k_set_irq_level(cpu, 5, 29); 629 break; 630 631 /* level 6 - audio etherrx/tx dma */ 632 case NEXT_ENTX_DMA_I: 633 case NEXT_ENRX_DMA_I: 634 case NEXT_SCSI_DMA_I: 635 case NEXT_SND_I: 636 case NEXT_SCC_DMA_I: 637 m68k_set_irq_level(cpu, 6, 30); 638 break; 639 } 640 } else { 641 s->int_status &= ~(1 << shift); 642 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); 643 } 644 } 645 646 static void nextdma_write(void *opaque, uint8_t *buf, int size, int type) 647 { 648 uint32_t base_addr; 649 int irq = 0; 650 uint8_t align = 16; 651 NeXTState *next_state = NEXT_MACHINE(qdev_get_machine()); 652 653 if (type == NEXTDMA_ENRX || type == NEXTDMA_ENTX) { 654 align = 32; 655 } 656 /* Most DMA is supposedly 16 byte aligned */ 657 if ((size % align) != 0) { 658 size -= size % align; 659 size += align; 660 } 661 662 /* 663 * prom sets the dma start using initbuf while the bootloader uses next 664 * so we check to see if initbuf is 0 665 */ 666 if (next_state->dma[type].next_initbuf == 0) { 667 base_addr = next_state->dma[type].next; 668 } else { 669 base_addr = next_state->dma[type].next_initbuf; 670 } 671 672 cpu_physical_memory_write(base_addr, buf, size); 673 674 next_state->dma[type].next_initbuf = 0; 675 676 /* saved limit is checked to calculate packet size by both, rom and netbsd */ 677 next_state->dma[type].saved_limit = (next_state->dma[type].next + size); 678 next_state->dma[type].saved_next = (next_state->dma[type].next); 679 680 /* 681 * 32 bytes under savedbase seems to be some kind of register 682 * of which the purpose is unknown as of yet 683 */ 684 /* stl_phys(s->rx_dma.base-32,0xFFFFFFFF); */ 685 686 if (!(next_state->dma[type].csr & DMA_SUPDATE)) { 687 next_state->dma[type].next = next_state->dma[type].start; 688 next_state->dma[type].limit = next_state->dma[type].stop; 689 } 690 691 /* Set dma registers and raise an irq */ 692 next_state->dma[type].csr |= DMA_COMPLETE; /* DON'T CHANGE THIS! */ 693 694 switch (type) { 695 case NEXTDMA_SCSI: 696 irq = NEXT_SCSI_DMA_I; 697 break; 698 } 699 700 next_irq(opaque, irq, 1); 701 next_irq(opaque, irq, 0); 702 } 703 704 static void nextscsi_read(void *opaque, uint8_t *buf, int len) 705 { 706 DPRINTF("SCSI READ: %x\n", len); 707 abort(); 708 } 709 710 static void nextscsi_write(void *opaque, uint8_t *buf, int size) 711 { 712 DPRINTF("SCSI WRITE: %i\n", size); 713 nextdma_write(opaque, buf, size, NEXTDMA_SCSI); 714 } 715 716 static void next_scsi_csr_write(void *opaque, hwaddr addr, uint64_t val, 717 unsigned size) 718 { 719 NeXTSCSI *s = NEXT_SCSI(opaque); 720 NeXTPC *pc = NEXT_PC(container_of(s, NeXTPC, next_scsi)); 721 722 switch (addr) { 723 case 0: 724 if (val & SCSICSR_FIFOFL) { 725 DPRINTF("SCSICSR FIFO Flush\n"); 726 /* will have to add another irq to the esp if this is needed */ 727 /* esp_puflush_fifo(esp_g); */ 728 } 729 730 if (val & SCSICSR_ENABLE) { 731 DPRINTF("SCSICSR Enable\n"); 732 /* 733 * qemu_irq_raise(s->scsi_dma); 734 * s->scsi_csr_1 = 0xc0; 735 * s->scsi_csr_1 |= 0x1; 736 * qemu_irq_pulse(s->scsi_dma); 737 */ 738 } 739 /* 740 * else 741 * s->scsi_csr_1 &= ~SCSICSR_ENABLE; 742 */ 743 744 if (val & SCSICSR_RESET) { 745 DPRINTF("SCSICSR Reset\n"); 746 /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */ 747 qemu_irq_raise(pc->scsi_reset); 748 s->scsi_csr_1 &= ~(SCSICSR_INTMASK | 0x80 | 0x1); 749 qemu_irq_lower(pc->scsi_reset); 750 } 751 if (val & SCSICSR_DMADIR) { 752 DPRINTF("SCSICSR DMAdir\n"); 753 } 754 if (val & SCSICSR_CPUDMA) { 755 DPRINTF("SCSICSR CPUDMA\n"); 756 /* qemu_irq_raise(s->scsi_dma); */ 757 pc->int_status |= 0x4000000; 758 } else { 759 /* fprintf(stderr,"SCSICSR CPUDMA disabled\n"); */ 760 pc->int_status &= ~(0x4000000); 761 /* qemu_irq_lower(s->scsi_dma); */ 762 } 763 if (val & SCSICSR_INTMASK) { 764 DPRINTF("SCSICSR INTMASK\n"); 765 /* 766 * int_mask &= ~0x1000; 767 * s->scsi_csr_1 |= val; 768 * s->scsi_csr_1 &= ~SCSICSR_INTMASK; 769 * if (s->scsi_queued) { 770 * s->scsi_queued = 0; 771 * next_irq(s, NEXT_SCSI_I, level); 772 * } 773 */ 774 } else { 775 /* int_mask |= 0x1000; */ 776 } 777 if (val & 0x80) { 778 /* int_mask |= 0x1000; */ 779 /* s->scsi_csr_1 |= 0x80; */ 780 } 781 DPRINTF("SCSICSR1 Write: %"PRIx64 "\n", val); 782 s->scsi_csr_1 = val; 783 break; 784 785 case 1: 786 DPRINTF("SCSICSR2 Write: %"PRIx64 "\n", val); 787 s->scsi_csr_2 = val; 788 break; 789 790 default: 791 g_assert_not_reached(); 792 } 793 } 794 795 static uint64_t next_scsi_csr_read(void *opaque, hwaddr addr, unsigned size) 796 { 797 NeXTSCSI *s = NEXT_SCSI(opaque); 798 uint64_t val; 799 800 switch (addr) { 801 case 0: 802 DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1); 803 val = s->scsi_csr_1; 804 break; 805 806 case 1: 807 DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2); 808 val = s->scsi_csr_2; 809 break; 810 811 default: 812 g_assert_not_reached(); 813 } 814 815 return val; 816 } 817 818 static const MemoryRegionOps next_scsi_csr_ops = { 819 .read = next_scsi_csr_read, 820 .write = next_scsi_csr_write, 821 .valid.min_access_size = 1, 822 .valid.max_access_size = 1, 823 .endianness = DEVICE_BIG_ENDIAN, 824 }; 825 826 static void next_scsi_init(Object *obj) 827 { 828 NeXTSCSI *s = NEXT_SCSI(obj); 829 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 830 831 object_initialize_child(obj, "esp", &s->sysbus_esp, TYPE_SYSBUS_ESP); 832 833 memory_region_init_io(&s->scsi_csr_mem, obj, &next_scsi_csr_ops, 834 s, "csrs", 2); 835 836 memory_region_init(&s->scsi_mem, obj, "next.scsi", 0x40); 837 sysbus_init_mmio(sbd, &s->scsi_mem); 838 } 839 840 static void next_scsi_realize(DeviceState *dev, Error **errp) 841 { 842 NeXTSCSI *s = NEXT_SCSI(dev); 843 SysBusESPState *sysbus_esp; 844 SysBusDevice *sbd; 845 ESPState *esp; 846 NeXTPC *pcdev; 847 848 pcdev = NEXT_PC(container_of(s, NeXTPC, next_scsi)); 849 850 /* ESP */ 851 sysbus_esp = SYSBUS_ESP(&s->sysbus_esp); 852 esp = &sysbus_esp->esp; 853 esp->dma_memory_read = nextscsi_read; 854 esp->dma_memory_write = nextscsi_write; 855 esp->dma_opaque = pcdev; 856 sysbus_esp->it_shift = 0; 857 esp->dma_enabled = 1; 858 sbd = SYS_BUS_DEVICE(sysbus_esp); 859 if (!sysbus_realize(sbd, errp)) { 860 return; 861 } 862 memory_region_add_subregion(&s->scsi_mem, 0x0, 863 sysbus_mmio_get_region(sbd, 0)); 864 865 /* SCSI CSRs */ 866 memory_region_add_subregion(&s->scsi_mem, 0x20, &s->scsi_csr_mem); 867 868 scsi_bus_legacy_handle_cmdline(&s->sysbus_esp.esp.bus); 869 } 870 871 static const VMStateDescription next_scsi_vmstate = { 872 .name = "next-scsi", 873 .version_id = 0, 874 .minimum_version_id = 0, 875 .fields = (const VMStateField[]) { 876 VMSTATE_UINT8(scsi_csr_1, NeXTSCSI), 877 VMSTATE_UINT8(scsi_csr_2, NeXTSCSI), 878 VMSTATE_END_OF_LIST() 879 }, 880 }; 881 882 static void next_scsi_class_init(ObjectClass *klass, void *data) 883 { 884 DeviceClass *dc = DEVICE_CLASS(klass); 885 886 dc->desc = "NeXT SCSI Controller"; 887 dc->realize = next_scsi_realize; 888 dc->vmsd = &next_scsi_vmstate; 889 } 890 891 static const TypeInfo next_scsi_info = { 892 .name = TYPE_NEXT_SCSI, 893 .parent = TYPE_SYS_BUS_DEVICE, 894 .instance_init = next_scsi_init, 895 .instance_size = sizeof(NeXTSCSI), 896 .class_init = next_scsi_class_init, 897 }; 898 899 static void next_floppy_write(void *opaque, hwaddr addr, uint64_t val, 900 unsigned size) 901 { 902 switch (addr) { 903 case 0: 904 DPRINTF("FDCSR Write: %"PRIx64 "\n", val); 905 if (val == 0x0) { 906 /* qemu_irq_raise(s->fd_irq[0]); */ 907 } 908 break; 909 910 default: 911 g_assert_not_reached(); 912 } 913 } 914 915 static uint64_t next_floppy_read(void *opaque, hwaddr addr, unsigned size) 916 { 917 uint64_t val; 918 919 switch (addr) { 920 case 0: 921 DPRINTF("FD read @ %x\n", (unsigned int)addr); 922 val = 0x40 | 0x04 | 0x2 | 0x1; 923 break; 924 925 default: 926 g_assert_not_reached(); 927 } 928 929 return val; 930 } 931 932 static const MemoryRegionOps next_floppy_ops = { 933 .read = next_floppy_read, 934 .write = next_floppy_write, 935 .valid.min_access_size = 1, 936 .valid.max_access_size = 4, 937 .endianness = DEVICE_BIG_ENDIAN, 938 }; 939 940 static void next_timer_write(void *opaque, hwaddr addr, uint64_t val, 941 unsigned size) 942 { 943 switch (addr) { 944 case 0 ... 3: 945 /* Hardware timer latch - not implemented yet */ 946 break; 947 948 default: 949 g_assert_not_reached(); 950 } 951 } 952 953 static uint64_t next_timer_read(void *opaque, hwaddr addr, unsigned size) 954 { 955 uint64_t val; 956 957 switch (addr) { 958 case 0 ... 3: 959 /* 960 * These 4 registers are the hardware timer, not sure which register 961 * is the latch instead of data, but no problems so far. 962 * 963 * Hack: We need to have the LSB change consistently to make it work 964 */ 965 val = extract32(clock(), (4 - addr - size) << 3, 966 size << 3); 967 break; 968 969 default: 970 g_assert_not_reached(); 971 } 972 973 return val; 974 } 975 976 static const MemoryRegionOps next_timer_ops = { 977 .read = next_timer_read, 978 .write = next_timer_write, 979 .valid.min_access_size = 1, 980 .valid.max_access_size = 4, 981 .endianness = DEVICE_BIG_ENDIAN, 982 }; 983 984 static void next_dummy_en_write(void *opaque, hwaddr addr, uint64_t val, 985 unsigned size) 986 { 987 /* Do nothing */ 988 return; 989 } 990 991 static uint64_t next_dummy_en_read(void *opaque, hwaddr addr, unsigned size) 992 { 993 uint64_t val; 994 995 switch (addr) { 996 case 0: 997 /* For now return dummy byte to allow the Ethernet test to timeout */ 998 val = 0xff; 999 break; 1000 1001 default: 1002 val = 0; 1003 } 1004 1005 return val; 1006 } 1007 1008 static const MemoryRegionOps next_dummy_en_ops = { 1009 .read = next_dummy_en_read, 1010 .write = next_dummy_en_write, 1011 .valid.min_access_size = 1, 1012 .valid.max_access_size = 4, 1013 .endianness = DEVICE_BIG_ENDIAN, 1014 }; 1015 1016 static void next_rtc_cmd_reset_irq(void *opaque, int n, int level) 1017 { 1018 NeXTRTC *rtc = NEXT_RTC(opaque); 1019 1020 if (level) { 1021 rtc->phase = 0; 1022 rtc->command = 0; 1023 rtc->value = 0; 1024 } 1025 } 1026 1027 static void next_rtc_reset_hold(Object *obj, ResetType type) 1028 { 1029 NeXTRTC *rtc = NEXT_RTC(obj); 1030 1031 rtc->status = 0x90; 1032 1033 /* Load RTC RAM - TODO: provide possibility to load contents from file */ 1034 memcpy(rtc->ram, rtc_ram2, 32); 1035 } 1036 1037 static void next_rtc_init(Object *obj) 1038 { 1039 NeXTRTC *rtc = NEXT_RTC(obj); 1040 1041 qdev_init_gpio_in_named(DEVICE(obj), next_rtc_data_in_irq, 1042 "rtc-data-in", 1); 1043 qdev_init_gpio_out_named(DEVICE(obj), &rtc->data_out_irq, 1044 "rtc-data-out", 1); 1045 qdev_init_gpio_in_named(DEVICE(obj), next_rtc_cmd_reset_irq, 1046 "rtc-cmd-reset", 1); 1047 } 1048 1049 static const VMStateDescription next_rtc_vmstate = { 1050 .name = "next-rtc", 1051 .version_id = 3, 1052 .minimum_version_id = 3, 1053 .fields = (const VMStateField[]) { 1054 VMSTATE_INT8(phase, NeXTRTC), 1055 VMSTATE_UINT8_ARRAY(ram, NeXTRTC, 32), 1056 VMSTATE_UINT8(command, NeXTRTC), 1057 VMSTATE_UINT8(value, NeXTRTC), 1058 VMSTATE_UINT8(status, NeXTRTC), 1059 VMSTATE_UINT8(control, NeXTRTC), 1060 VMSTATE_UINT8(retval, NeXTRTC), 1061 VMSTATE_END_OF_LIST() 1062 }, 1063 }; 1064 1065 static void next_rtc_class_init(ObjectClass *klass, void *data) 1066 { 1067 DeviceClass *dc = DEVICE_CLASS(klass); 1068 ResettableClass *rc = RESETTABLE_CLASS(klass); 1069 1070 dc->desc = "NeXT RTC"; 1071 dc->vmsd = &next_rtc_vmstate; 1072 rc->phases.hold = next_rtc_reset_hold; 1073 } 1074 1075 static const TypeInfo next_rtc_info = { 1076 .name = TYPE_NEXT_RTC, 1077 .parent = TYPE_SYS_BUS_DEVICE, 1078 .instance_init = next_rtc_init, 1079 .instance_size = sizeof(NeXTRTC), 1080 .class_init = next_rtc_class_init, 1081 }; 1082 1083 static void next_pc_rtc_data_in_irq(void *opaque, int n, int level) 1084 { 1085 NeXTPC *s = NEXT_PC(opaque); 1086 uint8_t scr2_2 = extract32(s->scr2, 8, 8); 1087 1088 if (level) { 1089 scr2_2 |= SCR2_RTDATA; 1090 } else { 1091 scr2_2 &= ~SCR2_RTDATA; 1092 } 1093 1094 s->scr2 = deposit32(s->scr2, 8, 8, scr2_2); 1095 } 1096 1097 static void next_pc_reset_hold(Object *obj, ResetType type) 1098 { 1099 NeXTPC *s = NEXT_PC(obj); 1100 1101 /* Set internal registers to initial values */ 1102 /* 0x0000XX00 << vital bits */ 1103 s->scr1 = 0x00011102; 1104 s->scr2 = 0x00ff0c80; 1105 s->old_scr2 = s->scr2; 1106 } 1107 1108 static void next_pc_realize(DeviceState *dev, Error **errp) 1109 { 1110 NeXTPC *s = NEXT_PC(dev); 1111 SysBusDevice *sbd; 1112 DeviceState *d; 1113 1114 /* SCSI */ 1115 sbd = SYS_BUS_DEVICE(&s->next_scsi); 1116 if (!sysbus_realize(sbd, errp)) { 1117 return; 1118 } 1119 1120 d = DEVICE(object_resolve_path_component(OBJECT(&s->next_scsi), "esp")); 1121 sysbus_connect_irq(SYS_BUS_DEVICE(d), 0, 1122 qdev_get_gpio_in(DEVICE(s), NEXT_SCSI_I)); 1123 1124 s->scsi_reset = qdev_get_gpio_in(d, 0); 1125 s->scsi_dma = qdev_get_gpio_in(d, 1); 1126 1127 /* ESCC */ 1128 d = DEVICE(&s->escc); 1129 qdev_prop_set_uint32(d, "disabled", 0); 1130 qdev_prop_set_uint32(d, "frequency", 9600 * 384); 1131 qdev_prop_set_uint32(d, "it_shift", 0); 1132 qdev_prop_set_bit(d, "bit_swap", true); 1133 qdev_prop_set_chr(d, "chrB", serial_hd(1)); 1134 qdev_prop_set_chr(d, "chrA", serial_hd(0)); 1135 qdev_prop_set_uint32(d, "chnBtype", escc_serial); 1136 qdev_prop_set_uint32(d, "chnAtype", escc_serial); 1137 1138 sbd = SYS_BUS_DEVICE(d); 1139 if (!sysbus_realize(sbd, errp)) { 1140 return; 1141 } 1142 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(dev, NEXT_SCC_I)); 1143 sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(dev, NEXT_SCC_DMA_I)); 1144 1145 /* RTC */ 1146 d = DEVICE(&s->rtc); 1147 if (!sysbus_realize(SYS_BUS_DEVICE(d), errp)) { 1148 return; 1149 } 1150 /* Data from NeXTPC to RTC */ 1151 qdev_connect_gpio_out_named(dev, "rtc-data-out", 0, 1152 qdev_get_gpio_in_named(d, "rtc-data-in", 0)); 1153 /* Data from RTC to NeXTPC */ 1154 qdev_connect_gpio_out_named(d, "rtc-data-out", 0, 1155 qdev_get_gpio_in_named(dev, 1156 "rtc-data-in", 0)); 1157 qdev_connect_gpio_out_named(dev, "rtc-cmd-reset", 0, 1158 qdev_get_gpio_in_named(d, "rtc-cmd-reset", 0)); 1159 } 1160 1161 static void next_pc_init(Object *obj) 1162 { 1163 NeXTPC *s = NEXT_PC(obj); 1164 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1165 1166 qdev_init_gpio_in(DEVICE(obj), next_irq, NEXT_NUM_IRQS); 1167 1168 memory_region_init_io(&s->mmiomem, OBJECT(s), &next_mmio_ops, s, 1169 "next.mmio", 0x9000); 1170 sysbus_init_mmio(sbd, &s->mmiomem); 1171 1172 memory_region_init_io(&s->dummyen_mem, OBJECT(s), &next_dummy_en_ops, s, 1173 "next.en", 0x20); 1174 sysbus_init_mmio(sbd, &s->dummyen_mem); 1175 1176 object_initialize_child(obj, "next-scsi", &s->next_scsi, TYPE_NEXT_SCSI); 1177 sysbus_init_mmio(sbd, 1178 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->next_scsi), 0)); 1179 1180 memory_region_init_io(&s->floppy_mem, OBJECT(s), &next_floppy_ops, s, 1181 "next.floppy", 4); 1182 sysbus_init_mmio(sbd, &s->floppy_mem); 1183 1184 object_initialize_child(obj, "escc", &s->escc, TYPE_ESCC); 1185 sysbus_init_mmio(sbd, 1186 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->escc), 0)); 1187 1188 memory_region_init_io(&s->timer_mem, OBJECT(s), &next_timer_ops, s, 1189 "next.timer", 4); 1190 sysbus_init_mmio(sbd, &s->timer_mem); 1191 1192 object_initialize_child(obj, "rtc", &s->rtc, TYPE_NEXT_RTC); 1193 1194 s->rtc_power_irq = qdev_get_gpio_in(DEVICE(obj), NEXT_PWR_I); 1195 qdev_init_gpio_in_named(DEVICE(obj), next_pc_rtc_data_in_irq, 1196 "rtc-data-in", 1); 1197 qdev_init_gpio_out_named(DEVICE(obj), &s->rtc_data_irq, 1198 "rtc-data-out", 1); 1199 qdev_init_gpio_out_named(DEVICE(obj), &s->rtc_cmd_reset_irq, 1200 "rtc-cmd-reset", 1); 1201 } 1202 1203 /* 1204 * If the m68k CPU implemented its inbound irq lines as GPIO lines 1205 * rather than via the m68k_set_irq_level() function we would not need 1206 * this cpu link property and could instead provide outbound IRQ lines 1207 * that the board could wire up to the CPU. 1208 */ 1209 static const Property next_pc_properties[] = { 1210 DEFINE_PROP_LINK("cpu", NeXTPC, cpu, TYPE_M68K_CPU, M68kCPU *), 1211 }; 1212 1213 static const VMStateDescription next_pc_vmstate = { 1214 .name = "next-pc", 1215 .version_id = 4, 1216 .minimum_version_id = 4, 1217 .fields = (const VMStateField[]) { 1218 VMSTATE_UINT32(scr1, NeXTPC), 1219 VMSTATE_UINT32(scr2, NeXTPC), 1220 VMSTATE_UINT32(old_scr2, NeXTPC), 1221 VMSTATE_UINT32(int_mask, NeXTPC), 1222 VMSTATE_UINT32(int_status, NeXTPC), 1223 VMSTATE_UINT32(led, NeXTPC), 1224 VMSTATE_END_OF_LIST() 1225 }, 1226 }; 1227 1228 static void next_pc_class_init(ObjectClass *klass, void *data) 1229 { 1230 DeviceClass *dc = DEVICE_CLASS(klass); 1231 ResettableClass *rc = RESETTABLE_CLASS(klass); 1232 1233 dc->desc = "NeXT Peripheral Controller"; 1234 dc->realize = next_pc_realize; 1235 device_class_set_props(dc, next_pc_properties); 1236 dc->vmsd = &next_pc_vmstate; 1237 rc->phases.hold = next_pc_reset_hold; 1238 } 1239 1240 static const TypeInfo next_pc_info = { 1241 .name = TYPE_NEXT_PC, 1242 .parent = TYPE_SYS_BUS_DEVICE, 1243 .instance_init = next_pc_init, 1244 .instance_size = sizeof(NeXTPC), 1245 .class_init = next_pc_class_init, 1246 }; 1247 1248 static void next_cube_init(MachineState *machine) 1249 { 1250 NeXTState *m = NEXT_MACHINE(machine); 1251 M68kCPU *cpu; 1252 CPUM68KState *env; 1253 MemoryRegion *sysmem = get_system_memory(); 1254 const char *bios_name = machine->firmware ?: ROM_FILE; 1255 DeviceState *pcdev; 1256 1257 /* Initialize the cpu core */ 1258 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 1259 if (!cpu) { 1260 error_report("Unable to find m68k CPU definition"); 1261 exit(1); 1262 } 1263 env = &cpu->env; 1264 1265 /* Initialize CPU registers. */ 1266 env->vbr = 0; 1267 env->sr = 0x2700; 1268 1269 /* Peripheral Controller */ 1270 pcdev = qdev_new(TYPE_NEXT_PC); 1271 object_property_set_link(OBJECT(pcdev), "cpu", OBJECT(cpu), &error_abort); 1272 sysbus_realize_and_unref(SYS_BUS_DEVICE(pcdev), &error_fatal); 1273 1274 /* 64MB RAM starting at 0x04000000 */ 1275 memory_region_add_subregion(sysmem, 0x04000000, machine->ram); 1276 1277 /* Framebuffer */ 1278 sysbus_create_simple(TYPE_NEXTFB, 0x0B000000, NULL); 1279 1280 /* MMIO */ 1281 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02005000); 1282 1283 /* BMAP IO - acts as a catch-all for now */ 1284 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02100000); 1285 1286 /* en network (dummy) */ 1287 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02106000); 1288 1289 /* unknown: Brightness control register? */ 1290 empty_slot_init("next.unknown.0", 0x02110000, 0x10); 1291 /* unknown: Magneto-Optical drive controller? */ 1292 empty_slot_init("next.unknown.1", 0x02112000, 0x10); 1293 1294 /* SCSI */ 1295 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 2, 0x02114000); 1296 /* Floppy */ 1297 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 3, 0x02114108); 1298 /* ESCC */ 1299 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 4, 0x02118000); 1300 1301 /* unknown: Serial clock configuration register? */ 1302 empty_slot_init("next.unknown.2", 0x02118004, 0x10); 1303 1304 /* Timer */ 1305 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 5, 0x0211a000); 1306 1307 /* BMAP memory */ 1308 memory_region_init_ram_flags_nomigrate(&m->bmapm1, NULL, "next.bmapmem", 1309 64, RAM_SHARED, &error_fatal); 1310 memory_region_add_subregion(sysmem, 0x020c0000, &m->bmapm1); 1311 /* The Rev_2.5_v66.bin firmware accesses it at 0x820c0020, too */ 1312 memory_region_init_alias(&m->bmapm2, NULL, "next.bmapmem2", &m->bmapm1, 1313 0x0, 64); 1314 memory_region_add_subregion(sysmem, 0x820c0000, &m->bmapm2); 1315 1316 /* KBD */ 1317 sysbus_create_simple(TYPE_NEXTKBD, 0x0200e000, NULL); 1318 1319 /* Load ROM here */ 1320 memory_region_init_rom(&m->rom, NULL, "next.rom", 0x20000, &error_fatal); 1321 memory_region_add_subregion(sysmem, 0x01000000, &m->rom); 1322 memory_region_init_alias(&m->rom2, NULL, "next.rom2", &m->rom, 0x0, 1323 0x20000); 1324 memory_region_add_subregion(sysmem, 0x0, &m->rom2); 1325 if (load_image_targphys(bios_name, 0x01000000, 0x20000) < 8) { 1326 if (!qtest_enabled()) { 1327 error_report("Failed to load firmware '%s'.", bios_name); 1328 } 1329 } else { 1330 uint8_t *ptr; 1331 /* Initial PC is always at offset 4 in firmware binaries */ 1332 ptr = rom_ptr(0x01000004, 4); 1333 g_assert(ptr != NULL); 1334 env->pc = ldl_be_p(ptr); 1335 if (env->pc >= 0x01020000) { 1336 error_report("'%s' does not seem to be a valid firmware image.", 1337 bios_name); 1338 exit(1); 1339 } 1340 } 1341 1342 /* DMA */ 1343 memory_region_init_io(&m->dmamem, NULL, &next_dma_ops, machine, 1344 "next.dma", 0x5000); 1345 memory_region_add_subregion(sysmem, 0x02000000, &m->dmamem); 1346 } 1347 1348 static void next_machine_class_init(ObjectClass *oc, void *data) 1349 { 1350 MachineClass *mc = MACHINE_CLASS(oc); 1351 1352 mc->desc = "NeXT Cube"; 1353 mc->init = next_cube_init; 1354 mc->block_default_type = IF_SCSI; 1355 mc->default_ram_size = RAM_SIZE; 1356 mc->default_ram_id = "next.ram"; 1357 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); 1358 mc->no_cdrom = true; 1359 } 1360 1361 static const TypeInfo next_typeinfo = { 1362 .name = TYPE_NEXT_MACHINE, 1363 .parent = TYPE_MACHINE, 1364 .class_init = next_machine_class_init, 1365 .instance_size = sizeof(NeXTState), 1366 }; 1367 1368 static void next_register_type(void) 1369 { 1370 type_register_static(&next_typeinfo); 1371 type_register_static(&next_pc_info); 1372 type_register_static(&next_scsi_info); 1373 type_register_static(&next_rtc_info); 1374 } 1375 1376 type_init(next_register_type) 1377