1 /* 2 * NeXT Cube System Driver 3 * 4 * Copyright (c) 2011 Bryce Lanham 5 * 6 * This code is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published 8 * by the Free Software Foundation; either version 2 of the License, 9 * or (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "exec/hwaddr.h" 14 #include "system/system.h" 15 #include "system/qtest.h" 16 #include "hw/irq.h" 17 #include "hw/m68k/next-cube.h" 18 #include "hw/boards.h" 19 #include "hw/loader.h" 20 #include "hw/scsi/esp.h" 21 #include "hw/sysbus.h" 22 #include "qom/object.h" 23 #include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */ 24 #include "hw/block/fdc.h" 25 #include "hw/misc/empty_slot.h" 26 #include "hw/qdev-properties.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "ui/console.h" 30 #include "target/m68k/cpu.h" 31 #include "migration/vmstate.h" 32 33 /* #define DEBUG_NEXT */ 34 #ifdef DEBUG_NEXT 35 #define DPRINTF(fmt, ...) \ 36 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0) 37 #else 38 #define DPRINTF(fmt, ...) do { } while (0) 39 #endif 40 41 #define ENTRY 0x0100001e 42 #define RAM_SIZE 0x4000000 43 #define ROM_FILE "Rev_2.5_v66.bin" 44 45 typedef struct NeXTRTC { 46 int8_t phase; 47 uint8_t ram[32]; 48 uint8_t command; 49 uint8_t value; 50 uint8_t status; 51 uint8_t control; 52 uint8_t retval; 53 } NeXTRTC; 54 55 #define TYPE_NEXT_SCSI "next-scsi" 56 OBJECT_DECLARE_SIMPLE_TYPE(NeXTSCSI, NEXT_SCSI) 57 58 /* NeXT SCSI Controller */ 59 struct NeXTSCSI { 60 SysBusDevice parent_obj; 61 62 MemoryRegion scsi_mem; 63 64 SysBusESPState sysbus_esp; 65 66 MemoryRegion scsi_csr_mem; 67 uint8_t scsi_csr_1; 68 uint8_t scsi_csr_2; 69 }; 70 71 #define TYPE_NEXT_PC "next-pc" 72 OBJECT_DECLARE_SIMPLE_TYPE(NeXTPC, NEXT_PC) 73 74 /* NeXT Peripheral Controller */ 75 struct NeXTPC { 76 SysBusDevice parent_obj; 77 78 M68kCPU *cpu; 79 80 MemoryRegion floppy_mem; 81 MemoryRegion timer_mem; 82 MemoryRegion dummyen_mem; 83 MemoryRegion mmiomem; 84 MemoryRegion scrmem; 85 86 uint32_t scr1; 87 uint32_t scr2; 88 uint32_t old_scr2; 89 uint32_t int_mask; 90 uint32_t int_status; 91 uint32_t led; 92 93 NeXTSCSI next_scsi; 94 95 qemu_irq scsi_reset; 96 qemu_irq scsi_dma; 97 98 ESCCState escc; 99 100 NeXTRTC rtc; 101 qemu_irq rtc_power_irq; 102 }; 103 104 typedef struct next_dma { 105 uint32_t csr; 106 107 uint32_t saved_next; 108 uint32_t saved_limit; 109 uint32_t saved_start; 110 uint32_t saved_stop; 111 112 uint32_t next; 113 uint32_t limit; 114 uint32_t start; 115 uint32_t stop; 116 117 uint32_t next_initbuf; 118 uint32_t size; 119 } next_dma; 120 121 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube") 122 OBJECT_DECLARE_SIMPLE_TYPE(NeXTState, NEXT_MACHINE) 123 124 struct NeXTState { 125 MachineState parent; 126 127 MemoryRegion rom; 128 MemoryRegion rom2; 129 MemoryRegion dmamem; 130 MemoryRegion bmapm1; 131 MemoryRegion bmapm2; 132 133 next_dma dma[10]; 134 }; 135 136 /* Thanks to NeXT forums for this */ 137 /* 138 static const uint8_t rtc_ram3[32] = { 139 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 140 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00, 141 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00, 142 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13 143 }; 144 */ 145 static const uint8_t rtc_ram2[32] = { 146 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00, 147 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00, 148 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 149 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e, 150 }; 151 152 #define SCR2_RTCLK 0x2 153 #define SCR2_RTDATA 0x4 154 #define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10)) 155 156 static void next_scr2_led_update(NeXTPC *s) 157 { 158 if (s->scr2 & 0x1) { 159 DPRINTF("fault!\n"); 160 s->led++; 161 if (s->led == 10) { 162 DPRINTF("LED flashing, possible fault!\n"); 163 s->led = 0; 164 } 165 } 166 } 167 168 static bool next_rtc_cmd_is_write(uint8_t cmd) 169 { 170 return (cmd >= 0x80 && cmd <= 0x9f) || 171 (cmd == 0xb1); 172 } 173 174 static void next_scr2_rtc_update(NeXTPC *s) 175 { 176 uint8_t old_scr2, scr2_2; 177 NeXTRTC *rtc = &s->rtc; 178 179 old_scr2 = extract32(s->old_scr2, 8, 8); 180 scr2_2 = extract32(s->scr2, 8, 8); 181 182 if (scr2_2 & 0x1) { 183 /* DPRINTF("RTC %x phase %i\n", scr2_2, rtc->phase); */ 184 if (rtc->phase == -1) { 185 rtc->phase = 0; 186 } 187 /* If we are in going down clock... do something */ 188 if (((old_scr2 & SCR2_RTCLK) != (scr2_2 & SCR2_RTCLK)) && 189 ((scr2_2 & SCR2_RTCLK) == 0)) { 190 if (rtc->phase < 8) { 191 rtc->command = (rtc->command << 1) | 192 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 193 } 194 if (rtc->phase >= 8 && rtc->phase < 16) { 195 if (next_rtc_cmd_is_write(rtc->command)) { 196 /* Shift in value to write */ 197 rtc->value = (rtc->value << 1) | 198 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 199 } else { 200 /* Shift out value to read */ 201 202 /* if we read RAM register, output RT_DATA bit */ 203 if (rtc->command <= 0x1F) { 204 scr2_2 = scr2_2 & (~SCR2_RTDATA); 205 if (rtc->ram[rtc->command] & 206 (0x80 >> (rtc->phase - 8))) { 207 scr2_2 |= SCR2_RTDATA; 208 } 209 210 rtc->retval = (rtc->retval << 1) | 211 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 212 } 213 /* read the status 0x30 */ 214 if (rtc->command == 0x30) { 215 scr2_2 = scr2_2 & (~SCR2_RTDATA); 216 /* for now status = 0x98 (new rtc + FTU) */ 217 if (rtc->status & (0x80 >> (rtc->phase - 8))) { 218 scr2_2 |= SCR2_RTDATA; 219 } 220 221 rtc->retval = (rtc->retval << 1) | 222 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 223 } 224 /* read the status 0x31 */ 225 if (rtc->command == 0x31) { 226 scr2_2 = scr2_2 & (~SCR2_RTDATA); 227 if (rtc->control & (0x80 >> (rtc->phase - 8))) { 228 scr2_2 |= SCR2_RTDATA; 229 } 230 rtc->retval = (rtc->retval << 1) | 231 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 232 } 233 234 if ((rtc->command >= 0x20) && (rtc->command <= 0x2F)) { 235 scr2_2 = scr2_2 & (~SCR2_RTDATA); 236 /* for now 0x00 */ 237 time_t time_h = time(NULL); 238 struct tm *info = localtime(&time_h); 239 int ret = 0; 240 241 switch (rtc->command) { 242 case 0x20: 243 ret = SCR2_TOBCD(info->tm_sec); 244 break; 245 case 0x21: 246 ret = SCR2_TOBCD(info->tm_min); 247 break; 248 case 0x22: 249 ret = SCR2_TOBCD(info->tm_hour); 250 break; 251 case 0x24: 252 ret = SCR2_TOBCD(info->tm_mday); 253 break; 254 case 0x25: 255 ret = SCR2_TOBCD((info->tm_mon + 1)); 256 break; 257 case 0x26: 258 ret = SCR2_TOBCD((info->tm_year - 100)); 259 break; 260 } 261 262 if (ret & (0x80 >> (rtc->phase - 8))) { 263 scr2_2 |= SCR2_RTDATA; 264 } 265 rtc->retval = (rtc->retval << 1) | 266 ((scr2_2 & SCR2_RTDATA) ? 1 : 0); 267 } 268 } 269 } 270 271 rtc->phase++; 272 if (rtc->phase == 16) { 273 if (rtc->command >= 0x80 && rtc->command <= 0x9F) { 274 rtc->ram[rtc->command - 0x80] = rtc->value; 275 } 276 /* write to x30 register */ 277 if (rtc->command == 0xB1) { 278 /* clear FTU */ 279 if (rtc->value & 0x04) { 280 rtc->status = rtc->status & (~0x18); 281 qemu_irq_lower(s->rtc_power_irq); 282 } 283 } 284 } 285 } 286 } else { 287 /* else end or abort */ 288 rtc->phase = -1; 289 rtc->command = 0; 290 rtc->value = 0; 291 } 292 293 s->scr2 = deposit32(s->scr2, 8, 8, scr2_2); 294 } 295 296 static uint64_t next_mmio_read(void *opaque, hwaddr addr, unsigned size) 297 { 298 NeXTPC *s = NEXT_PC(opaque); 299 uint64_t val; 300 301 switch (addr) { 302 case 0x2000: /* 0x2007000 */ 303 /* DPRINTF("Read INT status: %x\n", s->int_status); */ 304 val = s->int_status; 305 break; 306 307 case 0x2800: /* 0x2007800 */ 308 DPRINTF("MMIO Read INT mask: %x\n", s->int_mask); 309 val = s->int_mask; 310 break; 311 312 case 0x7000 ... 0x7003: /* 0x200c000 */ 313 val = extract32(s->scr1, (4 - (addr - 0x7000) - size) << 3, 314 size << 3); 315 break; 316 317 case 0x8000 ... 0x8003: /* 0x200d000 */ 318 val = extract32(s->scr2, (4 - (addr - 0x8000) - size) << 3, 319 size << 3); 320 break; 321 322 default: 323 val = 0; 324 DPRINTF("MMIO Read @ 0x%"HWADDR_PRIx" size %d\n", addr, size); 325 break; 326 } 327 328 return val; 329 } 330 331 static void next_mmio_write(void *opaque, hwaddr addr, uint64_t val, 332 unsigned size) 333 { 334 NeXTPC *s = NEXT_PC(opaque); 335 336 switch (addr) { 337 case 0x2000: /* 0x2007000 */ 338 DPRINTF("INT Status old: %x new: %x\n", s->int_status, 339 (unsigned int)val); 340 s->int_status = val; 341 break; 342 343 case 0x2800: /* 0x2007800 */ 344 DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, (unsigned int)val); 345 s->int_mask = val; 346 break; 347 348 case 0x7000 ... 0x7003: /* 0x200c000 */ 349 DPRINTF("SCR1 Write: %x\n", (unsigned int)val); 350 s->scr1 = deposit32(s->scr1, (4 - (addr - 0x7000) - size) << 3, 351 size << 3, val); 352 break; 353 354 case 0x8000 ... 0x8003: /* 0x200d000 */ 355 s->scr2 = deposit32(s->scr2, (4 - (addr - 0x8000) - size) << 3, 356 size << 3, val); 357 next_scr2_led_update(s); 358 next_scr2_rtc_update(s); 359 s->old_scr2 = s->scr2; 360 break; 361 362 default: 363 DPRINTF("MMIO Write @ 0x%"HWADDR_PRIx " with 0x%x size %u\n", addr, 364 (unsigned int)val, size); 365 } 366 } 367 368 static const MemoryRegionOps next_mmio_ops = { 369 .read = next_mmio_read, 370 .write = next_mmio_write, 371 .valid.min_access_size = 1, 372 .valid.max_access_size = 4, 373 .endianness = DEVICE_BIG_ENDIAN, 374 }; 375 376 #define SCSICSR_ENABLE 0x01 377 #define SCSICSR_RESET 0x02 /* reset scsi dma */ 378 #define SCSICSR_FIFOFL 0x04 379 #define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */ 380 #define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */ 381 #define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */ 382 383 #define NEXTDMA_SCSI(x) (0x10 + x) 384 #define NEXTDMA_FD(x) (0x10 + x) 385 #define NEXTDMA_ENTX(x) (0x110 + x) 386 #define NEXTDMA_ENRX(x) (0x150 + x) 387 #define NEXTDMA_CSR 0x0 388 #define NEXTDMA_NEXT 0x4000 389 #define NEXTDMA_LIMIT 0x4004 390 #define NEXTDMA_START 0x4008 391 #define NEXTDMA_STOP 0x400c 392 #define NEXTDMA_NEXT_INIT 0x4200 393 #define NEXTDMA_SIZE 0x4204 394 395 static void next_dma_write(void *opaque, hwaddr addr, uint64_t val, 396 unsigned int size) 397 { 398 NeXTState *next_state = NEXT_MACHINE(opaque); 399 400 switch (addr) { 401 case NEXTDMA_ENRX(NEXTDMA_CSR): 402 if (val & DMA_DEV2M) { 403 next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M; 404 } 405 406 if (val & DMA_SETENABLE) { 407 /* DPRINTF("SCSI DMA ENABLE\n"); */ 408 next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE; 409 } 410 if (val & DMA_SETSUPDATE) { 411 next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE; 412 } 413 if (val & DMA_CLRCOMPLETE) { 414 next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE; 415 } 416 417 if (val & DMA_RESET) { 418 next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 419 DMA_ENABLE | DMA_DEV2M); 420 } 421 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 422 break; 423 424 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 425 next_state->dma[NEXTDMA_ENRX].next_initbuf = val; 426 break; 427 428 case NEXTDMA_ENRX(NEXTDMA_NEXT): 429 next_state->dma[NEXTDMA_ENRX].next = val; 430 break; 431 432 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 433 next_state->dma[NEXTDMA_ENRX].limit = val; 434 break; 435 436 case NEXTDMA_SCSI(NEXTDMA_CSR): 437 if (val & DMA_DEV2M) { 438 next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M; 439 } 440 if (val & DMA_SETENABLE) { 441 /* DPRINTF("SCSI DMA ENABLE\n"); */ 442 next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE; 443 } 444 if (val & DMA_SETSUPDATE) { 445 next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE; 446 } 447 if (val & DMA_CLRCOMPLETE) { 448 next_state->dma[NEXTDMA_SCSI].csr &= ~DMA_COMPLETE; 449 } 450 451 if (val & DMA_RESET) { 452 next_state->dma[NEXTDMA_SCSI].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 453 DMA_ENABLE | DMA_DEV2M); 454 /* DPRINTF("SCSI DMA RESET\n"); */ 455 } 456 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 457 break; 458 459 case NEXTDMA_SCSI(NEXTDMA_NEXT): 460 next_state->dma[NEXTDMA_SCSI].next = val; 461 break; 462 463 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 464 next_state->dma[NEXTDMA_SCSI].limit = val; 465 break; 466 467 case NEXTDMA_SCSI(NEXTDMA_START): 468 next_state->dma[NEXTDMA_SCSI].start = val; 469 break; 470 471 case NEXTDMA_SCSI(NEXTDMA_STOP): 472 next_state->dma[NEXTDMA_SCSI].stop = val; 473 break; 474 475 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 476 next_state->dma[NEXTDMA_SCSI].next_initbuf = val; 477 break; 478 479 default: 480 DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)val); 481 } 482 } 483 484 static uint64_t next_dma_read(void *opaque, hwaddr addr, unsigned int size) 485 { 486 NeXTState *next_state = NEXT_MACHINE(opaque); 487 uint64_t val; 488 489 switch (addr) { 490 case NEXTDMA_SCSI(NEXTDMA_CSR): 491 DPRINTF("SCSI DMA CSR READ\n"); 492 val = next_state->dma[NEXTDMA_SCSI].csr; 493 break; 494 495 case NEXTDMA_ENRX(NEXTDMA_CSR): 496 val = next_state->dma[NEXTDMA_ENRX].csr; 497 break; 498 499 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 500 val = next_state->dma[NEXTDMA_ENRX].next_initbuf; 501 break; 502 503 case NEXTDMA_ENRX(NEXTDMA_NEXT): 504 val = next_state->dma[NEXTDMA_ENRX].next; 505 break; 506 507 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 508 val = next_state->dma[NEXTDMA_ENRX].limit; 509 break; 510 511 case NEXTDMA_SCSI(NEXTDMA_NEXT): 512 val = next_state->dma[NEXTDMA_SCSI].next; 513 break; 514 515 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 516 val = next_state->dma[NEXTDMA_SCSI].next_initbuf; 517 break; 518 519 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 520 val = next_state->dma[NEXTDMA_SCSI].limit; 521 break; 522 523 case NEXTDMA_SCSI(NEXTDMA_START): 524 val = next_state->dma[NEXTDMA_SCSI].start; 525 break; 526 527 case NEXTDMA_SCSI(NEXTDMA_STOP): 528 val = next_state->dma[NEXTDMA_SCSI].stop; 529 break; 530 531 default: 532 DPRINTF("DMA read @ %x\n", (unsigned int)addr); 533 val = 0; 534 } 535 536 /* 537 * once the csr's are done, subtract 0x3FEC from the addr, and that will 538 * normalize the upper registers 539 */ 540 541 return val; 542 } 543 544 static const MemoryRegionOps next_dma_ops = { 545 .read = next_dma_read, 546 .write = next_dma_write, 547 .impl.min_access_size = 4, 548 .valid.min_access_size = 4, 549 .valid.max_access_size = 4, 550 .endianness = DEVICE_BIG_ENDIAN, 551 }; 552 553 static void next_irq(void *opaque, int number, int level) 554 { 555 NeXTPC *s = NEXT_PC(opaque); 556 M68kCPU *cpu = s->cpu; 557 int shift = 0; 558 559 /* first switch sets interrupt status */ 560 /* DPRINTF("IRQ %i\n",number); */ 561 switch (number) { 562 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 563 case NEXT_FD_I: 564 shift = 7; 565 break; 566 case NEXT_KBD_I: 567 shift = 3; 568 break; 569 case NEXT_PWR_I: 570 shift = 2; 571 break; 572 case NEXT_ENRX_I: 573 shift = 9; 574 break; 575 case NEXT_ENTX_I: 576 shift = 10; 577 break; 578 case NEXT_SCSI_I: 579 shift = 12; 580 break; 581 case NEXT_CLK_I: 582 shift = 5; 583 break; 584 585 /* level 5 - scc (serial) */ 586 case NEXT_SCC_I: 587 shift = 17; 588 break; 589 590 /* level 6 - audio etherrx/tx dma */ 591 case NEXT_ENTX_DMA_I: 592 shift = 28; 593 break; 594 case NEXT_ENRX_DMA_I: 595 shift = 27; 596 break; 597 case NEXT_SCSI_DMA_I: 598 shift = 26; 599 break; 600 case NEXT_SND_I: 601 shift = 23; 602 break; 603 case NEXT_SCC_DMA_I: 604 shift = 21; 605 break; 606 607 } 608 /* 609 * this HAS to be wrong, the interrupt handlers in mach and together 610 * int_status and int_mask and return if there is a hit 611 */ 612 if (s->int_mask & (1 << shift)) { 613 DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc); 614 /* return; */ 615 } 616 617 /* second switch triggers the correct interrupt */ 618 if (level) { 619 s->int_status |= 1 << shift; 620 621 switch (number) { 622 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 623 case NEXT_FD_I: 624 case NEXT_KBD_I: 625 case NEXT_PWR_I: 626 case NEXT_ENRX_I: 627 case NEXT_ENTX_I: 628 case NEXT_SCSI_I: 629 case NEXT_CLK_I: 630 m68k_set_irq_level(cpu, 3, 27); 631 break; 632 633 /* level 5 - scc (serial) */ 634 case NEXT_SCC_I: 635 m68k_set_irq_level(cpu, 5, 29); 636 break; 637 638 /* level 6 - audio etherrx/tx dma */ 639 case NEXT_ENTX_DMA_I: 640 case NEXT_ENRX_DMA_I: 641 case NEXT_SCSI_DMA_I: 642 case NEXT_SND_I: 643 case NEXT_SCC_DMA_I: 644 m68k_set_irq_level(cpu, 6, 30); 645 break; 646 } 647 } else { 648 s->int_status &= ~(1 << shift); 649 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); 650 } 651 } 652 653 static void nextdma_write(void *opaque, uint8_t *buf, int size, int type) 654 { 655 uint32_t base_addr; 656 int irq = 0; 657 uint8_t align = 16; 658 NeXTState *next_state = NEXT_MACHINE(qdev_get_machine()); 659 660 if (type == NEXTDMA_ENRX || type == NEXTDMA_ENTX) { 661 align = 32; 662 } 663 /* Most DMA is supposedly 16 byte aligned */ 664 if ((size % align) != 0) { 665 size -= size % align; 666 size += align; 667 } 668 669 /* 670 * prom sets the dma start using initbuf while the bootloader uses next 671 * so we check to see if initbuf is 0 672 */ 673 if (next_state->dma[type].next_initbuf == 0) { 674 base_addr = next_state->dma[type].next; 675 } else { 676 base_addr = next_state->dma[type].next_initbuf; 677 } 678 679 cpu_physical_memory_write(base_addr, buf, size); 680 681 next_state->dma[type].next_initbuf = 0; 682 683 /* saved limit is checked to calculate packet size by both, rom and netbsd */ 684 next_state->dma[type].saved_limit = (next_state->dma[type].next + size); 685 next_state->dma[type].saved_next = (next_state->dma[type].next); 686 687 /* 688 * 32 bytes under savedbase seems to be some kind of register 689 * of which the purpose is unknown as of yet 690 */ 691 /* stl_phys(s->rx_dma.base-32,0xFFFFFFFF); */ 692 693 if (!(next_state->dma[type].csr & DMA_SUPDATE)) { 694 next_state->dma[type].next = next_state->dma[type].start; 695 next_state->dma[type].limit = next_state->dma[type].stop; 696 } 697 698 /* Set dma registers and raise an irq */ 699 next_state->dma[type].csr |= DMA_COMPLETE; /* DON'T CHANGE THIS! */ 700 701 switch (type) { 702 case NEXTDMA_SCSI: 703 irq = NEXT_SCSI_DMA_I; 704 break; 705 } 706 707 next_irq(opaque, irq, 1); 708 next_irq(opaque, irq, 0); 709 } 710 711 static void nextscsi_read(void *opaque, uint8_t *buf, int len) 712 { 713 DPRINTF("SCSI READ: %x\n", len); 714 abort(); 715 } 716 717 static void nextscsi_write(void *opaque, uint8_t *buf, int size) 718 { 719 DPRINTF("SCSI WRITE: %i\n", size); 720 nextdma_write(opaque, buf, size, NEXTDMA_SCSI); 721 } 722 723 static void next_scsi_csr_write(void *opaque, hwaddr addr, uint64_t val, 724 unsigned size) 725 { 726 NeXTSCSI *s = NEXT_SCSI(opaque); 727 NeXTPC *pc = NEXT_PC(container_of(s, NeXTPC, next_scsi)); 728 729 switch (addr) { 730 case 0: 731 if (val & SCSICSR_FIFOFL) { 732 DPRINTF("SCSICSR FIFO Flush\n"); 733 /* will have to add another irq to the esp if this is needed */ 734 /* esp_puflush_fifo(esp_g); */ 735 } 736 737 if (val & SCSICSR_ENABLE) { 738 DPRINTF("SCSICSR Enable\n"); 739 /* 740 * qemu_irq_raise(s->scsi_dma); 741 * s->scsi_csr_1 = 0xc0; 742 * s->scsi_csr_1 |= 0x1; 743 * qemu_irq_pulse(s->scsi_dma); 744 */ 745 } 746 /* 747 * else 748 * s->scsi_csr_1 &= ~SCSICSR_ENABLE; 749 */ 750 751 if (val & SCSICSR_RESET) { 752 DPRINTF("SCSICSR Reset\n"); 753 /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */ 754 qemu_irq_raise(pc->scsi_reset); 755 s->scsi_csr_1 &= ~(SCSICSR_INTMASK | 0x80 | 0x1); 756 qemu_irq_lower(pc->scsi_reset); 757 } 758 if (val & SCSICSR_DMADIR) { 759 DPRINTF("SCSICSR DMAdir\n"); 760 } 761 if (val & SCSICSR_CPUDMA) { 762 DPRINTF("SCSICSR CPUDMA\n"); 763 /* qemu_irq_raise(s->scsi_dma); */ 764 pc->int_status |= 0x4000000; 765 } else { 766 /* fprintf(stderr,"SCSICSR CPUDMA disabled\n"); */ 767 pc->int_status &= ~(0x4000000); 768 /* qemu_irq_lower(s->scsi_dma); */ 769 } 770 if (val & SCSICSR_INTMASK) { 771 DPRINTF("SCSICSR INTMASK\n"); 772 /* 773 * int_mask &= ~0x1000; 774 * s->scsi_csr_1 |= val; 775 * s->scsi_csr_1 &= ~SCSICSR_INTMASK; 776 * if (s->scsi_queued) { 777 * s->scsi_queued = 0; 778 * next_irq(s, NEXT_SCSI_I, level); 779 * } 780 */ 781 } else { 782 /* int_mask |= 0x1000; */ 783 } 784 if (val & 0x80) { 785 /* int_mask |= 0x1000; */ 786 /* s->scsi_csr_1 |= 0x80; */ 787 } 788 DPRINTF("SCSICSR1 Write: %"PRIx64 "\n", val); 789 s->scsi_csr_1 = val; 790 break; 791 792 case 1: 793 DPRINTF("SCSICSR2 Write: %"PRIx64 "\n", val); 794 s->scsi_csr_2 = val; 795 break; 796 797 default: 798 g_assert_not_reached(); 799 } 800 } 801 802 static uint64_t next_scsi_csr_read(void *opaque, hwaddr addr, unsigned size) 803 { 804 NeXTSCSI *s = NEXT_SCSI(opaque); 805 uint64_t val; 806 807 switch (addr) { 808 case 0: 809 DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1); 810 val = s->scsi_csr_1; 811 break; 812 813 case 1: 814 DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2); 815 val = s->scsi_csr_2; 816 break; 817 818 default: 819 g_assert_not_reached(); 820 } 821 822 return val; 823 } 824 825 static const MemoryRegionOps next_scsi_csr_ops = { 826 .read = next_scsi_csr_read, 827 .write = next_scsi_csr_write, 828 .valid.min_access_size = 1, 829 .valid.max_access_size = 1, 830 .endianness = DEVICE_BIG_ENDIAN, 831 }; 832 833 static void next_scsi_init(Object *obj) 834 { 835 NeXTSCSI *s = NEXT_SCSI(obj); 836 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 837 838 object_initialize_child(obj, "esp", &s->sysbus_esp, TYPE_SYSBUS_ESP); 839 840 memory_region_init_io(&s->scsi_csr_mem, obj, &next_scsi_csr_ops, 841 s, "csrs", 2); 842 843 memory_region_init(&s->scsi_mem, obj, "next.scsi", 0x40); 844 sysbus_init_mmio(sbd, &s->scsi_mem); 845 } 846 847 static void next_scsi_realize(DeviceState *dev, Error **errp) 848 { 849 NeXTSCSI *s = NEXT_SCSI(dev); 850 SysBusESPState *sysbus_esp; 851 SysBusDevice *sbd; 852 ESPState *esp; 853 NeXTPC *pcdev; 854 855 pcdev = NEXT_PC(container_of(s, NeXTPC, next_scsi)); 856 857 /* ESP */ 858 sysbus_esp = SYSBUS_ESP(&s->sysbus_esp); 859 esp = &sysbus_esp->esp; 860 esp->dma_memory_read = nextscsi_read; 861 esp->dma_memory_write = nextscsi_write; 862 esp->dma_opaque = pcdev; 863 sysbus_esp->it_shift = 0; 864 esp->dma_enabled = 1; 865 sbd = SYS_BUS_DEVICE(sysbus_esp); 866 if (!sysbus_realize(sbd, errp)) { 867 return; 868 } 869 memory_region_add_subregion(&s->scsi_mem, 0x0, 870 sysbus_mmio_get_region(sbd, 0)); 871 872 /* SCSI CSRs */ 873 memory_region_add_subregion(&s->scsi_mem, 0x20, &s->scsi_csr_mem); 874 875 scsi_bus_legacy_handle_cmdline(&s->sysbus_esp.esp.bus); 876 } 877 878 static const VMStateDescription next_scsi_vmstate = { 879 .name = "next-scsi", 880 .version_id = 0, 881 .minimum_version_id = 0, 882 .fields = (const VMStateField[]) { 883 VMSTATE_UINT8(scsi_csr_1, NeXTSCSI), 884 VMSTATE_UINT8(scsi_csr_2, NeXTSCSI), 885 VMSTATE_END_OF_LIST() 886 }, 887 }; 888 889 static void next_scsi_class_init(ObjectClass *klass, void *data) 890 { 891 DeviceClass *dc = DEVICE_CLASS(klass); 892 893 dc->desc = "NeXT SCSI Controller"; 894 dc->realize = next_scsi_realize; 895 dc->vmsd = &next_scsi_vmstate; 896 } 897 898 static const TypeInfo next_scsi_info = { 899 .name = TYPE_NEXT_SCSI, 900 .parent = TYPE_SYS_BUS_DEVICE, 901 .instance_init = next_scsi_init, 902 .instance_size = sizeof(NeXTSCSI), 903 .class_init = next_scsi_class_init, 904 }; 905 906 static void next_floppy_write(void *opaque, hwaddr addr, uint64_t val, 907 unsigned size) 908 { 909 switch (addr) { 910 case 0: 911 DPRINTF("FDCSR Write: %"PRIx64 "\n", val); 912 if (val == 0x0) { 913 /* qemu_irq_raise(s->fd_irq[0]); */ 914 } 915 break; 916 917 default: 918 g_assert_not_reached(); 919 } 920 } 921 922 static uint64_t next_floppy_read(void *opaque, hwaddr addr, unsigned size) 923 { 924 uint64_t val; 925 926 switch (addr) { 927 case 0: 928 DPRINTF("FD read @ %x\n", (unsigned int)addr); 929 val = 0x40 | 0x04 | 0x2 | 0x1; 930 break; 931 932 default: 933 g_assert_not_reached(); 934 } 935 936 return val; 937 } 938 939 static const MemoryRegionOps next_floppy_ops = { 940 .read = next_floppy_read, 941 .write = next_floppy_write, 942 .valid.min_access_size = 1, 943 .valid.max_access_size = 4, 944 .endianness = DEVICE_BIG_ENDIAN, 945 }; 946 947 static void next_timer_write(void *opaque, hwaddr addr, uint64_t val, 948 unsigned size) 949 { 950 switch (addr) { 951 case 0 ... 3: 952 /* Hardware timer latch - not implemented yet */ 953 break; 954 955 default: 956 g_assert_not_reached(); 957 } 958 } 959 960 static uint64_t next_timer_read(void *opaque, hwaddr addr, unsigned size) 961 { 962 uint64_t val; 963 964 switch (addr) { 965 case 0 ... 3: 966 /* 967 * These 4 registers are the hardware timer, not sure which register 968 * is the latch instead of data, but no problems so far. 969 * 970 * Hack: We need to have the LSB change consistently to make it work 971 */ 972 val = extract32(clock(), (4 - addr - size) << 3, 973 size << 3); 974 break; 975 976 default: 977 g_assert_not_reached(); 978 } 979 980 return val; 981 } 982 983 static const MemoryRegionOps next_timer_ops = { 984 .read = next_timer_read, 985 .write = next_timer_write, 986 .valid.min_access_size = 1, 987 .valid.max_access_size = 4, 988 .endianness = DEVICE_BIG_ENDIAN, 989 }; 990 991 static void next_dummy_en_write(void *opaque, hwaddr addr, uint64_t val, 992 unsigned size) 993 { 994 /* Do nothing */ 995 return; 996 } 997 998 static uint64_t next_dummy_en_read(void *opaque, hwaddr addr, unsigned size) 999 { 1000 uint64_t val; 1001 1002 switch (addr) { 1003 case 0: 1004 /* For now return dummy byte to allow the Ethernet test to timeout */ 1005 val = 0xff; 1006 break; 1007 1008 default: 1009 val = 0; 1010 } 1011 1012 return val; 1013 } 1014 1015 static const MemoryRegionOps next_dummy_en_ops = { 1016 .read = next_dummy_en_read, 1017 .write = next_dummy_en_write, 1018 .valid.min_access_size = 1, 1019 .valid.max_access_size = 4, 1020 .endianness = DEVICE_BIG_ENDIAN, 1021 }; 1022 1023 static void next_pc_reset_hold(Object *obj, ResetType type) 1024 { 1025 NeXTPC *s = NEXT_PC(obj); 1026 1027 /* Set internal registers to initial values */ 1028 /* 0x0000XX00 << vital bits */ 1029 s->scr1 = 0x00011102; 1030 s->scr2 = 0x00ff0c80; 1031 s->old_scr2 = s->scr2; 1032 1033 s->rtc.status = 0x90; 1034 1035 /* Load RTC RAM - TODO: provide possibility to load contents from file */ 1036 memcpy(s->rtc.ram, rtc_ram2, 32); 1037 } 1038 1039 static void next_pc_realize(DeviceState *dev, Error **errp) 1040 { 1041 NeXTPC *s = NEXT_PC(dev); 1042 SysBusDevice *sbd; 1043 DeviceState *d; 1044 1045 /* SCSI */ 1046 sbd = SYS_BUS_DEVICE(&s->next_scsi); 1047 if (!sysbus_realize(sbd, errp)) { 1048 return; 1049 } 1050 1051 d = DEVICE(object_resolve_path_component(OBJECT(&s->next_scsi), "esp")); 1052 sysbus_connect_irq(SYS_BUS_DEVICE(d), 0, 1053 qdev_get_gpio_in(DEVICE(s), NEXT_SCSI_I)); 1054 1055 s->scsi_reset = qdev_get_gpio_in(d, 0); 1056 s->scsi_dma = qdev_get_gpio_in(d, 1); 1057 1058 /* ESCC */ 1059 d = DEVICE(&s->escc); 1060 qdev_prop_set_uint32(d, "disabled", 0); 1061 qdev_prop_set_uint32(d, "frequency", 9600 * 384); 1062 qdev_prop_set_uint32(d, "it_shift", 0); 1063 qdev_prop_set_bit(d, "bit_swap", true); 1064 qdev_prop_set_chr(d, "chrB", serial_hd(1)); 1065 qdev_prop_set_chr(d, "chrA", serial_hd(0)); 1066 qdev_prop_set_uint32(d, "chnBtype", escc_serial); 1067 qdev_prop_set_uint32(d, "chnAtype", escc_serial); 1068 1069 sbd = SYS_BUS_DEVICE(d); 1070 if (!sysbus_realize(sbd, errp)) { 1071 return; 1072 } 1073 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(dev, NEXT_SCC_I)); 1074 sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(dev, NEXT_SCC_DMA_I)); 1075 } 1076 1077 static void next_pc_init(Object *obj) 1078 { 1079 NeXTPC *s = NEXT_PC(obj); 1080 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1081 1082 qdev_init_gpio_in(DEVICE(obj), next_irq, NEXT_NUM_IRQS); 1083 1084 memory_region_init_io(&s->mmiomem, OBJECT(s), &next_mmio_ops, s, 1085 "next.mmio", 0x9000); 1086 sysbus_init_mmio(sbd, &s->mmiomem); 1087 1088 memory_region_init_io(&s->dummyen_mem, OBJECT(s), &next_dummy_en_ops, s, 1089 "next.en", 0x20); 1090 sysbus_init_mmio(sbd, &s->dummyen_mem); 1091 1092 object_initialize_child(obj, "next-scsi", &s->next_scsi, TYPE_NEXT_SCSI); 1093 sysbus_init_mmio(sbd, 1094 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->next_scsi), 0)); 1095 1096 memory_region_init_io(&s->floppy_mem, OBJECT(s), &next_floppy_ops, s, 1097 "next.floppy", 4); 1098 sysbus_init_mmio(sbd, &s->floppy_mem); 1099 1100 object_initialize_child(obj, "escc", &s->escc, TYPE_ESCC); 1101 sysbus_init_mmio(sbd, 1102 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->escc), 0)); 1103 1104 memory_region_init_io(&s->timer_mem, OBJECT(s), &next_timer_ops, s, 1105 "next.timer", 4); 1106 sysbus_init_mmio(sbd, &s->timer_mem); 1107 1108 s->rtc_power_irq = qdev_get_gpio_in(DEVICE(obj), NEXT_PWR_I); 1109 } 1110 1111 /* 1112 * If the m68k CPU implemented its inbound irq lines as GPIO lines 1113 * rather than via the m68k_set_irq_level() function we would not need 1114 * this cpu link property and could instead provide outbound IRQ lines 1115 * that the board could wire up to the CPU. 1116 */ 1117 static const Property next_pc_properties[] = { 1118 DEFINE_PROP_LINK("cpu", NeXTPC, cpu, TYPE_M68K_CPU, M68kCPU *), 1119 }; 1120 1121 static const VMStateDescription next_rtc_vmstate = { 1122 .name = "next-rtc", 1123 .version_id = 2, 1124 .minimum_version_id = 2, 1125 .fields = (const VMStateField[]) { 1126 VMSTATE_INT8(phase, NeXTRTC), 1127 VMSTATE_UINT8_ARRAY(ram, NeXTRTC, 32), 1128 VMSTATE_UINT8(command, NeXTRTC), 1129 VMSTATE_UINT8(value, NeXTRTC), 1130 VMSTATE_UINT8(status, NeXTRTC), 1131 VMSTATE_UINT8(control, NeXTRTC), 1132 VMSTATE_UINT8(retval, NeXTRTC), 1133 VMSTATE_END_OF_LIST() 1134 }, 1135 }; 1136 1137 static const VMStateDescription next_pc_vmstate = { 1138 .name = "next-pc", 1139 .version_id = 3, 1140 .minimum_version_id = 3, 1141 .fields = (const VMStateField[]) { 1142 VMSTATE_UINT32(scr1, NeXTPC), 1143 VMSTATE_UINT32(scr2, NeXTPC), 1144 VMSTATE_UINT32(old_scr2, NeXTPC), 1145 VMSTATE_UINT32(int_mask, NeXTPC), 1146 VMSTATE_UINT32(int_status, NeXTPC), 1147 VMSTATE_UINT32(led, NeXTPC), 1148 VMSTATE_STRUCT(rtc, NeXTPC, 0, next_rtc_vmstate, NeXTRTC), 1149 VMSTATE_END_OF_LIST() 1150 }, 1151 }; 1152 1153 static void next_pc_class_init(ObjectClass *klass, void *data) 1154 { 1155 DeviceClass *dc = DEVICE_CLASS(klass); 1156 ResettableClass *rc = RESETTABLE_CLASS(klass); 1157 1158 dc->desc = "NeXT Peripheral Controller"; 1159 dc->realize = next_pc_realize; 1160 device_class_set_props(dc, next_pc_properties); 1161 dc->vmsd = &next_pc_vmstate; 1162 rc->phases.hold = next_pc_reset_hold; 1163 } 1164 1165 static const TypeInfo next_pc_info = { 1166 .name = TYPE_NEXT_PC, 1167 .parent = TYPE_SYS_BUS_DEVICE, 1168 .instance_init = next_pc_init, 1169 .instance_size = sizeof(NeXTPC), 1170 .class_init = next_pc_class_init, 1171 }; 1172 1173 static void next_cube_init(MachineState *machine) 1174 { 1175 NeXTState *m = NEXT_MACHINE(machine); 1176 M68kCPU *cpu; 1177 CPUM68KState *env; 1178 MemoryRegion *sysmem = get_system_memory(); 1179 const char *bios_name = machine->firmware ?: ROM_FILE; 1180 DeviceState *pcdev; 1181 1182 /* Initialize the cpu core */ 1183 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 1184 if (!cpu) { 1185 error_report("Unable to find m68k CPU definition"); 1186 exit(1); 1187 } 1188 env = &cpu->env; 1189 1190 /* Initialize CPU registers. */ 1191 env->vbr = 0; 1192 env->sr = 0x2700; 1193 1194 /* Peripheral Controller */ 1195 pcdev = qdev_new(TYPE_NEXT_PC); 1196 object_property_set_link(OBJECT(pcdev), "cpu", OBJECT(cpu), &error_abort); 1197 sysbus_realize_and_unref(SYS_BUS_DEVICE(pcdev), &error_fatal); 1198 1199 /* 64MB RAM starting at 0x04000000 */ 1200 memory_region_add_subregion(sysmem, 0x04000000, machine->ram); 1201 1202 /* Framebuffer */ 1203 sysbus_create_simple(TYPE_NEXTFB, 0x0B000000, NULL); 1204 1205 /* MMIO */ 1206 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02005000); 1207 1208 /* BMAP IO - acts as a catch-all for now */ 1209 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02100000); 1210 1211 /* en network (dummy) */ 1212 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02106000); 1213 1214 /* unknown: Brightness control register? */ 1215 empty_slot_init("next.unknown.0", 0x02110000, 0x10); 1216 /* unknown: Magneto-Optical drive controller? */ 1217 empty_slot_init("next.unknown.1", 0x02112000, 0x10); 1218 1219 /* SCSI */ 1220 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 2, 0x02114000); 1221 /* Floppy */ 1222 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 3, 0x02114108); 1223 /* ESCC */ 1224 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 4, 0x02118000); 1225 1226 /* unknown: Serial clock configuration register? */ 1227 empty_slot_init("next.unknown.2", 0x02118004, 0x10); 1228 1229 /* Timer */ 1230 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 5, 0x0211a000); 1231 1232 /* BMAP memory */ 1233 memory_region_init_ram_flags_nomigrate(&m->bmapm1, NULL, "next.bmapmem", 1234 64, RAM_SHARED, &error_fatal); 1235 memory_region_add_subregion(sysmem, 0x020c0000, &m->bmapm1); 1236 /* The Rev_2.5_v66.bin firmware accesses it at 0x820c0020, too */ 1237 memory_region_init_alias(&m->bmapm2, NULL, "next.bmapmem2", &m->bmapm1, 1238 0x0, 64); 1239 memory_region_add_subregion(sysmem, 0x820c0000, &m->bmapm2); 1240 1241 /* KBD */ 1242 sysbus_create_simple(TYPE_NEXTKBD, 0x0200e000, NULL); 1243 1244 /* Load ROM here */ 1245 memory_region_init_rom(&m->rom, NULL, "next.rom", 0x20000, &error_fatal); 1246 memory_region_add_subregion(sysmem, 0x01000000, &m->rom); 1247 memory_region_init_alias(&m->rom2, NULL, "next.rom2", &m->rom, 0x0, 1248 0x20000); 1249 memory_region_add_subregion(sysmem, 0x0, &m->rom2); 1250 if (load_image_targphys(bios_name, 0x01000000, 0x20000) < 8) { 1251 if (!qtest_enabled()) { 1252 error_report("Failed to load firmware '%s'.", bios_name); 1253 } 1254 } else { 1255 uint8_t *ptr; 1256 /* Initial PC is always at offset 4 in firmware binaries */ 1257 ptr = rom_ptr(0x01000004, 4); 1258 g_assert(ptr != NULL); 1259 env->pc = ldl_be_p(ptr); 1260 if (env->pc >= 0x01020000) { 1261 error_report("'%s' does not seem to be a valid firmware image.", 1262 bios_name); 1263 exit(1); 1264 } 1265 } 1266 1267 /* DMA */ 1268 memory_region_init_io(&m->dmamem, NULL, &next_dma_ops, machine, 1269 "next.dma", 0x5000); 1270 memory_region_add_subregion(sysmem, 0x02000000, &m->dmamem); 1271 } 1272 1273 static void next_machine_class_init(ObjectClass *oc, void *data) 1274 { 1275 MachineClass *mc = MACHINE_CLASS(oc); 1276 1277 mc->desc = "NeXT Cube"; 1278 mc->init = next_cube_init; 1279 mc->block_default_type = IF_SCSI; 1280 mc->default_ram_size = RAM_SIZE; 1281 mc->default_ram_id = "next.ram"; 1282 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); 1283 mc->no_cdrom = true; 1284 } 1285 1286 static const TypeInfo next_typeinfo = { 1287 .name = TYPE_NEXT_MACHINE, 1288 .parent = TYPE_MACHINE, 1289 .class_init = next_machine_class_init, 1290 .instance_size = sizeof(NeXTState), 1291 }; 1292 1293 static void next_register_type(void) 1294 { 1295 type_register_static(&next_typeinfo); 1296 type_register_static(&next_pc_info); 1297 type_register_static(&next_scsi_info); 1298 } 1299 1300 type_init(next_register_type) 1301