1 /* 2 * NeXT Cube System Driver 3 * 4 * Copyright (c) 2011 Bryce Lanham 5 * 6 * This code is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published 8 * by the Free Software Foundation; either version 2 of the License, 9 * or (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "exec/hwaddr.h" 14 #include "system/system.h" 15 #include "system/qtest.h" 16 #include "hw/irq.h" 17 #include "hw/m68k/next-cube.h" 18 #include "hw/boards.h" 19 #include "hw/loader.h" 20 #include "hw/scsi/esp.h" 21 #include "hw/sysbus.h" 22 #include "qom/object.h" 23 #include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */ 24 #include "hw/block/fdc.h" 25 #include "hw/misc/empty_slot.h" 26 #include "hw/qdev-properties.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "ui/console.h" 30 #include "target/m68k/cpu.h" 31 #include "migration/vmstate.h" 32 33 /* #define DEBUG_NEXT */ 34 #ifdef DEBUG_NEXT 35 #define DPRINTF(fmt, ...) \ 36 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0) 37 #else 38 #define DPRINTF(fmt, ...) do { } while (0) 39 #endif 40 41 #define ENTRY 0x0100001e 42 #define RAM_SIZE 0x4000000 43 #define ROM_FILE "Rev_2.5_v66.bin" 44 45 46 #define TYPE_NEXT_RTC "next-rtc" 47 OBJECT_DECLARE_SIMPLE_TYPE(NeXTRTC, NEXT_RTC) 48 49 struct NeXTRTC { 50 SysBusDevice parent_obj; 51 52 int8_t phase; 53 uint8_t ram[32]; 54 uint8_t command; 55 uint8_t value; 56 uint8_t status; 57 uint8_t control; 58 uint8_t retval; 59 60 qemu_irq data_out_irq; 61 qemu_irq power_irq; 62 }; 63 64 #define TYPE_NEXT_SCSI "next-scsi" 65 OBJECT_DECLARE_SIMPLE_TYPE(NeXTSCSI, NEXT_SCSI) 66 67 /* NeXT SCSI Controller */ 68 struct NeXTSCSI { 69 SysBusDevice parent_obj; 70 71 MemoryRegion scsi_mem; 72 73 SysBusESPState sysbus_esp; 74 75 MemoryRegion scsi_csr_mem; 76 uint8_t scsi_csr_1; 77 uint8_t scsi_csr_2; 78 }; 79 80 #define TYPE_NEXT_PC "next-pc" 81 OBJECT_DECLARE_SIMPLE_TYPE(NeXTPC, NEXT_PC) 82 83 /* NeXT Peripheral Controller */ 84 struct NeXTPC { 85 SysBusDevice parent_obj; 86 87 M68kCPU *cpu; 88 89 MemoryRegion floppy_mem; 90 MemoryRegion timer_mem; 91 MemoryRegion dummyen_mem; 92 MemoryRegion mmiomem; 93 MemoryRegion scrmem; 94 95 uint32_t scr1; 96 uint32_t scr2; 97 uint32_t old_scr2; 98 uint32_t int_mask; 99 uint32_t int_status; 100 uint32_t led; 101 102 NeXTSCSI next_scsi; 103 104 qemu_irq scsi_reset; 105 qemu_irq scsi_dma; 106 107 ESCCState escc; 108 109 NeXTRTC rtc; 110 qemu_irq rtc_data_irq; 111 qemu_irq rtc_cmd_reset_irq; 112 }; 113 114 typedef struct next_dma { 115 uint32_t csr; 116 117 uint32_t saved_next; 118 uint32_t saved_limit; 119 uint32_t saved_start; 120 uint32_t saved_stop; 121 122 uint32_t next; 123 uint32_t limit; 124 uint32_t start; 125 uint32_t stop; 126 127 uint32_t next_initbuf; 128 uint32_t size; 129 } next_dma; 130 131 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube") 132 OBJECT_DECLARE_SIMPLE_TYPE(NeXTState, NEXT_MACHINE) 133 134 struct NeXTState { 135 MachineState parent; 136 137 MemoryRegion rom; 138 MemoryRegion rom2; 139 MemoryRegion dmamem; 140 MemoryRegion bmapm1; 141 MemoryRegion bmapm2; 142 143 next_dma dma[10]; 144 }; 145 146 /* Thanks to NeXT forums for this */ 147 /* 148 static const uint8_t rtc_ram3[32] = { 149 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 150 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00, 151 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00, 152 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13 153 }; 154 */ 155 static const uint8_t rtc_ram2[32] = { 156 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00, 157 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00, 158 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 159 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e, 160 }; 161 162 #define SCR2_RTCLK 0x2 163 #define SCR2_RTDATA 0x4 164 #define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10)) 165 166 static void next_scr2_led_update(NeXTPC *s) 167 { 168 if (s->scr2 & 0x1) { 169 DPRINTF("fault!\n"); 170 s->led++; 171 if (s->led == 10) { 172 DPRINTF("LED flashing, possible fault!\n"); 173 s->led = 0; 174 } 175 } 176 } 177 178 static void next_scr2_rtc_update(NeXTPC *s) 179 { 180 uint8_t old_scr2_rtc, scr2_rtc; 181 182 old_scr2_rtc = extract32(s->old_scr2, 8, 8); 183 scr2_rtc = extract32(s->scr2, 8, 8); 184 185 if (scr2_rtc & 0x1) { 186 /* DPRINTF("RTC %x phase %i\n", scr2_2, rtc->phase); */ 187 /* If we are in going down clock... do something */ 188 if (((old_scr2_rtc & SCR2_RTCLK) != (scr2_rtc & SCR2_RTCLK)) && 189 ((scr2_rtc & SCR2_RTCLK) == 0)) { 190 if (scr2_rtc & SCR2_RTDATA) { 191 qemu_irq_raise(s->rtc_data_irq); 192 } else { 193 qemu_irq_lower(s->rtc_data_irq); 194 } 195 } 196 } else { 197 /* else end or abort */ 198 qemu_irq_raise(s->rtc_cmd_reset_irq); 199 } 200 } 201 202 static uint64_t next_mmio_read(void *opaque, hwaddr addr, unsigned size) 203 { 204 NeXTPC *s = NEXT_PC(opaque); 205 uint64_t val; 206 207 switch (addr) { 208 case 0x2000: /* 0x2007000 */ 209 /* DPRINTF("Read INT status: %x\n", s->int_status); */ 210 val = s->int_status; 211 break; 212 213 case 0x2800: /* 0x2007800 */ 214 DPRINTF("MMIO Read INT mask: %x\n", s->int_mask); 215 val = s->int_mask; 216 break; 217 218 case 0x7000 ... 0x7003: /* 0x200c000 */ 219 val = extract32(s->scr1, (4 - (addr - 0x7000) - size) << 3, 220 size << 3); 221 break; 222 223 case 0x8000 ... 0x8003: /* 0x200d000 */ 224 val = extract32(s->scr2, (4 - (addr - 0x8000) - size) << 3, 225 size << 3); 226 break; 227 228 default: 229 val = 0; 230 DPRINTF("MMIO Read @ 0x%"HWADDR_PRIx" size %d\n", addr, size); 231 break; 232 } 233 234 return val; 235 } 236 237 static void next_mmio_write(void *opaque, hwaddr addr, uint64_t val, 238 unsigned size) 239 { 240 NeXTPC *s = NEXT_PC(opaque); 241 242 switch (addr) { 243 case 0x2000: /* 0x2007000 */ 244 DPRINTF("INT Status old: %x new: %x\n", s->int_status, 245 (unsigned int)val); 246 s->int_status = val; 247 break; 248 249 case 0x2800: /* 0x2007800 */ 250 DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, (unsigned int)val); 251 s->int_mask = val; 252 break; 253 254 case 0x7000 ... 0x7003: /* 0x200c000 */ 255 DPRINTF("SCR1 Write: %x\n", (unsigned int)val); 256 s->scr1 = deposit32(s->scr1, (4 - (addr - 0x7000) - size) << 3, 257 size << 3, val); 258 break; 259 260 case 0x8000 ... 0x8003: /* 0x200d000 */ 261 s->scr2 = deposit32(s->scr2, (4 - (addr - 0x8000) - size) << 3, 262 size << 3, val); 263 next_scr2_led_update(s); 264 next_scr2_rtc_update(s); 265 s->old_scr2 = s->scr2; 266 break; 267 268 default: 269 DPRINTF("MMIO Write @ 0x%"HWADDR_PRIx " with 0x%x size %u\n", addr, 270 (unsigned int)val, size); 271 } 272 } 273 274 static const MemoryRegionOps next_mmio_ops = { 275 .read = next_mmio_read, 276 .write = next_mmio_write, 277 .valid.min_access_size = 1, 278 .valid.max_access_size = 4, 279 .endianness = DEVICE_BIG_ENDIAN, 280 }; 281 282 #define SCSICSR_ENABLE 0x01 283 #define SCSICSR_RESET 0x02 /* reset scsi dma */ 284 #define SCSICSR_FIFOFL 0x04 285 #define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */ 286 #define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */ 287 #define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */ 288 289 #define NEXTDMA_SCSI(x) (0x10 + x) 290 #define NEXTDMA_FD(x) (0x10 + x) 291 #define NEXTDMA_ENTX(x) (0x110 + x) 292 #define NEXTDMA_ENRX(x) (0x150 + x) 293 #define NEXTDMA_CSR 0x0 294 #define NEXTDMA_NEXT 0x4000 295 #define NEXTDMA_LIMIT 0x4004 296 #define NEXTDMA_START 0x4008 297 #define NEXTDMA_STOP 0x400c 298 #define NEXTDMA_NEXT_INIT 0x4200 299 #define NEXTDMA_SIZE 0x4204 300 301 static void next_dma_write(void *opaque, hwaddr addr, uint64_t val, 302 unsigned int size) 303 { 304 NeXTState *next_state = NEXT_MACHINE(opaque); 305 306 switch (addr) { 307 case NEXTDMA_ENRX(NEXTDMA_CSR): 308 if (val & DMA_DEV2M) { 309 next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M; 310 } 311 312 if (val & DMA_SETENABLE) { 313 /* DPRINTF("SCSI DMA ENABLE\n"); */ 314 next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE; 315 } 316 if (val & DMA_SETSUPDATE) { 317 next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE; 318 } 319 if (val & DMA_CLRCOMPLETE) { 320 next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE; 321 } 322 323 if (val & DMA_RESET) { 324 next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 325 DMA_ENABLE | DMA_DEV2M); 326 } 327 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 328 break; 329 330 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 331 next_state->dma[NEXTDMA_ENRX].next_initbuf = val; 332 break; 333 334 case NEXTDMA_ENRX(NEXTDMA_NEXT): 335 next_state->dma[NEXTDMA_ENRX].next = val; 336 break; 337 338 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 339 next_state->dma[NEXTDMA_ENRX].limit = val; 340 break; 341 342 case NEXTDMA_SCSI(NEXTDMA_CSR): 343 if (val & DMA_DEV2M) { 344 next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M; 345 } 346 if (val & DMA_SETENABLE) { 347 /* DPRINTF("SCSI DMA ENABLE\n"); */ 348 next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE; 349 } 350 if (val & DMA_SETSUPDATE) { 351 next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE; 352 } 353 if (val & DMA_CLRCOMPLETE) { 354 next_state->dma[NEXTDMA_SCSI].csr &= ~DMA_COMPLETE; 355 } 356 357 if (val & DMA_RESET) { 358 next_state->dma[NEXTDMA_SCSI].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 359 DMA_ENABLE | DMA_DEV2M); 360 /* DPRINTF("SCSI DMA RESET\n"); */ 361 } 362 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 363 break; 364 365 case NEXTDMA_SCSI(NEXTDMA_NEXT): 366 next_state->dma[NEXTDMA_SCSI].next = val; 367 break; 368 369 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 370 next_state->dma[NEXTDMA_SCSI].limit = val; 371 break; 372 373 case NEXTDMA_SCSI(NEXTDMA_START): 374 next_state->dma[NEXTDMA_SCSI].start = val; 375 break; 376 377 case NEXTDMA_SCSI(NEXTDMA_STOP): 378 next_state->dma[NEXTDMA_SCSI].stop = val; 379 break; 380 381 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 382 next_state->dma[NEXTDMA_SCSI].next_initbuf = val; 383 break; 384 385 default: 386 DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)val); 387 } 388 } 389 390 static uint64_t next_dma_read(void *opaque, hwaddr addr, unsigned int size) 391 { 392 NeXTState *next_state = NEXT_MACHINE(opaque); 393 uint64_t val; 394 395 switch (addr) { 396 case NEXTDMA_SCSI(NEXTDMA_CSR): 397 DPRINTF("SCSI DMA CSR READ\n"); 398 val = next_state->dma[NEXTDMA_SCSI].csr; 399 break; 400 401 case NEXTDMA_ENRX(NEXTDMA_CSR): 402 val = next_state->dma[NEXTDMA_ENRX].csr; 403 break; 404 405 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 406 val = next_state->dma[NEXTDMA_ENRX].next_initbuf; 407 break; 408 409 case NEXTDMA_ENRX(NEXTDMA_NEXT): 410 val = next_state->dma[NEXTDMA_ENRX].next; 411 break; 412 413 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 414 val = next_state->dma[NEXTDMA_ENRX].limit; 415 break; 416 417 case NEXTDMA_SCSI(NEXTDMA_NEXT): 418 val = next_state->dma[NEXTDMA_SCSI].next; 419 break; 420 421 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 422 val = next_state->dma[NEXTDMA_SCSI].next_initbuf; 423 break; 424 425 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 426 val = next_state->dma[NEXTDMA_SCSI].limit; 427 break; 428 429 case NEXTDMA_SCSI(NEXTDMA_START): 430 val = next_state->dma[NEXTDMA_SCSI].start; 431 break; 432 433 case NEXTDMA_SCSI(NEXTDMA_STOP): 434 val = next_state->dma[NEXTDMA_SCSI].stop; 435 break; 436 437 default: 438 DPRINTF("DMA read @ %x\n", (unsigned int)addr); 439 val = 0; 440 } 441 442 /* 443 * once the csr's are done, subtract 0x3FEC from the addr, and that will 444 * normalize the upper registers 445 */ 446 447 return val; 448 } 449 450 static const MemoryRegionOps next_dma_ops = { 451 .read = next_dma_read, 452 .write = next_dma_write, 453 .impl.min_access_size = 4, 454 .valid.min_access_size = 4, 455 .valid.max_access_size = 4, 456 .endianness = DEVICE_BIG_ENDIAN, 457 }; 458 459 static void next_irq(void *opaque, int number, int level) 460 { 461 NeXTPC *s = NEXT_PC(opaque); 462 M68kCPU *cpu = s->cpu; 463 int shift = 0; 464 465 /* first switch sets interrupt status */ 466 /* DPRINTF("IRQ %i\n",number); */ 467 switch (number) { 468 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 469 case NEXT_FD_I: 470 shift = 7; 471 break; 472 case NEXT_KBD_I: 473 shift = 3; 474 break; 475 case NEXT_PWR_I: 476 shift = 2; 477 break; 478 case NEXT_ENRX_I: 479 shift = 9; 480 break; 481 case NEXT_ENTX_I: 482 shift = 10; 483 break; 484 case NEXT_SCSI_I: 485 shift = 12; 486 break; 487 case NEXT_CLK_I: 488 shift = 5; 489 break; 490 491 /* level 5 - scc (serial) */ 492 case NEXT_SCC_I: 493 shift = 17; 494 break; 495 496 /* level 6 - audio etherrx/tx dma */ 497 case NEXT_ENTX_DMA_I: 498 shift = 28; 499 break; 500 case NEXT_ENRX_DMA_I: 501 shift = 27; 502 break; 503 case NEXT_SCSI_DMA_I: 504 shift = 26; 505 break; 506 case NEXT_SND_I: 507 shift = 23; 508 break; 509 case NEXT_SCC_DMA_I: 510 shift = 21; 511 break; 512 513 } 514 /* 515 * this HAS to be wrong, the interrupt handlers in mach and together 516 * int_status and int_mask and return if there is a hit 517 */ 518 if (s->int_mask & (1 << shift)) { 519 DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc); 520 /* return; */ 521 } 522 523 /* second switch triggers the correct interrupt */ 524 if (level) { 525 s->int_status |= 1 << shift; 526 527 switch (number) { 528 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 529 case NEXT_FD_I: 530 case NEXT_KBD_I: 531 case NEXT_PWR_I: 532 case NEXT_ENRX_I: 533 case NEXT_ENTX_I: 534 case NEXT_SCSI_I: 535 case NEXT_CLK_I: 536 m68k_set_irq_level(cpu, 3, 27); 537 break; 538 539 /* level 5 - scc (serial) */ 540 case NEXT_SCC_I: 541 m68k_set_irq_level(cpu, 5, 29); 542 break; 543 544 /* level 6 - audio etherrx/tx dma */ 545 case NEXT_ENTX_DMA_I: 546 case NEXT_ENRX_DMA_I: 547 case NEXT_SCSI_DMA_I: 548 case NEXT_SND_I: 549 case NEXT_SCC_DMA_I: 550 m68k_set_irq_level(cpu, 6, 30); 551 break; 552 } 553 } else { 554 s->int_status &= ~(1 << shift); 555 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); 556 } 557 } 558 559 static void nextdma_write(void *opaque, uint8_t *buf, int size, int type) 560 { 561 uint32_t base_addr; 562 int irq = 0; 563 uint8_t align = 16; 564 NeXTState *next_state = NEXT_MACHINE(qdev_get_machine()); 565 566 if (type == NEXTDMA_ENRX || type == NEXTDMA_ENTX) { 567 align = 32; 568 } 569 /* Most DMA is supposedly 16 byte aligned */ 570 if ((size % align) != 0) { 571 size -= size % align; 572 size += align; 573 } 574 575 /* 576 * prom sets the dma start using initbuf while the bootloader uses next 577 * so we check to see if initbuf is 0 578 */ 579 if (next_state->dma[type].next_initbuf == 0) { 580 base_addr = next_state->dma[type].next; 581 } else { 582 base_addr = next_state->dma[type].next_initbuf; 583 } 584 585 cpu_physical_memory_write(base_addr, buf, size); 586 587 next_state->dma[type].next_initbuf = 0; 588 589 /* saved limit is checked to calculate packet size by both, rom and netbsd */ 590 next_state->dma[type].saved_limit = (next_state->dma[type].next + size); 591 next_state->dma[type].saved_next = (next_state->dma[type].next); 592 593 /* 594 * 32 bytes under savedbase seems to be some kind of register 595 * of which the purpose is unknown as of yet 596 */ 597 /* stl_phys(s->rx_dma.base-32,0xFFFFFFFF); */ 598 599 if (!(next_state->dma[type].csr & DMA_SUPDATE)) { 600 next_state->dma[type].next = next_state->dma[type].start; 601 next_state->dma[type].limit = next_state->dma[type].stop; 602 } 603 604 /* Set dma registers and raise an irq */ 605 next_state->dma[type].csr |= DMA_COMPLETE; /* DON'T CHANGE THIS! */ 606 607 switch (type) { 608 case NEXTDMA_SCSI: 609 irq = NEXT_SCSI_DMA_I; 610 break; 611 } 612 613 next_irq(opaque, irq, 1); 614 next_irq(opaque, irq, 0); 615 } 616 617 static void nextscsi_read(void *opaque, uint8_t *buf, int len) 618 { 619 DPRINTF("SCSI READ: %x\n", len); 620 abort(); 621 } 622 623 static void nextscsi_write(void *opaque, uint8_t *buf, int size) 624 { 625 DPRINTF("SCSI WRITE: %i\n", size); 626 nextdma_write(opaque, buf, size, NEXTDMA_SCSI); 627 } 628 629 static void next_scsi_csr_write(void *opaque, hwaddr addr, uint64_t val, 630 unsigned size) 631 { 632 NeXTSCSI *s = NEXT_SCSI(opaque); 633 NeXTPC *pc = NEXT_PC(container_of(s, NeXTPC, next_scsi)); 634 635 switch (addr) { 636 case 0: 637 if (val & SCSICSR_FIFOFL) { 638 DPRINTF("SCSICSR FIFO Flush\n"); 639 /* will have to add another irq to the esp if this is needed */ 640 /* esp_puflush_fifo(esp_g); */ 641 } 642 643 if (val & SCSICSR_ENABLE) { 644 DPRINTF("SCSICSR Enable\n"); 645 /* 646 * qemu_irq_raise(s->scsi_dma); 647 * s->scsi_csr_1 = 0xc0; 648 * s->scsi_csr_1 |= 0x1; 649 * qemu_irq_pulse(s->scsi_dma); 650 */ 651 } 652 /* 653 * else 654 * s->scsi_csr_1 &= ~SCSICSR_ENABLE; 655 */ 656 657 if (val & SCSICSR_RESET) { 658 DPRINTF("SCSICSR Reset\n"); 659 /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */ 660 qemu_irq_raise(pc->scsi_reset); 661 s->scsi_csr_1 &= ~(SCSICSR_INTMASK | 0x80 | 0x1); 662 qemu_irq_lower(pc->scsi_reset); 663 } 664 if (val & SCSICSR_DMADIR) { 665 DPRINTF("SCSICSR DMAdir\n"); 666 } 667 if (val & SCSICSR_CPUDMA) { 668 DPRINTF("SCSICSR CPUDMA\n"); 669 /* qemu_irq_raise(s->scsi_dma); */ 670 pc->int_status |= 0x4000000; 671 } else { 672 /* fprintf(stderr,"SCSICSR CPUDMA disabled\n"); */ 673 pc->int_status &= ~(0x4000000); 674 /* qemu_irq_lower(s->scsi_dma); */ 675 } 676 if (val & SCSICSR_INTMASK) { 677 DPRINTF("SCSICSR INTMASK\n"); 678 /* 679 * int_mask &= ~0x1000; 680 * s->scsi_csr_1 |= val; 681 * s->scsi_csr_1 &= ~SCSICSR_INTMASK; 682 * if (s->scsi_queued) { 683 * s->scsi_queued = 0; 684 * next_irq(s, NEXT_SCSI_I, level); 685 * } 686 */ 687 } else { 688 /* int_mask |= 0x1000; */ 689 } 690 if (val & 0x80) { 691 /* int_mask |= 0x1000; */ 692 /* s->scsi_csr_1 |= 0x80; */ 693 } 694 DPRINTF("SCSICSR1 Write: %"PRIx64 "\n", val); 695 s->scsi_csr_1 = val; 696 break; 697 698 case 1: 699 DPRINTF("SCSICSR2 Write: %"PRIx64 "\n", val); 700 s->scsi_csr_2 = val; 701 break; 702 703 default: 704 g_assert_not_reached(); 705 } 706 } 707 708 static uint64_t next_scsi_csr_read(void *opaque, hwaddr addr, unsigned size) 709 { 710 NeXTSCSI *s = NEXT_SCSI(opaque); 711 uint64_t val; 712 713 switch (addr) { 714 case 0: 715 DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1); 716 val = s->scsi_csr_1; 717 break; 718 719 case 1: 720 DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2); 721 val = s->scsi_csr_2; 722 break; 723 724 default: 725 g_assert_not_reached(); 726 } 727 728 return val; 729 } 730 731 static const MemoryRegionOps next_scsi_csr_ops = { 732 .read = next_scsi_csr_read, 733 .write = next_scsi_csr_write, 734 .valid.min_access_size = 1, 735 .valid.max_access_size = 1, 736 .endianness = DEVICE_BIG_ENDIAN, 737 }; 738 739 static void next_scsi_init(Object *obj) 740 { 741 NeXTSCSI *s = NEXT_SCSI(obj); 742 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 743 744 object_initialize_child(obj, "esp", &s->sysbus_esp, TYPE_SYSBUS_ESP); 745 746 memory_region_init_io(&s->scsi_csr_mem, obj, &next_scsi_csr_ops, 747 s, "csrs", 2); 748 749 memory_region_init(&s->scsi_mem, obj, "next.scsi", 0x40); 750 sysbus_init_mmio(sbd, &s->scsi_mem); 751 } 752 753 static void next_scsi_realize(DeviceState *dev, Error **errp) 754 { 755 NeXTSCSI *s = NEXT_SCSI(dev); 756 SysBusESPState *sysbus_esp; 757 SysBusDevice *sbd; 758 ESPState *esp; 759 NeXTPC *pcdev; 760 761 pcdev = NEXT_PC(container_of(s, NeXTPC, next_scsi)); 762 763 /* ESP */ 764 sysbus_esp = SYSBUS_ESP(&s->sysbus_esp); 765 esp = &sysbus_esp->esp; 766 esp->dma_memory_read = nextscsi_read; 767 esp->dma_memory_write = nextscsi_write; 768 esp->dma_opaque = pcdev; 769 sysbus_esp->it_shift = 0; 770 esp->dma_enabled = 1; 771 sbd = SYS_BUS_DEVICE(sysbus_esp); 772 if (!sysbus_realize(sbd, errp)) { 773 return; 774 } 775 memory_region_add_subregion(&s->scsi_mem, 0x0, 776 sysbus_mmio_get_region(sbd, 0)); 777 778 /* SCSI CSRs */ 779 memory_region_add_subregion(&s->scsi_mem, 0x20, &s->scsi_csr_mem); 780 781 scsi_bus_legacy_handle_cmdline(&s->sysbus_esp.esp.bus); 782 } 783 784 static const VMStateDescription next_scsi_vmstate = { 785 .name = "next-scsi", 786 .version_id = 0, 787 .minimum_version_id = 0, 788 .fields = (const VMStateField[]) { 789 VMSTATE_UINT8(scsi_csr_1, NeXTSCSI), 790 VMSTATE_UINT8(scsi_csr_2, NeXTSCSI), 791 VMSTATE_END_OF_LIST() 792 }, 793 }; 794 795 static void next_scsi_class_init(ObjectClass *klass, void *data) 796 { 797 DeviceClass *dc = DEVICE_CLASS(klass); 798 799 dc->desc = "NeXT SCSI Controller"; 800 dc->realize = next_scsi_realize; 801 dc->vmsd = &next_scsi_vmstate; 802 } 803 804 static const TypeInfo next_scsi_info = { 805 .name = TYPE_NEXT_SCSI, 806 .parent = TYPE_SYS_BUS_DEVICE, 807 .instance_init = next_scsi_init, 808 .instance_size = sizeof(NeXTSCSI), 809 .class_init = next_scsi_class_init, 810 }; 811 812 static void next_floppy_write(void *opaque, hwaddr addr, uint64_t val, 813 unsigned size) 814 { 815 switch (addr) { 816 case 0: 817 DPRINTF("FDCSR Write: %"PRIx64 "\n", val); 818 if (val == 0x0) { 819 /* qemu_irq_raise(s->fd_irq[0]); */ 820 } 821 break; 822 823 default: 824 g_assert_not_reached(); 825 } 826 } 827 828 static uint64_t next_floppy_read(void *opaque, hwaddr addr, unsigned size) 829 { 830 uint64_t val; 831 832 switch (addr) { 833 case 0: 834 DPRINTF("FD read @ %x\n", (unsigned int)addr); 835 val = 0x40 | 0x04 | 0x2 | 0x1; 836 break; 837 838 default: 839 g_assert_not_reached(); 840 } 841 842 return val; 843 } 844 845 static const MemoryRegionOps next_floppy_ops = { 846 .read = next_floppy_read, 847 .write = next_floppy_write, 848 .valid.min_access_size = 1, 849 .valid.max_access_size = 4, 850 .endianness = DEVICE_BIG_ENDIAN, 851 }; 852 853 static void next_timer_write(void *opaque, hwaddr addr, uint64_t val, 854 unsigned size) 855 { 856 switch (addr) { 857 case 0 ... 3: 858 /* Hardware timer latch - not implemented yet */ 859 break; 860 861 default: 862 g_assert_not_reached(); 863 } 864 } 865 866 static uint64_t next_timer_read(void *opaque, hwaddr addr, unsigned size) 867 { 868 uint64_t val; 869 870 switch (addr) { 871 case 0 ... 3: 872 /* 873 * These 4 registers are the hardware timer, not sure which register 874 * is the latch instead of data, but no problems so far. 875 * 876 * Hack: We need to have the LSB change consistently to make it work 877 */ 878 val = extract32(clock(), (4 - addr - size) << 3, 879 size << 3); 880 break; 881 882 default: 883 g_assert_not_reached(); 884 } 885 886 return val; 887 } 888 889 static const MemoryRegionOps next_timer_ops = { 890 .read = next_timer_read, 891 .write = next_timer_write, 892 .valid.min_access_size = 1, 893 .valid.max_access_size = 4, 894 .endianness = DEVICE_BIG_ENDIAN, 895 }; 896 897 static void next_dummy_en_write(void *opaque, hwaddr addr, uint64_t val, 898 unsigned size) 899 { 900 /* Do nothing */ 901 return; 902 } 903 904 static uint64_t next_dummy_en_read(void *opaque, hwaddr addr, unsigned size) 905 { 906 uint64_t val; 907 908 switch (addr) { 909 case 0: 910 /* For now return dummy byte to allow the Ethernet test to timeout */ 911 val = 0xff; 912 break; 913 914 default: 915 val = 0; 916 } 917 918 return val; 919 } 920 921 static const MemoryRegionOps next_dummy_en_ops = { 922 .read = next_dummy_en_read, 923 .write = next_dummy_en_write, 924 .valid.min_access_size = 1, 925 .valid.max_access_size = 4, 926 .endianness = DEVICE_BIG_ENDIAN, 927 }; 928 929 static bool next_rtc_cmd_is_write(uint8_t cmd) 930 { 931 return (cmd >= 0x80 && cmd <= 0x9f) || 932 (cmd == 0xb1); 933 } 934 935 static void next_rtc_data_in_irq(void *opaque, int n, int level) 936 { 937 NeXTRTC *rtc = NEXT_RTC(opaque); 938 939 if (rtc->phase < 8) { 940 rtc->command = (rtc->command << 1) | level; 941 942 if (rtc->phase == 7 && !next_rtc_cmd_is_write(rtc->command)) { 943 if (rtc->command <= 0x1f) { 944 /* RAM registers */ 945 rtc->retval = rtc->ram[rtc->command]; 946 } 947 if ((rtc->command >= 0x20) && (rtc->command <= 0x2f)) { 948 /* RTC */ 949 time_t time_h = time(NULL); 950 struct tm *info = localtime(&time_h); 951 rtc->retval = 0; 952 953 switch (rtc->command) { 954 case 0x20: 955 rtc->retval = SCR2_TOBCD(info->tm_sec); 956 break; 957 case 0x21: 958 rtc->retval = SCR2_TOBCD(info->tm_min); 959 break; 960 case 0x22: 961 rtc->retval = SCR2_TOBCD(info->tm_hour); 962 break; 963 case 0x24: 964 rtc->retval = SCR2_TOBCD(info->tm_mday); 965 break; 966 case 0x25: 967 rtc->retval = SCR2_TOBCD((info->tm_mon + 1)); 968 break; 969 case 0x26: 970 rtc->retval = SCR2_TOBCD((info->tm_year - 100)); 971 break; 972 } 973 } 974 if (rtc->command == 0x30) { 975 /* read the status 0x30 */ 976 rtc->retval = rtc->status; 977 } 978 if (rtc->command == 0x31) { 979 /* read the control 0x31 */ 980 rtc->retval = rtc->control; 981 } 982 } 983 } 984 if (rtc->phase >= 8 && rtc->phase < 16) { 985 if (next_rtc_cmd_is_write(rtc->command)) { 986 /* Shift in value to write */ 987 rtc->value = (rtc->value << 1) | level; 988 } else { 989 /* Shift out value to read */ 990 if (rtc->retval & (0x80 >> (rtc->phase - 8))) { 991 qemu_irq_raise(rtc->data_out_irq); 992 } else { 993 qemu_irq_lower(rtc->data_out_irq); 994 } 995 } 996 } 997 998 rtc->phase++; 999 if (rtc->phase == 16 && next_rtc_cmd_is_write(rtc->command)) { 1000 if (rtc->command >= 0x80 && rtc->command <= 0x9f) { 1001 /* RAM registers */ 1002 rtc->ram[rtc->command - 0x80] = rtc->value; 1003 } 1004 if (rtc->command == 0xb1) { 1005 /* write to 0x30 register */ 1006 if (rtc->value & 0x04) { 1007 /* clear FTU */ 1008 rtc->status = rtc->status & (~0x18); 1009 qemu_irq_lower(rtc->power_irq); 1010 } 1011 } 1012 } 1013 } 1014 1015 static void next_rtc_cmd_reset_irq(void *opaque, int n, int level) 1016 { 1017 NeXTRTC *rtc = NEXT_RTC(opaque); 1018 1019 if (level) { 1020 rtc->phase = 0; 1021 rtc->command = 0; 1022 rtc->value = 0; 1023 } 1024 } 1025 1026 static void next_rtc_reset_hold(Object *obj, ResetType type) 1027 { 1028 NeXTRTC *rtc = NEXT_RTC(obj); 1029 1030 rtc->status = 0x90; 1031 1032 /* Load RTC RAM - TODO: provide possibility to load contents from file */ 1033 memcpy(rtc->ram, rtc_ram2, 32); 1034 } 1035 1036 static void next_rtc_init(Object *obj) 1037 { 1038 NeXTRTC *rtc = NEXT_RTC(obj); 1039 1040 qdev_init_gpio_in_named(DEVICE(obj), next_rtc_data_in_irq, 1041 "rtc-data-in", 1); 1042 qdev_init_gpio_out_named(DEVICE(obj), &rtc->data_out_irq, 1043 "rtc-data-out", 1); 1044 qdev_init_gpio_in_named(DEVICE(obj), next_rtc_cmd_reset_irq, 1045 "rtc-cmd-reset", 1); 1046 qdev_init_gpio_out_named(DEVICE(obj), &rtc->power_irq, 1047 "rtc-power-out", 1); 1048 } 1049 1050 static const VMStateDescription next_rtc_vmstate = { 1051 .name = "next-rtc", 1052 .version_id = 3, 1053 .minimum_version_id = 3, 1054 .fields = (const VMStateField[]) { 1055 VMSTATE_INT8(phase, NeXTRTC), 1056 VMSTATE_UINT8_ARRAY(ram, NeXTRTC, 32), 1057 VMSTATE_UINT8(command, NeXTRTC), 1058 VMSTATE_UINT8(value, NeXTRTC), 1059 VMSTATE_UINT8(status, NeXTRTC), 1060 VMSTATE_UINT8(control, NeXTRTC), 1061 VMSTATE_UINT8(retval, NeXTRTC), 1062 VMSTATE_END_OF_LIST() 1063 }, 1064 }; 1065 1066 static void next_rtc_class_init(ObjectClass *klass, void *data) 1067 { 1068 DeviceClass *dc = DEVICE_CLASS(klass); 1069 ResettableClass *rc = RESETTABLE_CLASS(klass); 1070 1071 dc->desc = "NeXT RTC"; 1072 dc->vmsd = &next_rtc_vmstate; 1073 rc->phases.hold = next_rtc_reset_hold; 1074 } 1075 1076 static const TypeInfo next_rtc_info = { 1077 .name = TYPE_NEXT_RTC, 1078 .parent = TYPE_SYS_BUS_DEVICE, 1079 .instance_init = next_rtc_init, 1080 .instance_size = sizeof(NeXTRTC), 1081 .class_init = next_rtc_class_init, 1082 }; 1083 1084 static void next_pc_rtc_data_in_irq(void *opaque, int n, int level) 1085 { 1086 NeXTPC *s = NEXT_PC(opaque); 1087 uint8_t scr2_2 = extract32(s->scr2, 8, 8); 1088 1089 if (level) { 1090 scr2_2 |= SCR2_RTDATA; 1091 } else { 1092 scr2_2 &= ~SCR2_RTDATA; 1093 } 1094 1095 s->scr2 = deposit32(s->scr2, 8, 8, scr2_2); 1096 } 1097 1098 static void next_pc_reset_hold(Object *obj, ResetType type) 1099 { 1100 NeXTPC *s = NEXT_PC(obj); 1101 1102 /* Set internal registers to initial values */ 1103 /* 0x0000XX00 << vital bits */ 1104 s->scr1 = 0x00011102; 1105 s->scr2 = 0x00ff0c80; 1106 s->old_scr2 = s->scr2; 1107 } 1108 1109 static void next_pc_realize(DeviceState *dev, Error **errp) 1110 { 1111 NeXTPC *s = NEXT_PC(dev); 1112 SysBusDevice *sbd; 1113 DeviceState *d; 1114 1115 /* SCSI */ 1116 sbd = SYS_BUS_DEVICE(&s->next_scsi); 1117 if (!sysbus_realize(sbd, errp)) { 1118 return; 1119 } 1120 1121 d = DEVICE(object_resolve_path_component(OBJECT(&s->next_scsi), "esp")); 1122 sysbus_connect_irq(SYS_BUS_DEVICE(d), 0, 1123 qdev_get_gpio_in(DEVICE(s), NEXT_SCSI_I)); 1124 1125 s->scsi_reset = qdev_get_gpio_in(d, 0); 1126 s->scsi_dma = qdev_get_gpio_in(d, 1); 1127 1128 /* ESCC */ 1129 d = DEVICE(&s->escc); 1130 qdev_prop_set_uint32(d, "disabled", 0); 1131 qdev_prop_set_uint32(d, "frequency", 9600 * 384); 1132 qdev_prop_set_uint32(d, "it_shift", 0); 1133 qdev_prop_set_bit(d, "bit_swap", true); 1134 qdev_prop_set_chr(d, "chrB", serial_hd(1)); 1135 qdev_prop_set_chr(d, "chrA", serial_hd(0)); 1136 qdev_prop_set_uint32(d, "chnBtype", escc_serial); 1137 qdev_prop_set_uint32(d, "chnAtype", escc_serial); 1138 1139 sbd = SYS_BUS_DEVICE(d); 1140 if (!sysbus_realize(sbd, errp)) { 1141 return; 1142 } 1143 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(dev, NEXT_SCC_I)); 1144 sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(dev, NEXT_SCC_DMA_I)); 1145 1146 /* RTC */ 1147 d = DEVICE(&s->rtc); 1148 if (!sysbus_realize(SYS_BUS_DEVICE(d), errp)) { 1149 return; 1150 } 1151 /* Data from NeXTPC to RTC */ 1152 qdev_connect_gpio_out_named(dev, "rtc-data-out", 0, 1153 qdev_get_gpio_in_named(d, "rtc-data-in", 0)); 1154 /* Data from RTC to NeXTPC */ 1155 qdev_connect_gpio_out_named(d, "rtc-data-out", 0, 1156 qdev_get_gpio_in_named(dev, 1157 "rtc-data-in", 0)); 1158 qdev_connect_gpio_out_named(dev, "rtc-cmd-reset", 0, 1159 qdev_get_gpio_in_named(d, "rtc-cmd-reset", 0)); 1160 qdev_connect_gpio_out_named(d, "rtc-power-out", 0, 1161 qdev_get_gpio_in(dev, NEXT_PWR_I)); 1162 } 1163 1164 static void next_pc_init(Object *obj) 1165 { 1166 NeXTPC *s = NEXT_PC(obj); 1167 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1168 1169 qdev_init_gpio_in(DEVICE(obj), next_irq, NEXT_NUM_IRQS); 1170 1171 memory_region_init_io(&s->mmiomem, OBJECT(s), &next_mmio_ops, s, 1172 "next.mmio", 0x9000); 1173 sysbus_init_mmio(sbd, &s->mmiomem); 1174 1175 memory_region_init_io(&s->dummyen_mem, OBJECT(s), &next_dummy_en_ops, s, 1176 "next.en", 0x20); 1177 sysbus_init_mmio(sbd, &s->dummyen_mem); 1178 1179 object_initialize_child(obj, "next-scsi", &s->next_scsi, TYPE_NEXT_SCSI); 1180 sysbus_init_mmio(sbd, 1181 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->next_scsi), 0)); 1182 1183 memory_region_init_io(&s->floppy_mem, OBJECT(s), &next_floppy_ops, s, 1184 "next.floppy", 4); 1185 sysbus_init_mmio(sbd, &s->floppy_mem); 1186 1187 object_initialize_child(obj, "escc", &s->escc, TYPE_ESCC); 1188 sysbus_init_mmio(sbd, 1189 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->escc), 0)); 1190 1191 memory_region_init_io(&s->timer_mem, OBJECT(s), &next_timer_ops, s, 1192 "next.timer", 4); 1193 sysbus_init_mmio(sbd, &s->timer_mem); 1194 1195 object_initialize_child(obj, "rtc", &s->rtc, TYPE_NEXT_RTC); 1196 1197 qdev_init_gpio_in_named(DEVICE(obj), next_pc_rtc_data_in_irq, 1198 "rtc-data-in", 1); 1199 qdev_init_gpio_out_named(DEVICE(obj), &s->rtc_data_irq, 1200 "rtc-data-out", 1); 1201 qdev_init_gpio_out_named(DEVICE(obj), &s->rtc_cmd_reset_irq, 1202 "rtc-cmd-reset", 1); 1203 } 1204 1205 /* 1206 * If the m68k CPU implemented its inbound irq lines as GPIO lines 1207 * rather than via the m68k_set_irq_level() function we would not need 1208 * this cpu link property and could instead provide outbound IRQ lines 1209 * that the board could wire up to the CPU. 1210 */ 1211 static const Property next_pc_properties[] = { 1212 DEFINE_PROP_LINK("cpu", NeXTPC, cpu, TYPE_M68K_CPU, M68kCPU *), 1213 }; 1214 1215 static const VMStateDescription next_pc_vmstate = { 1216 .name = "next-pc", 1217 .version_id = 4, 1218 .minimum_version_id = 4, 1219 .fields = (const VMStateField[]) { 1220 VMSTATE_UINT32(scr1, NeXTPC), 1221 VMSTATE_UINT32(scr2, NeXTPC), 1222 VMSTATE_UINT32(old_scr2, NeXTPC), 1223 VMSTATE_UINT32(int_mask, NeXTPC), 1224 VMSTATE_UINT32(int_status, NeXTPC), 1225 VMSTATE_UINT32(led, NeXTPC), 1226 VMSTATE_END_OF_LIST() 1227 }, 1228 }; 1229 1230 static void next_pc_class_init(ObjectClass *klass, void *data) 1231 { 1232 DeviceClass *dc = DEVICE_CLASS(klass); 1233 ResettableClass *rc = RESETTABLE_CLASS(klass); 1234 1235 dc->desc = "NeXT Peripheral Controller"; 1236 dc->realize = next_pc_realize; 1237 device_class_set_props(dc, next_pc_properties); 1238 dc->vmsd = &next_pc_vmstate; 1239 rc->phases.hold = next_pc_reset_hold; 1240 } 1241 1242 static const TypeInfo next_pc_info = { 1243 .name = TYPE_NEXT_PC, 1244 .parent = TYPE_SYS_BUS_DEVICE, 1245 .instance_init = next_pc_init, 1246 .instance_size = sizeof(NeXTPC), 1247 .class_init = next_pc_class_init, 1248 }; 1249 1250 static void next_cube_init(MachineState *machine) 1251 { 1252 NeXTState *m = NEXT_MACHINE(machine); 1253 M68kCPU *cpu; 1254 CPUM68KState *env; 1255 MemoryRegion *sysmem = get_system_memory(); 1256 const char *bios_name = machine->firmware ?: ROM_FILE; 1257 DeviceState *pcdev; 1258 1259 /* Initialize the cpu core */ 1260 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 1261 if (!cpu) { 1262 error_report("Unable to find m68k CPU definition"); 1263 exit(1); 1264 } 1265 env = &cpu->env; 1266 1267 /* Initialize CPU registers. */ 1268 env->vbr = 0; 1269 env->sr = 0x2700; 1270 1271 /* Peripheral Controller */ 1272 pcdev = qdev_new(TYPE_NEXT_PC); 1273 object_property_set_link(OBJECT(pcdev), "cpu", OBJECT(cpu), &error_abort); 1274 sysbus_realize_and_unref(SYS_BUS_DEVICE(pcdev), &error_fatal); 1275 1276 /* 64MB RAM starting at 0x04000000 */ 1277 memory_region_add_subregion(sysmem, 0x04000000, machine->ram); 1278 1279 /* Framebuffer */ 1280 sysbus_create_simple(TYPE_NEXTFB, 0x0B000000, NULL); 1281 1282 /* MMIO */ 1283 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02005000); 1284 1285 /* BMAP IO - acts as a catch-all for now */ 1286 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02100000); 1287 1288 /* en network (dummy) */ 1289 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02106000); 1290 1291 /* unknown: Brightness control register? */ 1292 empty_slot_init("next.unknown.0", 0x02110000, 0x10); 1293 /* unknown: Magneto-Optical drive controller? */ 1294 empty_slot_init("next.unknown.1", 0x02112000, 0x10); 1295 1296 /* SCSI */ 1297 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 2, 0x02114000); 1298 /* Floppy */ 1299 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 3, 0x02114108); 1300 /* ESCC */ 1301 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 4, 0x02118000); 1302 1303 /* unknown: Serial clock configuration register? */ 1304 empty_slot_init("next.unknown.2", 0x02118004, 0x10); 1305 1306 /* Timer */ 1307 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 5, 0x0211a000); 1308 1309 /* BMAP memory */ 1310 memory_region_init_ram_flags_nomigrate(&m->bmapm1, NULL, "next.bmapmem", 1311 64, RAM_SHARED, &error_fatal); 1312 memory_region_add_subregion(sysmem, 0x020c0000, &m->bmapm1); 1313 /* The Rev_2.5_v66.bin firmware accesses it at 0x820c0020, too */ 1314 memory_region_init_alias(&m->bmapm2, NULL, "next.bmapmem2", &m->bmapm1, 1315 0x0, 64); 1316 memory_region_add_subregion(sysmem, 0x820c0000, &m->bmapm2); 1317 1318 /* KBD */ 1319 sysbus_create_simple(TYPE_NEXTKBD, 0x0200e000, NULL); 1320 1321 /* Load ROM here */ 1322 memory_region_init_rom(&m->rom, NULL, "next.rom", 0x20000, &error_fatal); 1323 memory_region_add_subregion(sysmem, 0x01000000, &m->rom); 1324 memory_region_init_alias(&m->rom2, NULL, "next.rom2", &m->rom, 0x0, 1325 0x20000); 1326 memory_region_add_subregion(sysmem, 0x0, &m->rom2); 1327 if (load_image_targphys(bios_name, 0x01000000, 0x20000) < 8) { 1328 if (!qtest_enabled()) { 1329 error_report("Failed to load firmware '%s'.", bios_name); 1330 } 1331 } else { 1332 uint8_t *ptr; 1333 /* Initial PC is always at offset 4 in firmware binaries */ 1334 ptr = rom_ptr(0x01000004, 4); 1335 g_assert(ptr != NULL); 1336 env->pc = ldl_be_p(ptr); 1337 if (env->pc >= 0x01020000) { 1338 error_report("'%s' does not seem to be a valid firmware image.", 1339 bios_name); 1340 exit(1); 1341 } 1342 } 1343 1344 /* DMA */ 1345 memory_region_init_io(&m->dmamem, NULL, &next_dma_ops, machine, 1346 "next.dma", 0x5000); 1347 memory_region_add_subregion(sysmem, 0x02000000, &m->dmamem); 1348 } 1349 1350 static void next_machine_class_init(ObjectClass *oc, void *data) 1351 { 1352 MachineClass *mc = MACHINE_CLASS(oc); 1353 1354 mc->desc = "NeXT Cube"; 1355 mc->init = next_cube_init; 1356 mc->block_default_type = IF_SCSI; 1357 mc->default_ram_size = RAM_SIZE; 1358 mc->default_ram_id = "next.ram"; 1359 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); 1360 mc->no_cdrom = true; 1361 } 1362 1363 static const TypeInfo next_typeinfo = { 1364 .name = TYPE_NEXT_MACHINE, 1365 .parent = TYPE_MACHINE, 1366 .class_init = next_machine_class_init, 1367 .instance_size = sizeof(NeXTState), 1368 }; 1369 1370 static void next_register_type(void) 1371 { 1372 type_register_static(&next_typeinfo); 1373 type_register_static(&next_pc_info); 1374 type_register_static(&next_scsi_info); 1375 type_register_static(&next_rtc_info); 1376 } 1377 1378 type_init(next_register_type) 1379