1 /* 2 * NeXT Cube System Driver 3 * 4 * Copyright (c) 2011 Bryce Lanham 5 * Copyright (c) 2024 Mark Cave-Ayland 6 * 7 * This code is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published 9 * by the Free Software Foundation; either version 2 of the License, 10 * or (at your option) any later version. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "exec/hwaddr.h" 15 #include "system/system.h" 16 #include "system/qtest.h" 17 #include "hw/irq.h" 18 #include "hw/m68k/next-cube.h" 19 #include "hw/boards.h" 20 #include "hw/loader.h" 21 #include "hw/scsi/esp.h" 22 #include "hw/sysbus.h" 23 #include "qom/object.h" 24 #include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */ 25 #include "hw/block/fdc.h" 26 #include "hw/misc/empty_slot.h" 27 #include "hw/qdev-properties.h" 28 #include "qapi/error.h" 29 #include "qemu/error-report.h" 30 #include "ui/console.h" 31 #include "target/m68k/cpu.h" 32 #include "migration/vmstate.h" 33 34 /* #define DEBUG_NEXT */ 35 #ifdef DEBUG_NEXT 36 #define DPRINTF(fmt, ...) \ 37 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0) 38 #else 39 #define DPRINTF(fmt, ...) do { } while (0) 40 #endif 41 42 #define ENTRY 0x0100001e 43 #define RAM_SIZE 0x4000000 44 #define ROM_FILE "Rev_2.5_v66.bin" 45 46 47 #define TYPE_NEXT_RTC "next-rtc" 48 OBJECT_DECLARE_SIMPLE_TYPE(NeXTRTC, NEXT_RTC) 49 50 struct NeXTRTC { 51 SysBusDevice parent_obj; 52 53 int8_t phase; 54 uint8_t ram[32]; 55 uint8_t command; 56 uint8_t value; 57 uint8_t status; 58 uint8_t control; 59 uint8_t retval; 60 61 qemu_irq data_out_irq; 62 qemu_irq power_irq; 63 }; 64 65 #define TYPE_NEXT_SCSI "next-scsi" 66 OBJECT_DECLARE_SIMPLE_TYPE(NeXTSCSI, NEXT_SCSI) 67 68 /* NeXT SCSI Controller */ 69 struct NeXTSCSI { 70 SysBusDevice parent_obj; 71 72 MemoryRegion scsi_mem; 73 74 SysBusESPState sysbus_esp; 75 76 MemoryRegion scsi_csr_mem; 77 uint8_t scsi_csr_1; 78 uint8_t scsi_csr_2; 79 }; 80 81 #define TYPE_NEXT_PC "next-pc" 82 OBJECT_DECLARE_SIMPLE_TYPE(NeXTPC, NEXT_PC) 83 84 /* NeXT Peripheral Controller */ 85 struct NeXTPC { 86 SysBusDevice parent_obj; 87 88 M68kCPU *cpu; 89 90 MemoryRegion floppy_mem; 91 MemoryRegion timer_mem; 92 MemoryRegion dummyen_mem; 93 MemoryRegion mmiomem; 94 MemoryRegion scrmem; 95 96 uint32_t scr1; 97 uint32_t scr2; 98 uint32_t old_scr2; 99 uint32_t int_mask; 100 uint32_t int_status; 101 uint32_t led; 102 103 NeXTSCSI next_scsi; 104 105 qemu_irq scsi_reset; 106 qemu_irq scsi_dma; 107 108 ESCCState escc; 109 110 NeXTRTC rtc; 111 qemu_irq rtc_data_irq; 112 qemu_irq rtc_cmd_reset_irq; 113 }; 114 115 typedef struct next_dma { 116 uint32_t csr; 117 118 uint32_t saved_next; 119 uint32_t saved_limit; 120 uint32_t saved_start; 121 uint32_t saved_stop; 122 123 uint32_t next; 124 uint32_t limit; 125 uint32_t start; 126 uint32_t stop; 127 128 uint32_t next_initbuf; 129 uint32_t size; 130 } next_dma; 131 132 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube") 133 OBJECT_DECLARE_SIMPLE_TYPE(NeXTState, NEXT_MACHINE) 134 135 struct NeXTState { 136 MachineState parent; 137 138 MemoryRegion rom; 139 MemoryRegion rom2; 140 MemoryRegion dmamem; 141 MemoryRegion bmapm1; 142 MemoryRegion bmapm2; 143 144 next_dma dma[10]; 145 }; 146 147 /* Thanks to NeXT forums for this */ 148 /* 149 static const uint8_t rtc_ram3[32] = { 150 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 151 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00, 152 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00, 153 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13 154 }; 155 */ 156 static const uint8_t rtc_ram2[32] = { 157 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00, 158 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00, 159 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 160 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e, 161 }; 162 163 #define SCR2_RTCLK 0x2 164 #define SCR2_RTDATA 0x4 165 #define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10)) 166 167 static void next_scr2_led_update(NeXTPC *s) 168 { 169 if (s->scr2 & 0x1) { 170 DPRINTF("fault!\n"); 171 s->led++; 172 if (s->led == 10) { 173 DPRINTF("LED flashing, possible fault!\n"); 174 s->led = 0; 175 } 176 } 177 } 178 179 static void next_scr2_rtc_update(NeXTPC *s) 180 { 181 uint8_t old_scr2_rtc, scr2_rtc; 182 183 old_scr2_rtc = extract32(s->old_scr2, 8, 8); 184 scr2_rtc = extract32(s->scr2, 8, 8); 185 186 if (scr2_rtc & 0x1) { 187 /* DPRINTF("RTC %x phase %i\n", scr2_2, rtc->phase); */ 188 /* If we are in going down clock... do something */ 189 if (((old_scr2_rtc & SCR2_RTCLK) != (scr2_rtc & SCR2_RTCLK)) && 190 ((scr2_rtc & SCR2_RTCLK) == 0)) { 191 if (scr2_rtc & SCR2_RTDATA) { 192 qemu_irq_raise(s->rtc_data_irq); 193 } else { 194 qemu_irq_lower(s->rtc_data_irq); 195 } 196 } 197 } else { 198 /* else end or abort */ 199 qemu_irq_raise(s->rtc_cmd_reset_irq); 200 } 201 } 202 203 static uint64_t next_mmio_read(void *opaque, hwaddr addr, unsigned size) 204 { 205 NeXTPC *s = NEXT_PC(opaque); 206 uint64_t val; 207 208 switch (addr) { 209 case 0x2000: /* 0x2007000 */ 210 /* DPRINTF("Read INT status: %x\n", s->int_status); */ 211 val = s->int_status; 212 break; 213 214 case 0x2800: /* 0x2007800 */ 215 DPRINTF("MMIO Read INT mask: %x\n", s->int_mask); 216 val = s->int_mask; 217 break; 218 219 case 0x7000 ... 0x7003: /* 0x200c000 */ 220 val = extract32(s->scr1, (4 - (addr - 0x7000) - size) << 3, 221 size << 3); 222 break; 223 224 case 0x8000 ... 0x8003: /* 0x200d000 */ 225 val = extract32(s->scr2, (4 - (addr - 0x8000) - size) << 3, 226 size << 3); 227 break; 228 229 default: 230 val = 0; 231 DPRINTF("MMIO Read @ 0x%"HWADDR_PRIx" size %d\n", addr, size); 232 break; 233 } 234 235 return val; 236 } 237 238 static void next_mmio_write(void *opaque, hwaddr addr, uint64_t val, 239 unsigned size) 240 { 241 NeXTPC *s = NEXT_PC(opaque); 242 243 switch (addr) { 244 case 0x2000: /* 0x2007000 */ 245 DPRINTF("INT Status old: %x new: %x\n", s->int_status, 246 (unsigned int)val); 247 s->int_status = val; 248 break; 249 250 case 0x2800: /* 0x2007800 */ 251 DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, (unsigned int)val); 252 s->int_mask = val; 253 break; 254 255 case 0x7000 ... 0x7003: /* 0x200c000 */ 256 DPRINTF("SCR1 Write: %x\n", (unsigned int)val); 257 s->scr1 = deposit32(s->scr1, (4 - (addr - 0x7000) - size) << 3, 258 size << 3, val); 259 break; 260 261 case 0x8000 ... 0x8003: /* 0x200d000 */ 262 s->scr2 = deposit32(s->scr2, (4 - (addr - 0x8000) - size) << 3, 263 size << 3, val); 264 next_scr2_led_update(s); 265 next_scr2_rtc_update(s); 266 s->old_scr2 = s->scr2; 267 break; 268 269 default: 270 DPRINTF("MMIO Write @ 0x%"HWADDR_PRIx " with 0x%x size %u\n", addr, 271 (unsigned int)val, size); 272 } 273 } 274 275 static const MemoryRegionOps next_mmio_ops = { 276 .read = next_mmio_read, 277 .write = next_mmio_write, 278 .valid.min_access_size = 1, 279 .valid.max_access_size = 4, 280 .endianness = DEVICE_BIG_ENDIAN, 281 }; 282 283 #define SCSICSR_ENABLE 0x01 284 #define SCSICSR_RESET 0x02 /* reset scsi dma */ 285 #define SCSICSR_FIFOFL 0x04 286 #define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */ 287 #define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */ 288 #define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */ 289 290 #define NEXTDMA_SCSI(x) (0x10 + x) 291 #define NEXTDMA_FD(x) (0x10 + x) 292 #define NEXTDMA_ENTX(x) (0x110 + x) 293 #define NEXTDMA_ENRX(x) (0x150 + x) 294 #define NEXTDMA_CSR 0x0 295 #define NEXTDMA_NEXT 0x4000 296 #define NEXTDMA_LIMIT 0x4004 297 #define NEXTDMA_START 0x4008 298 #define NEXTDMA_STOP 0x400c 299 #define NEXTDMA_NEXT_INIT 0x4200 300 #define NEXTDMA_SIZE 0x4204 301 302 static void next_dma_write(void *opaque, hwaddr addr, uint64_t val, 303 unsigned int size) 304 { 305 NeXTState *next_state = NEXT_MACHINE(opaque); 306 307 switch (addr) { 308 case NEXTDMA_ENRX(NEXTDMA_CSR): 309 if (val & DMA_DEV2M) { 310 next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M; 311 } 312 313 if (val & DMA_SETENABLE) { 314 /* DPRINTF("SCSI DMA ENABLE\n"); */ 315 next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE; 316 } 317 if (val & DMA_SETSUPDATE) { 318 next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE; 319 } 320 if (val & DMA_CLRCOMPLETE) { 321 next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE; 322 } 323 324 if (val & DMA_RESET) { 325 next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 326 DMA_ENABLE | DMA_DEV2M); 327 } 328 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 329 break; 330 331 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 332 next_state->dma[NEXTDMA_ENRX].next_initbuf = val; 333 break; 334 335 case NEXTDMA_ENRX(NEXTDMA_NEXT): 336 next_state->dma[NEXTDMA_ENRX].next = val; 337 break; 338 339 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 340 next_state->dma[NEXTDMA_ENRX].limit = val; 341 break; 342 343 case NEXTDMA_SCSI(NEXTDMA_CSR): 344 if (val & DMA_DEV2M) { 345 next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M; 346 } 347 if (val & DMA_SETENABLE) { 348 /* DPRINTF("SCSI DMA ENABLE\n"); */ 349 next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE; 350 } 351 if (val & DMA_SETSUPDATE) { 352 next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE; 353 } 354 if (val & DMA_CLRCOMPLETE) { 355 next_state->dma[NEXTDMA_SCSI].csr &= ~DMA_COMPLETE; 356 } 357 358 if (val & DMA_RESET) { 359 next_state->dma[NEXTDMA_SCSI].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 360 DMA_ENABLE | DMA_DEV2M); 361 /* DPRINTF("SCSI DMA RESET\n"); */ 362 } 363 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 364 break; 365 366 case NEXTDMA_SCSI(NEXTDMA_NEXT): 367 next_state->dma[NEXTDMA_SCSI].next = val; 368 break; 369 370 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 371 next_state->dma[NEXTDMA_SCSI].limit = val; 372 break; 373 374 case NEXTDMA_SCSI(NEXTDMA_START): 375 next_state->dma[NEXTDMA_SCSI].start = val; 376 break; 377 378 case NEXTDMA_SCSI(NEXTDMA_STOP): 379 next_state->dma[NEXTDMA_SCSI].stop = val; 380 break; 381 382 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 383 next_state->dma[NEXTDMA_SCSI].next_initbuf = val; 384 break; 385 386 default: 387 DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)val); 388 } 389 } 390 391 static uint64_t next_dma_read(void *opaque, hwaddr addr, unsigned int size) 392 { 393 NeXTState *next_state = NEXT_MACHINE(opaque); 394 uint64_t val; 395 396 switch (addr) { 397 case NEXTDMA_SCSI(NEXTDMA_CSR): 398 DPRINTF("SCSI DMA CSR READ\n"); 399 val = next_state->dma[NEXTDMA_SCSI].csr; 400 break; 401 402 case NEXTDMA_ENRX(NEXTDMA_CSR): 403 val = next_state->dma[NEXTDMA_ENRX].csr; 404 break; 405 406 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 407 val = next_state->dma[NEXTDMA_ENRX].next_initbuf; 408 break; 409 410 case NEXTDMA_ENRX(NEXTDMA_NEXT): 411 val = next_state->dma[NEXTDMA_ENRX].next; 412 break; 413 414 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 415 val = next_state->dma[NEXTDMA_ENRX].limit; 416 break; 417 418 case NEXTDMA_SCSI(NEXTDMA_NEXT): 419 val = next_state->dma[NEXTDMA_SCSI].next; 420 break; 421 422 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 423 val = next_state->dma[NEXTDMA_SCSI].next_initbuf; 424 break; 425 426 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 427 val = next_state->dma[NEXTDMA_SCSI].limit; 428 break; 429 430 case NEXTDMA_SCSI(NEXTDMA_START): 431 val = next_state->dma[NEXTDMA_SCSI].start; 432 break; 433 434 case NEXTDMA_SCSI(NEXTDMA_STOP): 435 val = next_state->dma[NEXTDMA_SCSI].stop; 436 break; 437 438 default: 439 DPRINTF("DMA read @ %x\n", (unsigned int)addr); 440 val = 0; 441 } 442 443 /* 444 * once the csr's are done, subtract 0x3FEC from the addr, and that will 445 * normalize the upper registers 446 */ 447 448 return val; 449 } 450 451 static const MemoryRegionOps next_dma_ops = { 452 .read = next_dma_read, 453 .write = next_dma_write, 454 .impl.min_access_size = 4, 455 .valid.min_access_size = 4, 456 .valid.max_access_size = 4, 457 .endianness = DEVICE_BIG_ENDIAN, 458 }; 459 460 static void next_irq(void *opaque, int number, int level) 461 { 462 NeXTPC *s = NEXT_PC(opaque); 463 M68kCPU *cpu = s->cpu; 464 int shift = 0; 465 466 /* first switch sets interrupt status */ 467 /* DPRINTF("IRQ %i\n",number); */ 468 switch (number) { 469 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 470 case NEXT_FD_I: 471 shift = 7; 472 break; 473 case NEXT_KBD_I: 474 shift = 3; 475 break; 476 case NEXT_PWR_I: 477 shift = 2; 478 break; 479 case NEXT_ENRX_I: 480 shift = 9; 481 break; 482 case NEXT_ENTX_I: 483 shift = 10; 484 break; 485 case NEXT_SCSI_I: 486 shift = 12; 487 break; 488 case NEXT_CLK_I: 489 shift = 5; 490 break; 491 492 /* level 5 - scc (serial) */ 493 case NEXT_SCC_I: 494 shift = 17; 495 break; 496 497 /* level 6 - audio etherrx/tx dma */ 498 case NEXT_ENTX_DMA_I: 499 shift = 28; 500 break; 501 case NEXT_ENRX_DMA_I: 502 shift = 27; 503 break; 504 case NEXT_SCSI_DMA_I: 505 shift = 26; 506 break; 507 case NEXT_SND_I: 508 shift = 23; 509 break; 510 case NEXT_SCC_DMA_I: 511 shift = 21; 512 break; 513 514 } 515 /* 516 * this HAS to be wrong, the interrupt handlers in mach and together 517 * int_status and int_mask and return if there is a hit 518 */ 519 if (s->int_mask & (1 << shift)) { 520 DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc); 521 /* return; */ 522 } 523 524 /* second switch triggers the correct interrupt */ 525 if (level) { 526 s->int_status |= 1 << shift; 527 528 switch (number) { 529 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 530 case NEXT_FD_I: 531 case NEXT_KBD_I: 532 case NEXT_PWR_I: 533 case NEXT_ENRX_I: 534 case NEXT_ENTX_I: 535 case NEXT_SCSI_I: 536 case NEXT_CLK_I: 537 m68k_set_irq_level(cpu, 3, 27); 538 break; 539 540 /* level 5 - scc (serial) */ 541 case NEXT_SCC_I: 542 m68k_set_irq_level(cpu, 5, 29); 543 break; 544 545 /* level 6 - audio etherrx/tx dma */ 546 case NEXT_ENTX_DMA_I: 547 case NEXT_ENRX_DMA_I: 548 case NEXT_SCSI_DMA_I: 549 case NEXT_SND_I: 550 case NEXT_SCC_DMA_I: 551 m68k_set_irq_level(cpu, 6, 30); 552 break; 553 } 554 } else { 555 s->int_status &= ~(1 << shift); 556 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); 557 } 558 } 559 560 static void nextdma_write(void *opaque, uint8_t *buf, int size, int type) 561 { 562 uint32_t base_addr; 563 int irq = 0; 564 uint8_t align = 16; 565 NeXTState *next_state = NEXT_MACHINE(qdev_get_machine()); 566 567 if (type == NEXTDMA_ENRX || type == NEXTDMA_ENTX) { 568 align = 32; 569 } 570 /* Most DMA is supposedly 16 byte aligned */ 571 if ((size % align) != 0) { 572 size -= size % align; 573 size += align; 574 } 575 576 /* 577 * prom sets the dma start using initbuf while the bootloader uses next 578 * so we check to see if initbuf is 0 579 */ 580 if (next_state->dma[type].next_initbuf == 0) { 581 base_addr = next_state->dma[type].next; 582 } else { 583 base_addr = next_state->dma[type].next_initbuf; 584 } 585 586 cpu_physical_memory_write(base_addr, buf, size); 587 588 next_state->dma[type].next_initbuf = 0; 589 590 /* saved limit is checked to calculate packet size by both, rom and netbsd */ 591 next_state->dma[type].saved_limit = (next_state->dma[type].next + size); 592 next_state->dma[type].saved_next = (next_state->dma[type].next); 593 594 /* 595 * 32 bytes under savedbase seems to be some kind of register 596 * of which the purpose is unknown as of yet 597 */ 598 /* stl_phys(s->rx_dma.base-32,0xFFFFFFFF); */ 599 600 if (!(next_state->dma[type].csr & DMA_SUPDATE)) { 601 next_state->dma[type].next = next_state->dma[type].start; 602 next_state->dma[type].limit = next_state->dma[type].stop; 603 } 604 605 /* Set dma registers and raise an irq */ 606 next_state->dma[type].csr |= DMA_COMPLETE; /* DON'T CHANGE THIS! */ 607 608 switch (type) { 609 case NEXTDMA_SCSI: 610 irq = NEXT_SCSI_DMA_I; 611 break; 612 } 613 614 next_irq(opaque, irq, 1); 615 next_irq(opaque, irq, 0); 616 } 617 618 static void nextscsi_read(void *opaque, uint8_t *buf, int len) 619 { 620 DPRINTF("SCSI READ: %x\n", len); 621 abort(); 622 } 623 624 static void nextscsi_write(void *opaque, uint8_t *buf, int size) 625 { 626 DPRINTF("SCSI WRITE: %i\n", size); 627 nextdma_write(opaque, buf, size, NEXTDMA_SCSI); 628 } 629 630 static void next_scsi_csr_write(void *opaque, hwaddr addr, uint64_t val, 631 unsigned size) 632 { 633 NeXTSCSI *s = NEXT_SCSI(opaque); 634 NeXTPC *pc = NEXT_PC(container_of(s, NeXTPC, next_scsi)); 635 636 switch (addr) { 637 case 0: 638 if (val & SCSICSR_FIFOFL) { 639 DPRINTF("SCSICSR FIFO Flush\n"); 640 /* will have to add another irq to the esp if this is needed */ 641 /* esp_puflush_fifo(esp_g); */ 642 } 643 644 if (val & SCSICSR_ENABLE) { 645 DPRINTF("SCSICSR Enable\n"); 646 /* 647 * qemu_irq_raise(s->scsi_dma); 648 * s->scsi_csr_1 = 0xc0; 649 * s->scsi_csr_1 |= 0x1; 650 * qemu_irq_pulse(s->scsi_dma); 651 */ 652 } 653 /* 654 * else 655 * s->scsi_csr_1 &= ~SCSICSR_ENABLE; 656 */ 657 658 if (val & SCSICSR_RESET) { 659 DPRINTF("SCSICSR Reset\n"); 660 /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */ 661 qemu_irq_raise(pc->scsi_reset); 662 s->scsi_csr_1 &= ~(SCSICSR_INTMASK | 0x80 | 0x1); 663 qemu_irq_lower(pc->scsi_reset); 664 } 665 if (val & SCSICSR_DMADIR) { 666 DPRINTF("SCSICSR DMAdir\n"); 667 } 668 if (val & SCSICSR_CPUDMA) { 669 DPRINTF("SCSICSR CPUDMA\n"); 670 /* qemu_irq_raise(s->scsi_dma); */ 671 pc->int_status |= 0x4000000; 672 } else { 673 /* fprintf(stderr,"SCSICSR CPUDMA disabled\n"); */ 674 pc->int_status &= ~(0x4000000); 675 /* qemu_irq_lower(s->scsi_dma); */ 676 } 677 if (val & SCSICSR_INTMASK) { 678 DPRINTF("SCSICSR INTMASK\n"); 679 /* 680 * int_mask &= ~0x1000; 681 * s->scsi_csr_1 |= val; 682 * s->scsi_csr_1 &= ~SCSICSR_INTMASK; 683 * if (s->scsi_queued) { 684 * s->scsi_queued = 0; 685 * next_irq(s, NEXT_SCSI_I, level); 686 * } 687 */ 688 } else { 689 /* int_mask |= 0x1000; */ 690 } 691 if (val & 0x80) { 692 /* int_mask |= 0x1000; */ 693 /* s->scsi_csr_1 |= 0x80; */ 694 } 695 DPRINTF("SCSICSR1 Write: %"PRIx64 "\n", val); 696 s->scsi_csr_1 = val; 697 break; 698 699 case 1: 700 DPRINTF("SCSICSR2 Write: %"PRIx64 "\n", val); 701 s->scsi_csr_2 = val; 702 break; 703 704 default: 705 g_assert_not_reached(); 706 } 707 } 708 709 static uint64_t next_scsi_csr_read(void *opaque, hwaddr addr, unsigned size) 710 { 711 NeXTSCSI *s = NEXT_SCSI(opaque); 712 uint64_t val; 713 714 switch (addr) { 715 case 0: 716 DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1); 717 val = s->scsi_csr_1; 718 break; 719 720 case 1: 721 DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2); 722 val = s->scsi_csr_2; 723 break; 724 725 default: 726 g_assert_not_reached(); 727 } 728 729 return val; 730 } 731 732 static const MemoryRegionOps next_scsi_csr_ops = { 733 .read = next_scsi_csr_read, 734 .write = next_scsi_csr_write, 735 .valid.min_access_size = 1, 736 .valid.max_access_size = 1, 737 .endianness = DEVICE_BIG_ENDIAN, 738 }; 739 740 static void next_scsi_init(Object *obj) 741 { 742 NeXTSCSI *s = NEXT_SCSI(obj); 743 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 744 745 object_initialize_child(obj, "esp", &s->sysbus_esp, TYPE_SYSBUS_ESP); 746 747 memory_region_init_io(&s->scsi_csr_mem, obj, &next_scsi_csr_ops, 748 s, "csrs", 2); 749 750 memory_region_init(&s->scsi_mem, obj, "next.scsi", 0x40); 751 sysbus_init_mmio(sbd, &s->scsi_mem); 752 } 753 754 static void next_scsi_realize(DeviceState *dev, Error **errp) 755 { 756 NeXTSCSI *s = NEXT_SCSI(dev); 757 SysBusESPState *sysbus_esp; 758 SysBusDevice *sbd; 759 ESPState *esp; 760 NeXTPC *pcdev; 761 762 pcdev = NEXT_PC(container_of(s, NeXTPC, next_scsi)); 763 764 /* ESP */ 765 sysbus_esp = SYSBUS_ESP(&s->sysbus_esp); 766 esp = &sysbus_esp->esp; 767 esp->dma_memory_read = nextscsi_read; 768 esp->dma_memory_write = nextscsi_write; 769 esp->dma_opaque = pcdev; 770 sysbus_esp->it_shift = 0; 771 esp->dma_enabled = 1; 772 sbd = SYS_BUS_DEVICE(sysbus_esp); 773 if (!sysbus_realize(sbd, errp)) { 774 return; 775 } 776 memory_region_add_subregion(&s->scsi_mem, 0x0, 777 sysbus_mmio_get_region(sbd, 0)); 778 779 /* SCSI CSRs */ 780 memory_region_add_subregion(&s->scsi_mem, 0x20, &s->scsi_csr_mem); 781 782 scsi_bus_legacy_handle_cmdline(&s->sysbus_esp.esp.bus); 783 } 784 785 static const VMStateDescription next_scsi_vmstate = { 786 .name = "next-scsi", 787 .version_id = 0, 788 .minimum_version_id = 0, 789 .fields = (const VMStateField[]) { 790 VMSTATE_UINT8(scsi_csr_1, NeXTSCSI), 791 VMSTATE_UINT8(scsi_csr_2, NeXTSCSI), 792 VMSTATE_END_OF_LIST() 793 }, 794 }; 795 796 static void next_scsi_class_init(ObjectClass *klass, void *data) 797 { 798 DeviceClass *dc = DEVICE_CLASS(klass); 799 800 dc->desc = "NeXT SCSI Controller"; 801 dc->realize = next_scsi_realize; 802 dc->vmsd = &next_scsi_vmstate; 803 } 804 805 static const TypeInfo next_scsi_info = { 806 .name = TYPE_NEXT_SCSI, 807 .parent = TYPE_SYS_BUS_DEVICE, 808 .instance_init = next_scsi_init, 809 .instance_size = sizeof(NeXTSCSI), 810 .class_init = next_scsi_class_init, 811 }; 812 813 static void next_floppy_write(void *opaque, hwaddr addr, uint64_t val, 814 unsigned size) 815 { 816 switch (addr) { 817 case 0: 818 DPRINTF("FDCSR Write: %"PRIx64 "\n", val); 819 if (val == 0x0) { 820 /* qemu_irq_raise(s->fd_irq[0]); */ 821 } 822 break; 823 824 default: 825 g_assert_not_reached(); 826 } 827 } 828 829 static uint64_t next_floppy_read(void *opaque, hwaddr addr, unsigned size) 830 { 831 uint64_t val; 832 833 switch (addr) { 834 case 0: 835 DPRINTF("FD read @ %x\n", (unsigned int)addr); 836 val = 0x40 | 0x04 | 0x2 | 0x1; 837 break; 838 839 default: 840 g_assert_not_reached(); 841 } 842 843 return val; 844 } 845 846 static const MemoryRegionOps next_floppy_ops = { 847 .read = next_floppy_read, 848 .write = next_floppy_write, 849 .valid.min_access_size = 1, 850 .valid.max_access_size = 4, 851 .endianness = DEVICE_BIG_ENDIAN, 852 }; 853 854 static void next_timer_write(void *opaque, hwaddr addr, uint64_t val, 855 unsigned size) 856 { 857 switch (addr) { 858 case 0 ... 3: 859 /* Hardware timer latch - not implemented yet */ 860 break; 861 862 default: 863 g_assert_not_reached(); 864 } 865 } 866 867 static uint64_t next_timer_read(void *opaque, hwaddr addr, unsigned size) 868 { 869 uint64_t val; 870 871 switch (addr) { 872 case 0 ... 3: 873 /* 874 * These 4 registers are the hardware timer, not sure which register 875 * is the latch instead of data, but no problems so far. 876 * 877 * Hack: We need to have the LSB change consistently to make it work 878 */ 879 val = extract32(clock(), (4 - addr - size) << 3, 880 size << 3); 881 break; 882 883 default: 884 g_assert_not_reached(); 885 } 886 887 return val; 888 } 889 890 static const MemoryRegionOps next_timer_ops = { 891 .read = next_timer_read, 892 .write = next_timer_write, 893 .valid.min_access_size = 1, 894 .valid.max_access_size = 4, 895 .endianness = DEVICE_BIG_ENDIAN, 896 }; 897 898 static void next_dummy_en_write(void *opaque, hwaddr addr, uint64_t val, 899 unsigned size) 900 { 901 /* Do nothing */ 902 } 903 904 static uint64_t next_dummy_en_read(void *opaque, hwaddr addr, unsigned size) 905 { 906 uint64_t val; 907 908 switch (addr) { 909 case 0: 910 /* For now return dummy byte to allow the Ethernet test to timeout */ 911 val = 0xff; 912 break; 913 914 default: 915 val = 0; 916 } 917 918 return val; 919 } 920 921 static const MemoryRegionOps next_dummy_en_ops = { 922 .read = next_dummy_en_read, 923 .write = next_dummy_en_write, 924 .valid.min_access_size = 1, 925 .valid.max_access_size = 4, 926 .endianness = DEVICE_BIG_ENDIAN, 927 }; 928 929 static bool next_rtc_cmd_is_write(uint8_t cmd) 930 { 931 return (cmd >= 0x80 && cmd <= 0x9f) || 932 (cmd == 0xb1); 933 } 934 935 static void next_rtc_data_in_irq(void *opaque, int n, int level) 936 { 937 NeXTRTC *rtc = NEXT_RTC(opaque); 938 939 if (rtc->phase < 8) { 940 rtc->command = (rtc->command << 1) | level; 941 942 if (rtc->phase == 7 && !next_rtc_cmd_is_write(rtc->command)) { 943 if (rtc->command <= 0x1f) { 944 /* RAM registers */ 945 rtc->retval = rtc->ram[rtc->command]; 946 } 947 if ((rtc->command >= 0x20) && (rtc->command <= 0x2f)) { 948 /* RTC */ 949 time_t time_h = time(NULL); 950 struct tm *info = localtime(&time_h); 951 rtc->retval = 0; 952 953 switch (rtc->command) { 954 case 0x20: 955 rtc->retval = SCR2_TOBCD(info->tm_sec); 956 break; 957 case 0x21: 958 rtc->retval = SCR2_TOBCD(info->tm_min); 959 break; 960 case 0x22: 961 rtc->retval = SCR2_TOBCD(info->tm_hour); 962 break; 963 case 0x24: 964 rtc->retval = SCR2_TOBCD(info->tm_mday); 965 break; 966 case 0x25: 967 rtc->retval = SCR2_TOBCD((info->tm_mon + 1)); 968 break; 969 case 0x26: 970 rtc->retval = SCR2_TOBCD((info->tm_year - 100)); 971 break; 972 } 973 } 974 if (rtc->command == 0x30) { 975 /* read the status 0x30 */ 976 rtc->retval = rtc->status; 977 } 978 if (rtc->command == 0x31) { 979 /* read the control 0x31 */ 980 rtc->retval = rtc->control; 981 } 982 } 983 } 984 if (rtc->phase >= 8 && rtc->phase < 16) { 985 if (next_rtc_cmd_is_write(rtc->command)) { 986 /* Shift in value to write */ 987 rtc->value = (rtc->value << 1) | level; 988 } else { 989 /* Shift out value to read */ 990 if (rtc->retval & (0x80 >> (rtc->phase - 8))) { 991 qemu_irq_raise(rtc->data_out_irq); 992 } else { 993 qemu_irq_lower(rtc->data_out_irq); 994 } 995 } 996 } 997 998 rtc->phase++; 999 if (rtc->phase == 16 && next_rtc_cmd_is_write(rtc->command)) { 1000 if (rtc->command >= 0x80 && rtc->command <= 0x9f) { 1001 /* RAM registers */ 1002 rtc->ram[rtc->command - 0x80] = rtc->value; 1003 } 1004 if (rtc->command == 0xb1) { 1005 /* write to 0x30 register */ 1006 if (rtc->value & 0x04) { 1007 /* clear FTU */ 1008 rtc->status = rtc->status & (~0x18); 1009 qemu_irq_lower(rtc->power_irq); 1010 } 1011 } 1012 } 1013 } 1014 1015 static void next_rtc_cmd_reset_irq(void *opaque, int n, int level) 1016 { 1017 NeXTRTC *rtc = NEXT_RTC(opaque); 1018 1019 if (level) { 1020 rtc->phase = 0; 1021 rtc->command = 0; 1022 rtc->value = 0; 1023 } 1024 } 1025 1026 static void next_rtc_reset_hold(Object *obj, ResetType type) 1027 { 1028 NeXTRTC *rtc = NEXT_RTC(obj); 1029 1030 rtc->status = 0x90; 1031 1032 /* Load RTC RAM - TODO: provide possibility to load contents from file */ 1033 memcpy(rtc->ram, rtc_ram2, 32); 1034 } 1035 1036 static void next_rtc_init(Object *obj) 1037 { 1038 NeXTRTC *rtc = NEXT_RTC(obj); 1039 1040 qdev_init_gpio_in_named(DEVICE(obj), next_rtc_data_in_irq, 1041 "rtc-data-in", 1); 1042 qdev_init_gpio_out_named(DEVICE(obj), &rtc->data_out_irq, 1043 "rtc-data-out", 1); 1044 qdev_init_gpio_in_named(DEVICE(obj), next_rtc_cmd_reset_irq, 1045 "rtc-cmd-reset", 1); 1046 qdev_init_gpio_out_named(DEVICE(obj), &rtc->power_irq, 1047 "rtc-power-out", 1); 1048 } 1049 1050 static const VMStateDescription next_rtc_vmstate = { 1051 .name = "next-rtc", 1052 .version_id = 3, 1053 .minimum_version_id = 3, 1054 .fields = (const VMStateField[]) { 1055 VMSTATE_INT8(phase, NeXTRTC), 1056 VMSTATE_UINT8_ARRAY(ram, NeXTRTC, 32), 1057 VMSTATE_UINT8(command, NeXTRTC), 1058 VMSTATE_UINT8(value, NeXTRTC), 1059 VMSTATE_UINT8(status, NeXTRTC), 1060 VMSTATE_UINT8(control, NeXTRTC), 1061 VMSTATE_UINT8(retval, NeXTRTC), 1062 VMSTATE_END_OF_LIST() 1063 }, 1064 }; 1065 1066 static void next_rtc_class_init(ObjectClass *klass, void *data) 1067 { 1068 DeviceClass *dc = DEVICE_CLASS(klass); 1069 ResettableClass *rc = RESETTABLE_CLASS(klass); 1070 1071 dc->desc = "NeXT RTC"; 1072 dc->vmsd = &next_rtc_vmstate; 1073 rc->phases.hold = next_rtc_reset_hold; 1074 } 1075 1076 static const TypeInfo next_rtc_info = { 1077 .name = TYPE_NEXT_RTC, 1078 .parent = TYPE_SYS_BUS_DEVICE, 1079 .instance_init = next_rtc_init, 1080 .instance_size = sizeof(NeXTRTC), 1081 .class_init = next_rtc_class_init, 1082 }; 1083 1084 static void next_pc_rtc_data_in_irq(void *opaque, int n, int level) 1085 { 1086 NeXTPC *s = NEXT_PC(opaque); 1087 uint8_t scr2_2 = extract32(s->scr2, 8, 8); 1088 1089 if (level) { 1090 scr2_2 |= SCR2_RTDATA; 1091 } else { 1092 scr2_2 &= ~SCR2_RTDATA; 1093 } 1094 1095 s->scr2 = deposit32(s->scr2, 8, 8, scr2_2); 1096 } 1097 1098 static void next_pc_reset_hold(Object *obj, ResetType type) 1099 { 1100 NeXTPC *s = NEXT_PC(obj); 1101 1102 /* Set internal registers to initial values */ 1103 /* 0x0000XX00 << vital bits */ 1104 s->scr1 = 0x00011102; 1105 s->scr2 = 0x00ff0c80; 1106 s->old_scr2 = s->scr2; 1107 } 1108 1109 static void next_pc_realize(DeviceState *dev, Error **errp) 1110 { 1111 NeXTPC *s = NEXT_PC(dev); 1112 SysBusDevice *sbd; 1113 DeviceState *d; 1114 1115 /* SCSI */ 1116 sbd = SYS_BUS_DEVICE(&s->next_scsi); 1117 if (!sysbus_realize(sbd, errp)) { 1118 return; 1119 } 1120 1121 d = DEVICE(object_resolve_path_component(OBJECT(&s->next_scsi), "esp")); 1122 sysbus_connect_irq(SYS_BUS_DEVICE(d), 0, 1123 qdev_get_gpio_in(DEVICE(s), NEXT_SCSI_I)); 1124 1125 s->scsi_reset = qdev_get_gpio_in(d, 0); 1126 s->scsi_dma = qdev_get_gpio_in(d, 1); 1127 1128 /* ESCC */ 1129 d = DEVICE(&s->escc); 1130 qdev_prop_set_uint32(d, "disabled", 0); 1131 qdev_prop_set_uint32(d, "frequency", 9600 * 384); 1132 qdev_prop_set_uint32(d, "it_shift", 0); 1133 qdev_prop_set_bit(d, "bit_swap", true); 1134 qdev_prop_set_chr(d, "chrB", serial_hd(1)); 1135 qdev_prop_set_chr(d, "chrA", serial_hd(0)); 1136 qdev_prop_set_uint32(d, "chnBtype", escc_serial); 1137 qdev_prop_set_uint32(d, "chnAtype", escc_serial); 1138 1139 sbd = SYS_BUS_DEVICE(d); 1140 if (!sysbus_realize(sbd, errp)) { 1141 return; 1142 } 1143 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(dev, NEXT_SCC_I)); 1144 sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(dev, NEXT_SCC_DMA_I)); 1145 1146 /* RTC */ 1147 d = DEVICE(&s->rtc); 1148 if (!sysbus_realize(SYS_BUS_DEVICE(d), errp)) { 1149 return; 1150 } 1151 /* Data from NeXTPC to RTC */ 1152 qdev_connect_gpio_out_named(dev, "rtc-data-out", 0, 1153 qdev_get_gpio_in_named(d, "rtc-data-in", 0)); 1154 /* Data from RTC to NeXTPC */ 1155 qdev_connect_gpio_out_named(d, "rtc-data-out", 0, 1156 qdev_get_gpio_in_named(dev, 1157 "rtc-data-in", 0)); 1158 qdev_connect_gpio_out_named(dev, "rtc-cmd-reset", 0, 1159 qdev_get_gpio_in_named(d, "rtc-cmd-reset", 0)); 1160 qdev_connect_gpio_out_named(d, "rtc-power-out", 0, 1161 qdev_get_gpio_in(dev, NEXT_PWR_I)); 1162 } 1163 1164 static void next_pc_init(Object *obj) 1165 { 1166 NeXTPC *s = NEXT_PC(obj); 1167 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1168 1169 qdev_init_gpio_in(DEVICE(obj), next_irq, NEXT_NUM_IRQS); 1170 1171 memory_region_init_io(&s->mmiomem, OBJECT(s), &next_mmio_ops, s, 1172 "next.mmio", 0x9000); 1173 sysbus_init_mmio(sbd, &s->mmiomem); 1174 1175 memory_region_init_io(&s->dummyen_mem, OBJECT(s), &next_dummy_en_ops, s, 1176 "next.en", 0x20); 1177 sysbus_init_mmio(sbd, &s->dummyen_mem); 1178 1179 object_initialize_child(obj, "next-scsi", &s->next_scsi, TYPE_NEXT_SCSI); 1180 sysbus_init_mmio(sbd, 1181 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->next_scsi), 0)); 1182 1183 memory_region_init_io(&s->floppy_mem, OBJECT(s), &next_floppy_ops, s, 1184 "next.floppy", 4); 1185 sysbus_init_mmio(sbd, &s->floppy_mem); 1186 1187 object_initialize_child(obj, "escc", &s->escc, TYPE_ESCC); 1188 sysbus_init_mmio(sbd, 1189 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->escc), 0)); 1190 1191 memory_region_init_io(&s->timer_mem, OBJECT(s), &next_timer_ops, s, 1192 "next.timer", 4); 1193 sysbus_init_mmio(sbd, &s->timer_mem); 1194 1195 object_initialize_child(obj, "rtc", &s->rtc, TYPE_NEXT_RTC); 1196 1197 qdev_init_gpio_in_named(DEVICE(obj), next_pc_rtc_data_in_irq, 1198 "rtc-data-in", 1); 1199 qdev_init_gpio_out_named(DEVICE(obj), &s->rtc_data_irq, 1200 "rtc-data-out", 1); 1201 qdev_init_gpio_out_named(DEVICE(obj), &s->rtc_cmd_reset_irq, 1202 "rtc-cmd-reset", 1); 1203 } 1204 1205 /* 1206 * If the m68k CPU implemented its inbound irq lines as GPIO lines 1207 * rather than via the m68k_set_irq_level() function we would not need 1208 * this cpu link property and could instead provide outbound IRQ lines 1209 * that the board could wire up to the CPU. 1210 */ 1211 static const Property next_pc_properties[] = { 1212 DEFINE_PROP_LINK("cpu", NeXTPC, cpu, TYPE_M68K_CPU, M68kCPU *), 1213 }; 1214 1215 static const VMStateDescription next_pc_vmstate = { 1216 .name = "next-pc", 1217 .version_id = 4, 1218 .minimum_version_id = 4, 1219 .fields = (const VMStateField[]) { 1220 VMSTATE_UINT32(scr1, NeXTPC), 1221 VMSTATE_UINT32(scr2, NeXTPC), 1222 VMSTATE_UINT32(old_scr2, NeXTPC), 1223 VMSTATE_UINT32(int_mask, NeXTPC), 1224 VMSTATE_UINT32(int_status, NeXTPC), 1225 VMSTATE_UINT32(led, NeXTPC), 1226 VMSTATE_END_OF_LIST() 1227 }, 1228 }; 1229 1230 static void next_pc_class_init(ObjectClass *klass, void *data) 1231 { 1232 DeviceClass *dc = DEVICE_CLASS(klass); 1233 ResettableClass *rc = RESETTABLE_CLASS(klass); 1234 1235 dc->desc = "NeXT Peripheral Controller"; 1236 dc->realize = next_pc_realize; 1237 device_class_set_props(dc, next_pc_properties); 1238 dc->vmsd = &next_pc_vmstate; 1239 rc->phases.hold = next_pc_reset_hold; 1240 } 1241 1242 static const TypeInfo next_pc_info = { 1243 .name = TYPE_NEXT_PC, 1244 .parent = TYPE_SYS_BUS_DEVICE, 1245 .instance_init = next_pc_init, 1246 .instance_size = sizeof(NeXTPC), 1247 .class_init = next_pc_class_init, 1248 }; 1249 1250 static void next_cube_init(MachineState *machine) 1251 { 1252 NeXTState *m = NEXT_MACHINE(machine); 1253 M68kCPU *cpu; 1254 CPUM68KState *env; 1255 MemoryRegion *sysmem = get_system_memory(); 1256 const char *bios_name = machine->firmware ?: ROM_FILE; 1257 DeviceState *pcdev; 1258 1259 /* Initialize the cpu core */ 1260 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 1261 if (!cpu) { 1262 error_report("Unable to find m68k CPU definition"); 1263 exit(1); 1264 } 1265 env = &cpu->env; 1266 1267 /* Initialize CPU registers. */ 1268 env->vbr = 0; 1269 env->sr = 0x2700; 1270 1271 /* Peripheral Controller */ 1272 pcdev = qdev_new(TYPE_NEXT_PC); 1273 object_property_set_link(OBJECT(pcdev), "cpu", OBJECT(cpu), &error_abort); 1274 sysbus_realize_and_unref(SYS_BUS_DEVICE(pcdev), &error_fatal); 1275 1276 /* 64MB RAM starting at 0x04000000 */ 1277 memory_region_add_subregion(sysmem, 0x04000000, machine->ram); 1278 1279 /* Framebuffer */ 1280 sysbus_create_simple(TYPE_NEXTFB, 0x0B000000, NULL); 1281 1282 /* MMIO */ 1283 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02005000); 1284 1285 /* BMAP IO - acts as a catch-all for now */ 1286 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02100000); 1287 1288 /* en network (dummy) */ 1289 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02106000); 1290 1291 /* unknown: Brightness control register? */ 1292 empty_slot_init("next.unknown.0", 0x02110000, 0x10); 1293 /* unknown: Magneto-Optical drive controller? */ 1294 empty_slot_init("next.unknown.1", 0x02112000, 0x10); 1295 1296 /* SCSI */ 1297 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 2, 0x02114000); 1298 /* Floppy */ 1299 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 3, 0x02114108); 1300 /* ESCC */ 1301 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 4, 0x02118000); 1302 1303 /* unknown: Serial clock configuration register? */ 1304 empty_slot_init("next.unknown.2", 0x02118004, 0x10); 1305 1306 /* Timer */ 1307 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 5, 0x0211a000); 1308 1309 /* BMAP memory */ 1310 memory_region_init_ram_flags_nomigrate(&m->bmapm1, NULL, "next.bmapmem", 1311 64, RAM_SHARED, &error_fatal); 1312 memory_region_add_subregion(sysmem, 0x020c0000, &m->bmapm1); 1313 /* The Rev_2.5_v66.bin firmware accesses it at 0x820c0020, too */ 1314 memory_region_init_alias(&m->bmapm2, NULL, "next.bmapmem2", &m->bmapm1, 1315 0x0, 64); 1316 memory_region_add_subregion(sysmem, 0x820c0000, &m->bmapm2); 1317 1318 /* KBD */ 1319 sysbus_create_simple(TYPE_NEXTKBD, 0x0200e000, NULL); 1320 1321 /* Load ROM here */ 1322 memory_region_init_rom(&m->rom, NULL, "next.rom", 0x20000, &error_fatal); 1323 memory_region_add_subregion(sysmem, 0x01000000, &m->rom); 1324 memory_region_init_alias(&m->rom2, NULL, "next.rom2", &m->rom, 0x0, 1325 0x20000); 1326 memory_region_add_subregion(sysmem, 0x0, &m->rom2); 1327 if (load_image_targphys(bios_name, 0x01000000, 0x20000) < 8) { 1328 if (!qtest_enabled()) { 1329 error_report("Failed to load firmware '%s'.", bios_name); 1330 } 1331 } else { 1332 uint8_t *ptr; 1333 /* Initial PC is always at offset 4 in firmware binaries */ 1334 ptr = rom_ptr(0x01000004, 4); 1335 g_assert(ptr != NULL); 1336 env->pc = ldl_be_p(ptr); 1337 if (env->pc >= 0x01020000) { 1338 error_report("'%s' does not seem to be a valid firmware image.", 1339 bios_name); 1340 exit(1); 1341 } 1342 } 1343 1344 /* DMA */ 1345 memory_region_init_io(&m->dmamem, NULL, &next_dma_ops, machine, 1346 "next.dma", 0x5000); 1347 memory_region_add_subregion(sysmem, 0x02000000, &m->dmamem); 1348 } 1349 1350 static void next_machine_class_init(ObjectClass *oc, void *data) 1351 { 1352 MachineClass *mc = MACHINE_CLASS(oc); 1353 1354 mc->desc = "NeXT Cube"; 1355 mc->init = next_cube_init; 1356 mc->block_default_type = IF_SCSI; 1357 mc->default_ram_size = RAM_SIZE; 1358 mc->default_ram_id = "next.ram"; 1359 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); 1360 mc->no_cdrom = true; 1361 } 1362 1363 static const TypeInfo next_typeinfo = { 1364 .name = TYPE_NEXT_MACHINE, 1365 .parent = TYPE_MACHINE, 1366 .class_init = next_machine_class_init, 1367 .instance_size = sizeof(NeXTState), 1368 }; 1369 1370 static void next_register_type(void) 1371 { 1372 type_register_static(&next_typeinfo); 1373 type_register_static(&next_pc_info); 1374 type_register_static(&next_scsi_info); 1375 type_register_static(&next_rtc_info); 1376 } 1377 1378 type_init(next_register_type) 1379