1 /* 2 * NeXT Cube System Driver 3 * 4 * Copyright (c) 2011 Bryce Lanham 5 * 6 * This code is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published 8 * by the Free Software Foundation; either version 2 of the License, 9 * or (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "exec/hwaddr.h" 14 #include "system/system.h" 15 #include "system/qtest.h" 16 #include "hw/irq.h" 17 #include "hw/m68k/next-cube.h" 18 #include "hw/boards.h" 19 #include "hw/loader.h" 20 #include "hw/scsi/esp.h" 21 #include "hw/sysbus.h" 22 #include "qom/object.h" 23 #include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */ 24 #include "hw/block/fdc.h" 25 #include "hw/misc/empty_slot.h" 26 #include "hw/qdev-properties.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "ui/console.h" 30 #include "target/m68k/cpu.h" 31 #include "migration/vmstate.h" 32 33 /* #define DEBUG_NEXT */ 34 #ifdef DEBUG_NEXT 35 #define DPRINTF(fmt, ...) \ 36 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0) 37 #else 38 #define DPRINTF(fmt, ...) do { } while (0) 39 #endif 40 41 #define ENTRY 0x0100001e 42 #define RAM_SIZE 0x4000000 43 #define ROM_FILE "Rev_2.5_v66.bin" 44 45 typedef struct NeXTRTC { 46 int8_t phase; 47 uint8_t ram[32]; 48 uint8_t command; 49 uint8_t value; 50 uint8_t status; 51 uint8_t control; 52 uint8_t retval; 53 } NeXTRTC; 54 55 #define TYPE_NEXT_SCSI "next-scsi" 56 OBJECT_DECLARE_SIMPLE_TYPE(NeXTSCSI, NEXT_SCSI) 57 58 /* NeXT SCSI Controller */ 59 struct NeXTSCSI { 60 SysBusDevice parent_obj; 61 62 MemoryRegion scsi_mem; 63 64 SysBusESPState sysbus_esp; 65 66 MemoryRegion scsi_csr_mem; 67 uint8_t scsi_csr_1; 68 uint8_t scsi_csr_2; 69 }; 70 71 #define TYPE_NEXT_PC "next-pc" 72 OBJECT_DECLARE_SIMPLE_TYPE(NeXTPC, NEXT_PC) 73 74 /* NeXT Peripheral Controller */ 75 struct NeXTPC { 76 SysBusDevice parent_obj; 77 78 M68kCPU *cpu; 79 80 MemoryRegion floppy_mem; 81 MemoryRegion timer_mem; 82 MemoryRegion dummyen_mem; 83 MemoryRegion mmiomem; 84 MemoryRegion scrmem; 85 86 uint32_t scr1; 87 uint32_t scr2; 88 uint32_t old_scr2; 89 uint32_t int_mask; 90 uint32_t int_status; 91 uint32_t led; 92 93 NeXTSCSI next_scsi; 94 95 qemu_irq scsi_reset; 96 qemu_irq scsi_dma; 97 98 ESCCState escc; 99 100 NeXTRTC rtc; 101 qemu_irq rtc_power_irq; 102 }; 103 104 typedef struct next_dma { 105 uint32_t csr; 106 107 uint32_t saved_next; 108 uint32_t saved_limit; 109 uint32_t saved_start; 110 uint32_t saved_stop; 111 112 uint32_t next; 113 uint32_t limit; 114 uint32_t start; 115 uint32_t stop; 116 117 uint32_t next_initbuf; 118 uint32_t size; 119 } next_dma; 120 121 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube") 122 OBJECT_DECLARE_SIMPLE_TYPE(NeXTState, NEXT_MACHINE) 123 124 struct NeXTState { 125 MachineState parent; 126 127 MemoryRegion rom; 128 MemoryRegion rom2; 129 MemoryRegion dmamem; 130 MemoryRegion bmapm1; 131 MemoryRegion bmapm2; 132 133 next_dma dma[10]; 134 }; 135 136 /* Thanks to NeXT forums for this */ 137 /* 138 static const uint8_t rtc_ram3[32] = { 139 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 140 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00, 141 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00, 142 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13 143 }; 144 */ 145 static const uint8_t rtc_ram2[32] = { 146 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00, 147 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00, 148 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 149 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e, 150 }; 151 152 #define SCR2_RTCLK 0x2 153 #define SCR2_RTDATA 0x4 154 #define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10)) 155 156 static void next_scr2_led_update(NeXTPC *s) 157 { 158 if (s->scr2 & 0x1) { 159 DPRINTF("fault!\n"); 160 s->led++; 161 if (s->led == 10) { 162 DPRINTF("LED flashing, possible fault!\n"); 163 s->led = 0; 164 } 165 } 166 } 167 168 static bool next_rtc_cmd_is_write(uint8_t cmd) 169 { 170 return (cmd >= 0x80 && cmd <= 0x9f) || 171 (cmd == 0xb1); 172 } 173 174 static void next_rtc_data_in_irq(void *opaque, int n, int level) 175 { 176 NeXTPC *s = NEXT_PC(opaque); 177 NeXTRTC *rtc = &s->rtc; 178 179 if (rtc->phase < 8) { 180 rtc->command = (rtc->command << 1) | level; 181 182 if (rtc->phase == 7 && !next_rtc_cmd_is_write(rtc->command)) { 183 if (rtc->command <= 0x1f) { 184 /* RAM registers */ 185 rtc->retval = rtc->ram[rtc->command]; 186 } 187 if ((rtc->command >= 0x20) && (rtc->command <= 0x2f)) { 188 /* RTC */ 189 time_t time_h = time(NULL); 190 struct tm *info = localtime(&time_h); 191 rtc->retval = 0; 192 193 switch (rtc->command) { 194 case 0x20: 195 rtc->retval = SCR2_TOBCD(info->tm_sec); 196 break; 197 case 0x21: 198 rtc->retval = SCR2_TOBCD(info->tm_min); 199 break; 200 case 0x22: 201 rtc->retval = SCR2_TOBCD(info->tm_hour); 202 break; 203 case 0x24: 204 rtc->retval = SCR2_TOBCD(info->tm_mday); 205 break; 206 case 0x25: 207 rtc->retval = SCR2_TOBCD((info->tm_mon + 1)); 208 break; 209 case 0x26: 210 rtc->retval = SCR2_TOBCD((info->tm_year - 100)); 211 break; 212 } 213 } 214 if (rtc->command == 0x30) { 215 /* read the status 0x30 */ 216 rtc->retval = rtc->status; 217 } 218 if (rtc->command == 0x31) { 219 /* read the control 0x31 */ 220 rtc->retval = rtc->control; 221 } 222 } 223 } 224 if (rtc->phase >= 8 && rtc->phase < 16) { 225 if (next_rtc_cmd_is_write(rtc->command)) { 226 /* Shift in value to write */ 227 rtc->value = (rtc->value << 1) | level; 228 } else { 229 /* Shift out value to read */ 230 qemu_irq rtc_data_in_irq = qdev_get_gpio_in_named( 231 DEVICE(s), "pc-rtc-data-in", 0); 232 233 if (rtc->retval & (0x80 >> (rtc->phase - 8))) { 234 qemu_irq_raise(rtc_data_in_irq); 235 } else { 236 qemu_irq_lower(rtc_data_in_irq); 237 } 238 } 239 } 240 241 rtc->phase++; 242 if (rtc->phase == 16 && next_rtc_cmd_is_write(rtc->command)) { 243 if (rtc->command >= 0x80 && rtc->command <= 0x9f) { 244 /* RAM registers */ 245 rtc->ram[rtc->command - 0x80] = rtc->value; 246 } 247 if (rtc->command == 0xb1) { 248 /* write to 0x30 register */ 249 if (rtc->value & 0x04) { 250 /* clear FTU */ 251 rtc->status = rtc->status & (~0x18); 252 qemu_irq_lower(s->rtc_power_irq); 253 } 254 } 255 } 256 } 257 258 static void next_scr2_rtc_update(NeXTPC *s) 259 { 260 uint8_t old_scr2, scr2_2; 261 NeXTRTC *rtc = &s->rtc; 262 263 old_scr2 = extract32(s->old_scr2, 8, 8); 264 scr2_2 = extract32(s->scr2, 8, 8); 265 266 if (scr2_2 & 0x1) { 267 /* DPRINTF("RTC %x phase %i\n", scr2_2, rtc->phase); */ 268 if (rtc->phase == -1) { 269 rtc->phase = 0; 270 } 271 /* If we are in going down clock... do something */ 272 if (((old_scr2 & SCR2_RTCLK) != (scr2_2 & SCR2_RTCLK)) && 273 ((scr2_2 & SCR2_RTCLK) == 0)) { 274 qemu_irq rtc_data_in_irq = qdev_get_gpio_in_named( 275 DEVICE(s), "rtc-data-in", 0); 276 277 if (scr2_2 & SCR2_RTDATA) { 278 qemu_irq_raise(rtc_data_in_irq); 279 } else { 280 qemu_irq_lower(rtc_data_in_irq); 281 } 282 } 283 } else { 284 /* else end or abort */ 285 rtc->phase = -1; 286 rtc->command = 0; 287 rtc->value = 0; 288 } 289 } 290 291 static uint64_t next_mmio_read(void *opaque, hwaddr addr, unsigned size) 292 { 293 NeXTPC *s = NEXT_PC(opaque); 294 uint64_t val; 295 296 switch (addr) { 297 case 0x2000: /* 0x2007000 */ 298 /* DPRINTF("Read INT status: %x\n", s->int_status); */ 299 val = s->int_status; 300 break; 301 302 case 0x2800: /* 0x2007800 */ 303 DPRINTF("MMIO Read INT mask: %x\n", s->int_mask); 304 val = s->int_mask; 305 break; 306 307 case 0x7000 ... 0x7003: /* 0x200c000 */ 308 val = extract32(s->scr1, (4 - (addr - 0x7000) - size) << 3, 309 size << 3); 310 break; 311 312 case 0x8000 ... 0x8003: /* 0x200d000 */ 313 val = extract32(s->scr2, (4 - (addr - 0x8000) - size) << 3, 314 size << 3); 315 break; 316 317 default: 318 val = 0; 319 DPRINTF("MMIO Read @ 0x%"HWADDR_PRIx" size %d\n", addr, size); 320 break; 321 } 322 323 return val; 324 } 325 326 static void next_mmio_write(void *opaque, hwaddr addr, uint64_t val, 327 unsigned size) 328 { 329 NeXTPC *s = NEXT_PC(opaque); 330 331 switch (addr) { 332 case 0x2000: /* 0x2007000 */ 333 DPRINTF("INT Status old: %x new: %x\n", s->int_status, 334 (unsigned int)val); 335 s->int_status = val; 336 break; 337 338 case 0x2800: /* 0x2007800 */ 339 DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, (unsigned int)val); 340 s->int_mask = val; 341 break; 342 343 case 0x7000 ... 0x7003: /* 0x200c000 */ 344 DPRINTF("SCR1 Write: %x\n", (unsigned int)val); 345 s->scr1 = deposit32(s->scr1, (4 - (addr - 0x7000) - size) << 3, 346 size << 3, val); 347 break; 348 349 case 0x8000 ... 0x8003: /* 0x200d000 */ 350 s->scr2 = deposit32(s->scr2, (4 - (addr - 0x8000) - size) << 3, 351 size << 3, val); 352 next_scr2_led_update(s); 353 next_scr2_rtc_update(s); 354 s->old_scr2 = s->scr2; 355 break; 356 357 default: 358 DPRINTF("MMIO Write @ 0x%"HWADDR_PRIx " with 0x%x size %u\n", addr, 359 (unsigned int)val, size); 360 } 361 } 362 363 static const MemoryRegionOps next_mmio_ops = { 364 .read = next_mmio_read, 365 .write = next_mmio_write, 366 .valid.min_access_size = 1, 367 .valid.max_access_size = 4, 368 .endianness = DEVICE_BIG_ENDIAN, 369 }; 370 371 #define SCSICSR_ENABLE 0x01 372 #define SCSICSR_RESET 0x02 /* reset scsi dma */ 373 #define SCSICSR_FIFOFL 0x04 374 #define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */ 375 #define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */ 376 #define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */ 377 378 #define NEXTDMA_SCSI(x) (0x10 + x) 379 #define NEXTDMA_FD(x) (0x10 + x) 380 #define NEXTDMA_ENTX(x) (0x110 + x) 381 #define NEXTDMA_ENRX(x) (0x150 + x) 382 #define NEXTDMA_CSR 0x0 383 #define NEXTDMA_NEXT 0x4000 384 #define NEXTDMA_LIMIT 0x4004 385 #define NEXTDMA_START 0x4008 386 #define NEXTDMA_STOP 0x400c 387 #define NEXTDMA_NEXT_INIT 0x4200 388 #define NEXTDMA_SIZE 0x4204 389 390 static void next_dma_write(void *opaque, hwaddr addr, uint64_t val, 391 unsigned int size) 392 { 393 NeXTState *next_state = NEXT_MACHINE(opaque); 394 395 switch (addr) { 396 case NEXTDMA_ENRX(NEXTDMA_CSR): 397 if (val & DMA_DEV2M) { 398 next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M; 399 } 400 401 if (val & DMA_SETENABLE) { 402 /* DPRINTF("SCSI DMA ENABLE\n"); */ 403 next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE; 404 } 405 if (val & DMA_SETSUPDATE) { 406 next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE; 407 } 408 if (val & DMA_CLRCOMPLETE) { 409 next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE; 410 } 411 412 if (val & DMA_RESET) { 413 next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 414 DMA_ENABLE | DMA_DEV2M); 415 } 416 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 417 break; 418 419 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 420 next_state->dma[NEXTDMA_ENRX].next_initbuf = val; 421 break; 422 423 case NEXTDMA_ENRX(NEXTDMA_NEXT): 424 next_state->dma[NEXTDMA_ENRX].next = val; 425 break; 426 427 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 428 next_state->dma[NEXTDMA_ENRX].limit = val; 429 break; 430 431 case NEXTDMA_SCSI(NEXTDMA_CSR): 432 if (val & DMA_DEV2M) { 433 next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M; 434 } 435 if (val & DMA_SETENABLE) { 436 /* DPRINTF("SCSI DMA ENABLE\n"); */ 437 next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE; 438 } 439 if (val & DMA_SETSUPDATE) { 440 next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE; 441 } 442 if (val & DMA_CLRCOMPLETE) { 443 next_state->dma[NEXTDMA_SCSI].csr &= ~DMA_COMPLETE; 444 } 445 446 if (val & DMA_RESET) { 447 next_state->dma[NEXTDMA_SCSI].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 448 DMA_ENABLE | DMA_DEV2M); 449 /* DPRINTF("SCSI DMA RESET\n"); */ 450 } 451 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 452 break; 453 454 case NEXTDMA_SCSI(NEXTDMA_NEXT): 455 next_state->dma[NEXTDMA_SCSI].next = val; 456 break; 457 458 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 459 next_state->dma[NEXTDMA_SCSI].limit = val; 460 break; 461 462 case NEXTDMA_SCSI(NEXTDMA_START): 463 next_state->dma[NEXTDMA_SCSI].start = val; 464 break; 465 466 case NEXTDMA_SCSI(NEXTDMA_STOP): 467 next_state->dma[NEXTDMA_SCSI].stop = val; 468 break; 469 470 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 471 next_state->dma[NEXTDMA_SCSI].next_initbuf = val; 472 break; 473 474 default: 475 DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)val); 476 } 477 } 478 479 static uint64_t next_dma_read(void *opaque, hwaddr addr, unsigned int size) 480 { 481 NeXTState *next_state = NEXT_MACHINE(opaque); 482 uint64_t val; 483 484 switch (addr) { 485 case NEXTDMA_SCSI(NEXTDMA_CSR): 486 DPRINTF("SCSI DMA CSR READ\n"); 487 val = next_state->dma[NEXTDMA_SCSI].csr; 488 break; 489 490 case NEXTDMA_ENRX(NEXTDMA_CSR): 491 val = next_state->dma[NEXTDMA_ENRX].csr; 492 break; 493 494 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 495 val = next_state->dma[NEXTDMA_ENRX].next_initbuf; 496 break; 497 498 case NEXTDMA_ENRX(NEXTDMA_NEXT): 499 val = next_state->dma[NEXTDMA_ENRX].next; 500 break; 501 502 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 503 val = next_state->dma[NEXTDMA_ENRX].limit; 504 break; 505 506 case NEXTDMA_SCSI(NEXTDMA_NEXT): 507 val = next_state->dma[NEXTDMA_SCSI].next; 508 break; 509 510 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 511 val = next_state->dma[NEXTDMA_SCSI].next_initbuf; 512 break; 513 514 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 515 val = next_state->dma[NEXTDMA_SCSI].limit; 516 break; 517 518 case NEXTDMA_SCSI(NEXTDMA_START): 519 val = next_state->dma[NEXTDMA_SCSI].start; 520 break; 521 522 case NEXTDMA_SCSI(NEXTDMA_STOP): 523 val = next_state->dma[NEXTDMA_SCSI].stop; 524 break; 525 526 default: 527 DPRINTF("DMA read @ %x\n", (unsigned int)addr); 528 val = 0; 529 } 530 531 /* 532 * once the csr's are done, subtract 0x3FEC from the addr, and that will 533 * normalize the upper registers 534 */ 535 536 return val; 537 } 538 539 static const MemoryRegionOps next_dma_ops = { 540 .read = next_dma_read, 541 .write = next_dma_write, 542 .impl.min_access_size = 4, 543 .valid.min_access_size = 4, 544 .valid.max_access_size = 4, 545 .endianness = DEVICE_BIG_ENDIAN, 546 }; 547 548 static void next_irq(void *opaque, int number, int level) 549 { 550 NeXTPC *s = NEXT_PC(opaque); 551 M68kCPU *cpu = s->cpu; 552 int shift = 0; 553 554 /* first switch sets interrupt status */ 555 /* DPRINTF("IRQ %i\n",number); */ 556 switch (number) { 557 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 558 case NEXT_FD_I: 559 shift = 7; 560 break; 561 case NEXT_KBD_I: 562 shift = 3; 563 break; 564 case NEXT_PWR_I: 565 shift = 2; 566 break; 567 case NEXT_ENRX_I: 568 shift = 9; 569 break; 570 case NEXT_ENTX_I: 571 shift = 10; 572 break; 573 case NEXT_SCSI_I: 574 shift = 12; 575 break; 576 case NEXT_CLK_I: 577 shift = 5; 578 break; 579 580 /* level 5 - scc (serial) */ 581 case NEXT_SCC_I: 582 shift = 17; 583 break; 584 585 /* level 6 - audio etherrx/tx dma */ 586 case NEXT_ENTX_DMA_I: 587 shift = 28; 588 break; 589 case NEXT_ENRX_DMA_I: 590 shift = 27; 591 break; 592 case NEXT_SCSI_DMA_I: 593 shift = 26; 594 break; 595 case NEXT_SND_I: 596 shift = 23; 597 break; 598 case NEXT_SCC_DMA_I: 599 shift = 21; 600 break; 601 602 } 603 /* 604 * this HAS to be wrong, the interrupt handlers in mach and together 605 * int_status and int_mask and return if there is a hit 606 */ 607 if (s->int_mask & (1 << shift)) { 608 DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc); 609 /* return; */ 610 } 611 612 /* second switch triggers the correct interrupt */ 613 if (level) { 614 s->int_status |= 1 << shift; 615 616 switch (number) { 617 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 618 case NEXT_FD_I: 619 case NEXT_KBD_I: 620 case NEXT_PWR_I: 621 case NEXT_ENRX_I: 622 case NEXT_ENTX_I: 623 case NEXT_SCSI_I: 624 case NEXT_CLK_I: 625 m68k_set_irq_level(cpu, 3, 27); 626 break; 627 628 /* level 5 - scc (serial) */ 629 case NEXT_SCC_I: 630 m68k_set_irq_level(cpu, 5, 29); 631 break; 632 633 /* level 6 - audio etherrx/tx dma */ 634 case NEXT_ENTX_DMA_I: 635 case NEXT_ENRX_DMA_I: 636 case NEXT_SCSI_DMA_I: 637 case NEXT_SND_I: 638 case NEXT_SCC_DMA_I: 639 m68k_set_irq_level(cpu, 6, 30); 640 break; 641 } 642 } else { 643 s->int_status &= ~(1 << shift); 644 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); 645 } 646 } 647 648 static void nextdma_write(void *opaque, uint8_t *buf, int size, int type) 649 { 650 uint32_t base_addr; 651 int irq = 0; 652 uint8_t align = 16; 653 NeXTState *next_state = NEXT_MACHINE(qdev_get_machine()); 654 655 if (type == NEXTDMA_ENRX || type == NEXTDMA_ENTX) { 656 align = 32; 657 } 658 /* Most DMA is supposedly 16 byte aligned */ 659 if ((size % align) != 0) { 660 size -= size % align; 661 size += align; 662 } 663 664 /* 665 * prom sets the dma start using initbuf while the bootloader uses next 666 * so we check to see if initbuf is 0 667 */ 668 if (next_state->dma[type].next_initbuf == 0) { 669 base_addr = next_state->dma[type].next; 670 } else { 671 base_addr = next_state->dma[type].next_initbuf; 672 } 673 674 cpu_physical_memory_write(base_addr, buf, size); 675 676 next_state->dma[type].next_initbuf = 0; 677 678 /* saved limit is checked to calculate packet size by both, rom and netbsd */ 679 next_state->dma[type].saved_limit = (next_state->dma[type].next + size); 680 next_state->dma[type].saved_next = (next_state->dma[type].next); 681 682 /* 683 * 32 bytes under savedbase seems to be some kind of register 684 * of which the purpose is unknown as of yet 685 */ 686 /* stl_phys(s->rx_dma.base-32,0xFFFFFFFF); */ 687 688 if (!(next_state->dma[type].csr & DMA_SUPDATE)) { 689 next_state->dma[type].next = next_state->dma[type].start; 690 next_state->dma[type].limit = next_state->dma[type].stop; 691 } 692 693 /* Set dma registers and raise an irq */ 694 next_state->dma[type].csr |= DMA_COMPLETE; /* DON'T CHANGE THIS! */ 695 696 switch (type) { 697 case NEXTDMA_SCSI: 698 irq = NEXT_SCSI_DMA_I; 699 break; 700 } 701 702 next_irq(opaque, irq, 1); 703 next_irq(opaque, irq, 0); 704 } 705 706 static void nextscsi_read(void *opaque, uint8_t *buf, int len) 707 { 708 DPRINTF("SCSI READ: %x\n", len); 709 abort(); 710 } 711 712 static void nextscsi_write(void *opaque, uint8_t *buf, int size) 713 { 714 DPRINTF("SCSI WRITE: %i\n", size); 715 nextdma_write(opaque, buf, size, NEXTDMA_SCSI); 716 } 717 718 static void next_scsi_csr_write(void *opaque, hwaddr addr, uint64_t val, 719 unsigned size) 720 { 721 NeXTSCSI *s = NEXT_SCSI(opaque); 722 NeXTPC *pc = NEXT_PC(container_of(s, NeXTPC, next_scsi)); 723 724 switch (addr) { 725 case 0: 726 if (val & SCSICSR_FIFOFL) { 727 DPRINTF("SCSICSR FIFO Flush\n"); 728 /* will have to add another irq to the esp if this is needed */ 729 /* esp_puflush_fifo(esp_g); */ 730 } 731 732 if (val & SCSICSR_ENABLE) { 733 DPRINTF("SCSICSR Enable\n"); 734 /* 735 * qemu_irq_raise(s->scsi_dma); 736 * s->scsi_csr_1 = 0xc0; 737 * s->scsi_csr_1 |= 0x1; 738 * qemu_irq_pulse(s->scsi_dma); 739 */ 740 } 741 /* 742 * else 743 * s->scsi_csr_1 &= ~SCSICSR_ENABLE; 744 */ 745 746 if (val & SCSICSR_RESET) { 747 DPRINTF("SCSICSR Reset\n"); 748 /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */ 749 qemu_irq_raise(pc->scsi_reset); 750 s->scsi_csr_1 &= ~(SCSICSR_INTMASK | 0x80 | 0x1); 751 qemu_irq_lower(pc->scsi_reset); 752 } 753 if (val & SCSICSR_DMADIR) { 754 DPRINTF("SCSICSR DMAdir\n"); 755 } 756 if (val & SCSICSR_CPUDMA) { 757 DPRINTF("SCSICSR CPUDMA\n"); 758 /* qemu_irq_raise(s->scsi_dma); */ 759 pc->int_status |= 0x4000000; 760 } else { 761 /* fprintf(stderr,"SCSICSR CPUDMA disabled\n"); */ 762 pc->int_status &= ~(0x4000000); 763 /* qemu_irq_lower(s->scsi_dma); */ 764 } 765 if (val & SCSICSR_INTMASK) { 766 DPRINTF("SCSICSR INTMASK\n"); 767 /* 768 * int_mask &= ~0x1000; 769 * s->scsi_csr_1 |= val; 770 * s->scsi_csr_1 &= ~SCSICSR_INTMASK; 771 * if (s->scsi_queued) { 772 * s->scsi_queued = 0; 773 * next_irq(s, NEXT_SCSI_I, level); 774 * } 775 */ 776 } else { 777 /* int_mask |= 0x1000; */ 778 } 779 if (val & 0x80) { 780 /* int_mask |= 0x1000; */ 781 /* s->scsi_csr_1 |= 0x80; */ 782 } 783 DPRINTF("SCSICSR1 Write: %"PRIx64 "\n", val); 784 s->scsi_csr_1 = val; 785 break; 786 787 case 1: 788 DPRINTF("SCSICSR2 Write: %"PRIx64 "\n", val); 789 s->scsi_csr_2 = val; 790 break; 791 792 default: 793 g_assert_not_reached(); 794 } 795 } 796 797 static uint64_t next_scsi_csr_read(void *opaque, hwaddr addr, unsigned size) 798 { 799 NeXTSCSI *s = NEXT_SCSI(opaque); 800 uint64_t val; 801 802 switch (addr) { 803 case 0: 804 DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1); 805 val = s->scsi_csr_1; 806 break; 807 808 case 1: 809 DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2); 810 val = s->scsi_csr_2; 811 break; 812 813 default: 814 g_assert_not_reached(); 815 } 816 817 return val; 818 } 819 820 static const MemoryRegionOps next_scsi_csr_ops = { 821 .read = next_scsi_csr_read, 822 .write = next_scsi_csr_write, 823 .valid.min_access_size = 1, 824 .valid.max_access_size = 1, 825 .endianness = DEVICE_BIG_ENDIAN, 826 }; 827 828 static void next_scsi_init(Object *obj) 829 { 830 NeXTSCSI *s = NEXT_SCSI(obj); 831 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 832 833 object_initialize_child(obj, "esp", &s->sysbus_esp, TYPE_SYSBUS_ESP); 834 835 memory_region_init_io(&s->scsi_csr_mem, obj, &next_scsi_csr_ops, 836 s, "csrs", 2); 837 838 memory_region_init(&s->scsi_mem, obj, "next.scsi", 0x40); 839 sysbus_init_mmio(sbd, &s->scsi_mem); 840 } 841 842 static void next_scsi_realize(DeviceState *dev, Error **errp) 843 { 844 NeXTSCSI *s = NEXT_SCSI(dev); 845 SysBusESPState *sysbus_esp; 846 SysBusDevice *sbd; 847 ESPState *esp; 848 NeXTPC *pcdev; 849 850 pcdev = NEXT_PC(container_of(s, NeXTPC, next_scsi)); 851 852 /* ESP */ 853 sysbus_esp = SYSBUS_ESP(&s->sysbus_esp); 854 esp = &sysbus_esp->esp; 855 esp->dma_memory_read = nextscsi_read; 856 esp->dma_memory_write = nextscsi_write; 857 esp->dma_opaque = pcdev; 858 sysbus_esp->it_shift = 0; 859 esp->dma_enabled = 1; 860 sbd = SYS_BUS_DEVICE(sysbus_esp); 861 if (!sysbus_realize(sbd, errp)) { 862 return; 863 } 864 memory_region_add_subregion(&s->scsi_mem, 0x0, 865 sysbus_mmio_get_region(sbd, 0)); 866 867 /* SCSI CSRs */ 868 memory_region_add_subregion(&s->scsi_mem, 0x20, &s->scsi_csr_mem); 869 870 scsi_bus_legacy_handle_cmdline(&s->sysbus_esp.esp.bus); 871 } 872 873 static const VMStateDescription next_scsi_vmstate = { 874 .name = "next-scsi", 875 .version_id = 0, 876 .minimum_version_id = 0, 877 .fields = (const VMStateField[]) { 878 VMSTATE_UINT8(scsi_csr_1, NeXTSCSI), 879 VMSTATE_UINT8(scsi_csr_2, NeXTSCSI), 880 VMSTATE_END_OF_LIST() 881 }, 882 }; 883 884 static void next_scsi_class_init(ObjectClass *klass, void *data) 885 { 886 DeviceClass *dc = DEVICE_CLASS(klass); 887 888 dc->desc = "NeXT SCSI Controller"; 889 dc->realize = next_scsi_realize; 890 dc->vmsd = &next_scsi_vmstate; 891 } 892 893 static const TypeInfo next_scsi_info = { 894 .name = TYPE_NEXT_SCSI, 895 .parent = TYPE_SYS_BUS_DEVICE, 896 .instance_init = next_scsi_init, 897 .instance_size = sizeof(NeXTSCSI), 898 .class_init = next_scsi_class_init, 899 }; 900 901 static void next_floppy_write(void *opaque, hwaddr addr, uint64_t val, 902 unsigned size) 903 { 904 switch (addr) { 905 case 0: 906 DPRINTF("FDCSR Write: %"PRIx64 "\n", val); 907 if (val == 0x0) { 908 /* qemu_irq_raise(s->fd_irq[0]); */ 909 } 910 break; 911 912 default: 913 g_assert_not_reached(); 914 } 915 } 916 917 static uint64_t next_floppy_read(void *opaque, hwaddr addr, unsigned size) 918 { 919 uint64_t val; 920 921 switch (addr) { 922 case 0: 923 DPRINTF("FD read @ %x\n", (unsigned int)addr); 924 val = 0x40 | 0x04 | 0x2 | 0x1; 925 break; 926 927 default: 928 g_assert_not_reached(); 929 } 930 931 return val; 932 } 933 934 static const MemoryRegionOps next_floppy_ops = { 935 .read = next_floppy_read, 936 .write = next_floppy_write, 937 .valid.min_access_size = 1, 938 .valid.max_access_size = 4, 939 .endianness = DEVICE_BIG_ENDIAN, 940 }; 941 942 static void next_timer_write(void *opaque, hwaddr addr, uint64_t val, 943 unsigned size) 944 { 945 switch (addr) { 946 case 0 ... 3: 947 /* Hardware timer latch - not implemented yet */ 948 break; 949 950 default: 951 g_assert_not_reached(); 952 } 953 } 954 955 static uint64_t next_timer_read(void *opaque, hwaddr addr, unsigned size) 956 { 957 uint64_t val; 958 959 switch (addr) { 960 case 0 ... 3: 961 /* 962 * These 4 registers are the hardware timer, not sure which register 963 * is the latch instead of data, but no problems so far. 964 * 965 * Hack: We need to have the LSB change consistently to make it work 966 */ 967 val = extract32(clock(), (4 - addr - size) << 3, 968 size << 3); 969 break; 970 971 default: 972 g_assert_not_reached(); 973 } 974 975 return val; 976 } 977 978 static const MemoryRegionOps next_timer_ops = { 979 .read = next_timer_read, 980 .write = next_timer_write, 981 .valid.min_access_size = 1, 982 .valid.max_access_size = 4, 983 .endianness = DEVICE_BIG_ENDIAN, 984 }; 985 986 static void next_dummy_en_write(void *opaque, hwaddr addr, uint64_t val, 987 unsigned size) 988 { 989 /* Do nothing */ 990 return; 991 } 992 993 static uint64_t next_dummy_en_read(void *opaque, hwaddr addr, unsigned size) 994 { 995 uint64_t val; 996 997 switch (addr) { 998 case 0: 999 /* For now return dummy byte to allow the Ethernet test to timeout */ 1000 val = 0xff; 1001 break; 1002 1003 default: 1004 val = 0; 1005 } 1006 1007 return val; 1008 } 1009 1010 static const MemoryRegionOps next_dummy_en_ops = { 1011 .read = next_dummy_en_read, 1012 .write = next_dummy_en_write, 1013 .valid.min_access_size = 1, 1014 .valid.max_access_size = 4, 1015 .endianness = DEVICE_BIG_ENDIAN, 1016 }; 1017 1018 static void next_pc_rtc_data_in_irq(void *opaque, int n, int level) 1019 { 1020 NeXTPC *s = NEXT_PC(opaque); 1021 uint8_t scr2_2 = extract32(s->scr2, 8, 8); 1022 1023 if (level) { 1024 scr2_2 |= SCR2_RTDATA; 1025 } else { 1026 scr2_2 &= ~SCR2_RTDATA; 1027 } 1028 1029 s->scr2 = deposit32(s->scr2, 8, 8, scr2_2); 1030 } 1031 1032 static void next_pc_reset_hold(Object *obj, ResetType type) 1033 { 1034 NeXTPC *s = NEXT_PC(obj); 1035 1036 /* Set internal registers to initial values */ 1037 /* 0x0000XX00 << vital bits */ 1038 s->scr1 = 0x00011102; 1039 s->scr2 = 0x00ff0c80; 1040 s->old_scr2 = s->scr2; 1041 1042 s->rtc.status = 0x90; 1043 1044 /* Load RTC RAM - TODO: provide possibility to load contents from file */ 1045 memcpy(s->rtc.ram, rtc_ram2, 32); 1046 } 1047 1048 static void next_pc_realize(DeviceState *dev, Error **errp) 1049 { 1050 NeXTPC *s = NEXT_PC(dev); 1051 SysBusDevice *sbd; 1052 DeviceState *d; 1053 1054 /* SCSI */ 1055 sbd = SYS_BUS_DEVICE(&s->next_scsi); 1056 if (!sysbus_realize(sbd, errp)) { 1057 return; 1058 } 1059 1060 d = DEVICE(object_resolve_path_component(OBJECT(&s->next_scsi), "esp")); 1061 sysbus_connect_irq(SYS_BUS_DEVICE(d), 0, 1062 qdev_get_gpio_in(DEVICE(s), NEXT_SCSI_I)); 1063 1064 s->scsi_reset = qdev_get_gpio_in(d, 0); 1065 s->scsi_dma = qdev_get_gpio_in(d, 1); 1066 1067 /* ESCC */ 1068 d = DEVICE(&s->escc); 1069 qdev_prop_set_uint32(d, "disabled", 0); 1070 qdev_prop_set_uint32(d, "frequency", 9600 * 384); 1071 qdev_prop_set_uint32(d, "it_shift", 0); 1072 qdev_prop_set_bit(d, "bit_swap", true); 1073 qdev_prop_set_chr(d, "chrB", serial_hd(1)); 1074 qdev_prop_set_chr(d, "chrA", serial_hd(0)); 1075 qdev_prop_set_uint32(d, "chnBtype", escc_serial); 1076 qdev_prop_set_uint32(d, "chnAtype", escc_serial); 1077 1078 sbd = SYS_BUS_DEVICE(d); 1079 if (!sysbus_realize(sbd, errp)) { 1080 return; 1081 } 1082 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(dev, NEXT_SCC_I)); 1083 sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(dev, NEXT_SCC_DMA_I)); 1084 } 1085 1086 static void next_pc_init(Object *obj) 1087 { 1088 NeXTPC *s = NEXT_PC(obj); 1089 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1090 1091 qdev_init_gpio_in(DEVICE(obj), next_irq, NEXT_NUM_IRQS); 1092 1093 memory_region_init_io(&s->mmiomem, OBJECT(s), &next_mmio_ops, s, 1094 "next.mmio", 0x9000); 1095 sysbus_init_mmio(sbd, &s->mmiomem); 1096 1097 memory_region_init_io(&s->dummyen_mem, OBJECT(s), &next_dummy_en_ops, s, 1098 "next.en", 0x20); 1099 sysbus_init_mmio(sbd, &s->dummyen_mem); 1100 1101 object_initialize_child(obj, "next-scsi", &s->next_scsi, TYPE_NEXT_SCSI); 1102 sysbus_init_mmio(sbd, 1103 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->next_scsi), 0)); 1104 1105 memory_region_init_io(&s->floppy_mem, OBJECT(s), &next_floppy_ops, s, 1106 "next.floppy", 4); 1107 sysbus_init_mmio(sbd, &s->floppy_mem); 1108 1109 object_initialize_child(obj, "escc", &s->escc, TYPE_ESCC); 1110 sysbus_init_mmio(sbd, 1111 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->escc), 0)); 1112 1113 memory_region_init_io(&s->timer_mem, OBJECT(s), &next_timer_ops, s, 1114 "next.timer", 4); 1115 sysbus_init_mmio(sbd, &s->timer_mem); 1116 1117 s->rtc_power_irq = qdev_get_gpio_in(DEVICE(obj), NEXT_PWR_I); 1118 qdev_init_gpio_in_named(DEVICE(obj), next_pc_rtc_data_in_irq, 1119 "pc-rtc-data-in", 1); 1120 qdev_init_gpio_in_named(DEVICE(obj), next_rtc_data_in_irq, 1121 "rtc-data-in", 1); 1122 } 1123 1124 /* 1125 * If the m68k CPU implemented its inbound irq lines as GPIO lines 1126 * rather than via the m68k_set_irq_level() function we would not need 1127 * this cpu link property and could instead provide outbound IRQ lines 1128 * that the board could wire up to the CPU. 1129 */ 1130 static const Property next_pc_properties[] = { 1131 DEFINE_PROP_LINK("cpu", NeXTPC, cpu, TYPE_M68K_CPU, M68kCPU *), 1132 }; 1133 1134 static const VMStateDescription next_rtc_vmstate = { 1135 .name = "next-rtc", 1136 .version_id = 2, 1137 .minimum_version_id = 2, 1138 .fields = (const VMStateField[]) { 1139 VMSTATE_INT8(phase, NeXTRTC), 1140 VMSTATE_UINT8_ARRAY(ram, NeXTRTC, 32), 1141 VMSTATE_UINT8(command, NeXTRTC), 1142 VMSTATE_UINT8(value, NeXTRTC), 1143 VMSTATE_UINT8(status, NeXTRTC), 1144 VMSTATE_UINT8(control, NeXTRTC), 1145 VMSTATE_UINT8(retval, NeXTRTC), 1146 VMSTATE_END_OF_LIST() 1147 }, 1148 }; 1149 1150 static const VMStateDescription next_pc_vmstate = { 1151 .name = "next-pc", 1152 .version_id = 3, 1153 .minimum_version_id = 3, 1154 .fields = (const VMStateField[]) { 1155 VMSTATE_UINT32(scr1, NeXTPC), 1156 VMSTATE_UINT32(scr2, NeXTPC), 1157 VMSTATE_UINT32(old_scr2, NeXTPC), 1158 VMSTATE_UINT32(int_mask, NeXTPC), 1159 VMSTATE_UINT32(int_status, NeXTPC), 1160 VMSTATE_UINT32(led, NeXTPC), 1161 VMSTATE_STRUCT(rtc, NeXTPC, 0, next_rtc_vmstate, NeXTRTC), 1162 VMSTATE_END_OF_LIST() 1163 }, 1164 }; 1165 1166 static void next_pc_class_init(ObjectClass *klass, void *data) 1167 { 1168 DeviceClass *dc = DEVICE_CLASS(klass); 1169 ResettableClass *rc = RESETTABLE_CLASS(klass); 1170 1171 dc->desc = "NeXT Peripheral Controller"; 1172 dc->realize = next_pc_realize; 1173 device_class_set_props(dc, next_pc_properties); 1174 dc->vmsd = &next_pc_vmstate; 1175 rc->phases.hold = next_pc_reset_hold; 1176 } 1177 1178 static const TypeInfo next_pc_info = { 1179 .name = TYPE_NEXT_PC, 1180 .parent = TYPE_SYS_BUS_DEVICE, 1181 .instance_init = next_pc_init, 1182 .instance_size = sizeof(NeXTPC), 1183 .class_init = next_pc_class_init, 1184 }; 1185 1186 static void next_cube_init(MachineState *machine) 1187 { 1188 NeXTState *m = NEXT_MACHINE(machine); 1189 M68kCPU *cpu; 1190 CPUM68KState *env; 1191 MemoryRegion *sysmem = get_system_memory(); 1192 const char *bios_name = machine->firmware ?: ROM_FILE; 1193 DeviceState *pcdev; 1194 1195 /* Initialize the cpu core */ 1196 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 1197 if (!cpu) { 1198 error_report("Unable to find m68k CPU definition"); 1199 exit(1); 1200 } 1201 env = &cpu->env; 1202 1203 /* Initialize CPU registers. */ 1204 env->vbr = 0; 1205 env->sr = 0x2700; 1206 1207 /* Peripheral Controller */ 1208 pcdev = qdev_new(TYPE_NEXT_PC); 1209 object_property_set_link(OBJECT(pcdev), "cpu", OBJECT(cpu), &error_abort); 1210 sysbus_realize_and_unref(SYS_BUS_DEVICE(pcdev), &error_fatal); 1211 1212 /* 64MB RAM starting at 0x04000000 */ 1213 memory_region_add_subregion(sysmem, 0x04000000, machine->ram); 1214 1215 /* Framebuffer */ 1216 sysbus_create_simple(TYPE_NEXTFB, 0x0B000000, NULL); 1217 1218 /* MMIO */ 1219 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02005000); 1220 1221 /* BMAP IO - acts as a catch-all for now */ 1222 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02100000); 1223 1224 /* en network (dummy) */ 1225 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02106000); 1226 1227 /* unknown: Brightness control register? */ 1228 empty_slot_init("next.unknown.0", 0x02110000, 0x10); 1229 /* unknown: Magneto-Optical drive controller? */ 1230 empty_slot_init("next.unknown.1", 0x02112000, 0x10); 1231 1232 /* SCSI */ 1233 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 2, 0x02114000); 1234 /* Floppy */ 1235 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 3, 0x02114108); 1236 /* ESCC */ 1237 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 4, 0x02118000); 1238 1239 /* unknown: Serial clock configuration register? */ 1240 empty_slot_init("next.unknown.2", 0x02118004, 0x10); 1241 1242 /* Timer */ 1243 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 5, 0x0211a000); 1244 1245 /* BMAP memory */ 1246 memory_region_init_ram_flags_nomigrate(&m->bmapm1, NULL, "next.bmapmem", 1247 64, RAM_SHARED, &error_fatal); 1248 memory_region_add_subregion(sysmem, 0x020c0000, &m->bmapm1); 1249 /* The Rev_2.5_v66.bin firmware accesses it at 0x820c0020, too */ 1250 memory_region_init_alias(&m->bmapm2, NULL, "next.bmapmem2", &m->bmapm1, 1251 0x0, 64); 1252 memory_region_add_subregion(sysmem, 0x820c0000, &m->bmapm2); 1253 1254 /* KBD */ 1255 sysbus_create_simple(TYPE_NEXTKBD, 0x0200e000, NULL); 1256 1257 /* Load ROM here */ 1258 memory_region_init_rom(&m->rom, NULL, "next.rom", 0x20000, &error_fatal); 1259 memory_region_add_subregion(sysmem, 0x01000000, &m->rom); 1260 memory_region_init_alias(&m->rom2, NULL, "next.rom2", &m->rom, 0x0, 1261 0x20000); 1262 memory_region_add_subregion(sysmem, 0x0, &m->rom2); 1263 if (load_image_targphys(bios_name, 0x01000000, 0x20000) < 8) { 1264 if (!qtest_enabled()) { 1265 error_report("Failed to load firmware '%s'.", bios_name); 1266 } 1267 } else { 1268 uint8_t *ptr; 1269 /* Initial PC is always at offset 4 in firmware binaries */ 1270 ptr = rom_ptr(0x01000004, 4); 1271 g_assert(ptr != NULL); 1272 env->pc = ldl_be_p(ptr); 1273 if (env->pc >= 0x01020000) { 1274 error_report("'%s' does not seem to be a valid firmware image.", 1275 bios_name); 1276 exit(1); 1277 } 1278 } 1279 1280 /* DMA */ 1281 memory_region_init_io(&m->dmamem, NULL, &next_dma_ops, machine, 1282 "next.dma", 0x5000); 1283 memory_region_add_subregion(sysmem, 0x02000000, &m->dmamem); 1284 } 1285 1286 static void next_machine_class_init(ObjectClass *oc, void *data) 1287 { 1288 MachineClass *mc = MACHINE_CLASS(oc); 1289 1290 mc->desc = "NeXT Cube"; 1291 mc->init = next_cube_init; 1292 mc->block_default_type = IF_SCSI; 1293 mc->default_ram_size = RAM_SIZE; 1294 mc->default_ram_id = "next.ram"; 1295 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); 1296 mc->no_cdrom = true; 1297 } 1298 1299 static const TypeInfo next_typeinfo = { 1300 .name = TYPE_NEXT_MACHINE, 1301 .parent = TYPE_MACHINE, 1302 .class_init = next_machine_class_init, 1303 .instance_size = sizeof(NeXTState), 1304 }; 1305 1306 static void next_register_type(void) 1307 { 1308 type_register_static(&next_typeinfo); 1309 type_register_static(&next_pc_info); 1310 type_register_static(&next_scsi_info); 1311 } 1312 1313 type_init(next_register_type) 1314