1 /* 2 * NeXT Cube System Driver 3 * 4 * Copyright (c) 2011 Bryce Lanham 5 * 6 * This code is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published 8 * by the Free Software Foundation; either version 2 of the License, 9 * or (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "exec/hwaddr.h" 14 #include "system/system.h" 15 #include "system/qtest.h" 16 #include "hw/irq.h" 17 #include "hw/m68k/next-cube.h" 18 #include "hw/boards.h" 19 #include "hw/loader.h" 20 #include "hw/scsi/esp.h" 21 #include "hw/sysbus.h" 22 #include "qom/object.h" 23 #include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */ 24 #include "hw/block/fdc.h" 25 #include "hw/misc/empty_slot.h" 26 #include "hw/qdev-properties.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "ui/console.h" 30 #include "target/m68k/cpu.h" 31 #include "migration/vmstate.h" 32 33 /* #define DEBUG_NEXT */ 34 #ifdef DEBUG_NEXT 35 #define DPRINTF(fmt, ...) \ 36 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0) 37 #else 38 #define DPRINTF(fmt, ...) do { } while (0) 39 #endif 40 41 #define ENTRY 0x0100001e 42 #define RAM_SIZE 0x4000000 43 #define ROM_FILE "Rev_2.5_v66.bin" 44 45 typedef struct NeXTRTC { 46 int8_t phase; 47 uint8_t ram[32]; 48 uint8_t command; 49 uint8_t value; 50 uint8_t status; 51 uint8_t control; 52 uint8_t retval; 53 } NeXTRTC; 54 55 #define TYPE_NEXT_SCSI "next-scsi" 56 OBJECT_DECLARE_SIMPLE_TYPE(NeXTSCSI, NEXT_SCSI) 57 58 /* NeXT SCSI Controller */ 59 struct NeXTSCSI { 60 SysBusDevice parent_obj; 61 62 MemoryRegion scsi_mem; 63 64 SysBusESPState sysbus_esp; 65 66 MemoryRegion scsi_csr_mem; 67 uint8_t scsi_csr_1; 68 uint8_t scsi_csr_2; 69 }; 70 71 #define TYPE_NEXT_PC "next-pc" 72 OBJECT_DECLARE_SIMPLE_TYPE(NeXTPC, NEXT_PC) 73 74 /* NeXT Peripheral Controller */ 75 struct NeXTPC { 76 SysBusDevice parent_obj; 77 78 M68kCPU *cpu; 79 80 MemoryRegion floppy_mem; 81 MemoryRegion timer_mem; 82 MemoryRegion dummyen_mem; 83 MemoryRegion mmiomem; 84 MemoryRegion scrmem; 85 86 uint32_t scr1; 87 uint32_t scr2; 88 uint32_t old_scr2; 89 uint32_t int_mask; 90 uint32_t int_status; 91 uint32_t led; 92 93 NeXTSCSI next_scsi; 94 95 qemu_irq scsi_reset; 96 qemu_irq scsi_dma; 97 98 ESCCState escc; 99 100 NeXTRTC rtc; 101 qemu_irq rtc_power_irq; 102 }; 103 104 typedef struct next_dma { 105 uint32_t csr; 106 107 uint32_t saved_next; 108 uint32_t saved_limit; 109 uint32_t saved_start; 110 uint32_t saved_stop; 111 112 uint32_t next; 113 uint32_t limit; 114 uint32_t start; 115 uint32_t stop; 116 117 uint32_t next_initbuf; 118 uint32_t size; 119 } next_dma; 120 121 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube") 122 OBJECT_DECLARE_SIMPLE_TYPE(NeXTState, NEXT_MACHINE) 123 124 struct NeXTState { 125 MachineState parent; 126 127 MemoryRegion rom; 128 MemoryRegion rom2; 129 MemoryRegion dmamem; 130 MemoryRegion bmapm1; 131 MemoryRegion bmapm2; 132 133 next_dma dma[10]; 134 }; 135 136 /* Thanks to NeXT forums for this */ 137 /* 138 static const uint8_t rtc_ram3[32] = { 139 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 140 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00, 141 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00, 142 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13 143 }; 144 */ 145 static const uint8_t rtc_ram2[32] = { 146 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00, 147 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00, 148 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 149 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e, 150 }; 151 152 #define SCR2_RTCLK 0x2 153 #define SCR2_RTDATA 0x4 154 #define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10)) 155 156 static void next_scr2_led_update(NeXTPC *s) 157 { 158 if (s->scr2 & 0x1) { 159 DPRINTF("fault!\n"); 160 s->led++; 161 if (s->led == 10) { 162 DPRINTF("LED flashing, possible fault!\n"); 163 s->led = 0; 164 } 165 } 166 } 167 168 static bool next_rtc_cmd_is_write(uint8_t cmd) 169 { 170 return (cmd >= 0x80 && cmd <= 0x9f) || 171 (cmd == 0xb1); 172 } 173 174 static void next_rtc_data_in_irq(void *opaque, int n, int level) 175 { 176 NeXTPC *s = NEXT_PC(opaque); 177 NeXTRTC *rtc = &s->rtc; 178 179 if (rtc->phase < 8) { 180 rtc->command = (rtc->command << 1) | level; 181 182 if (rtc->phase == 7 && !next_rtc_cmd_is_write(rtc->command)) { 183 if (rtc->command <= 0x1f) { 184 /* RAM registers */ 185 rtc->retval = rtc->ram[rtc->command]; 186 } 187 if ((rtc->command >= 0x20) && (rtc->command <= 0x2f)) { 188 /* RTC */ 189 time_t time_h = time(NULL); 190 struct tm *info = localtime(&time_h); 191 rtc->retval = 0; 192 193 switch (rtc->command) { 194 case 0x20: 195 rtc->retval = SCR2_TOBCD(info->tm_sec); 196 break; 197 case 0x21: 198 rtc->retval = SCR2_TOBCD(info->tm_min); 199 break; 200 case 0x22: 201 rtc->retval = SCR2_TOBCD(info->tm_hour); 202 break; 203 case 0x24: 204 rtc->retval = SCR2_TOBCD(info->tm_mday); 205 break; 206 case 0x25: 207 rtc->retval = SCR2_TOBCD((info->tm_mon + 1)); 208 break; 209 case 0x26: 210 rtc->retval = SCR2_TOBCD((info->tm_year - 100)); 211 break; 212 } 213 } 214 if (rtc->command == 0x30) { 215 /* read the status 0x30 */ 216 rtc->retval = rtc->status; 217 } 218 if (rtc->command == 0x31) { 219 /* read the control 0x31 */ 220 rtc->retval = rtc->control; 221 } 222 } 223 } 224 if (rtc->phase >= 8 && rtc->phase < 16) { 225 if (next_rtc_cmd_is_write(rtc->command)) { 226 /* Shift in value to write */ 227 rtc->value = (rtc->value << 1) | level; 228 } else { 229 /* Shift out value to read */ 230 qemu_irq rtc_data_in_irq = qdev_get_gpio_in_named( 231 DEVICE(s), "pc-rtc-data-in", 0); 232 233 if (rtc->retval & (0x80 >> (rtc->phase - 8))) { 234 qemu_irq_raise(rtc_data_in_irq); 235 } else { 236 qemu_irq_lower(rtc_data_in_irq); 237 } 238 } 239 } 240 241 rtc->phase++; 242 if (rtc->phase == 16 && next_rtc_cmd_is_write(rtc->command)) { 243 if (rtc->command >= 0x80 && rtc->command <= 0x9f) { 244 /* RAM registers */ 245 rtc->ram[rtc->command - 0x80] = rtc->value; 246 } 247 if (rtc->command == 0xb1) { 248 /* write to 0x30 register */ 249 if (rtc->value & 0x04) { 250 /* clear FTU */ 251 rtc->status = rtc->status & (~0x18); 252 qemu_irq_lower(s->rtc_power_irq); 253 } 254 } 255 } 256 } 257 258 static void next_scr2_rtc_update(NeXTPC *s) 259 { 260 uint8_t old_scr2, scr2_2; 261 NeXTRTC *rtc = &s->rtc; 262 263 old_scr2 = extract32(s->old_scr2, 8, 8); 264 scr2_2 = extract32(s->scr2, 8, 8); 265 266 if (scr2_2 & 0x1) { 267 /* DPRINTF("RTC %x phase %i\n", scr2_2, rtc->phase); */ 268 /* If we are in going down clock... do something */ 269 if (((old_scr2 & SCR2_RTCLK) != (scr2_2 & SCR2_RTCLK)) && 270 ((scr2_2 & SCR2_RTCLK) == 0)) { 271 qemu_irq rtc_data_in_irq = qdev_get_gpio_in_named( 272 DEVICE(s), "rtc-data-in", 0); 273 274 if (scr2_2 & SCR2_RTDATA) { 275 qemu_irq_raise(rtc_data_in_irq); 276 } else { 277 qemu_irq_lower(rtc_data_in_irq); 278 } 279 } 280 } else { 281 /* else end or abort */ 282 rtc->phase = 0; 283 rtc->command = 0; 284 rtc->value = 0; 285 } 286 } 287 288 static uint64_t next_mmio_read(void *opaque, hwaddr addr, unsigned size) 289 { 290 NeXTPC *s = NEXT_PC(opaque); 291 uint64_t val; 292 293 switch (addr) { 294 case 0x2000: /* 0x2007000 */ 295 /* DPRINTF("Read INT status: %x\n", s->int_status); */ 296 val = s->int_status; 297 break; 298 299 case 0x2800: /* 0x2007800 */ 300 DPRINTF("MMIO Read INT mask: %x\n", s->int_mask); 301 val = s->int_mask; 302 break; 303 304 case 0x7000 ... 0x7003: /* 0x200c000 */ 305 val = extract32(s->scr1, (4 - (addr - 0x7000) - size) << 3, 306 size << 3); 307 break; 308 309 case 0x8000 ... 0x8003: /* 0x200d000 */ 310 val = extract32(s->scr2, (4 - (addr - 0x8000) - size) << 3, 311 size << 3); 312 break; 313 314 default: 315 val = 0; 316 DPRINTF("MMIO Read @ 0x%"HWADDR_PRIx" size %d\n", addr, size); 317 break; 318 } 319 320 return val; 321 } 322 323 static void next_mmio_write(void *opaque, hwaddr addr, uint64_t val, 324 unsigned size) 325 { 326 NeXTPC *s = NEXT_PC(opaque); 327 328 switch (addr) { 329 case 0x2000: /* 0x2007000 */ 330 DPRINTF("INT Status old: %x new: %x\n", s->int_status, 331 (unsigned int)val); 332 s->int_status = val; 333 break; 334 335 case 0x2800: /* 0x2007800 */ 336 DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, (unsigned int)val); 337 s->int_mask = val; 338 break; 339 340 case 0x7000 ... 0x7003: /* 0x200c000 */ 341 DPRINTF("SCR1 Write: %x\n", (unsigned int)val); 342 s->scr1 = deposit32(s->scr1, (4 - (addr - 0x7000) - size) << 3, 343 size << 3, val); 344 break; 345 346 case 0x8000 ... 0x8003: /* 0x200d000 */ 347 s->scr2 = deposit32(s->scr2, (4 - (addr - 0x8000) - size) << 3, 348 size << 3, val); 349 next_scr2_led_update(s); 350 next_scr2_rtc_update(s); 351 s->old_scr2 = s->scr2; 352 break; 353 354 default: 355 DPRINTF("MMIO Write @ 0x%"HWADDR_PRIx " with 0x%x size %u\n", addr, 356 (unsigned int)val, size); 357 } 358 } 359 360 static const MemoryRegionOps next_mmio_ops = { 361 .read = next_mmio_read, 362 .write = next_mmio_write, 363 .valid.min_access_size = 1, 364 .valid.max_access_size = 4, 365 .endianness = DEVICE_BIG_ENDIAN, 366 }; 367 368 #define SCSICSR_ENABLE 0x01 369 #define SCSICSR_RESET 0x02 /* reset scsi dma */ 370 #define SCSICSR_FIFOFL 0x04 371 #define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */ 372 #define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */ 373 #define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */ 374 375 #define NEXTDMA_SCSI(x) (0x10 + x) 376 #define NEXTDMA_FD(x) (0x10 + x) 377 #define NEXTDMA_ENTX(x) (0x110 + x) 378 #define NEXTDMA_ENRX(x) (0x150 + x) 379 #define NEXTDMA_CSR 0x0 380 #define NEXTDMA_NEXT 0x4000 381 #define NEXTDMA_LIMIT 0x4004 382 #define NEXTDMA_START 0x4008 383 #define NEXTDMA_STOP 0x400c 384 #define NEXTDMA_NEXT_INIT 0x4200 385 #define NEXTDMA_SIZE 0x4204 386 387 static void next_dma_write(void *opaque, hwaddr addr, uint64_t val, 388 unsigned int size) 389 { 390 NeXTState *next_state = NEXT_MACHINE(opaque); 391 392 switch (addr) { 393 case NEXTDMA_ENRX(NEXTDMA_CSR): 394 if (val & DMA_DEV2M) { 395 next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M; 396 } 397 398 if (val & DMA_SETENABLE) { 399 /* DPRINTF("SCSI DMA ENABLE\n"); */ 400 next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE; 401 } 402 if (val & DMA_SETSUPDATE) { 403 next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE; 404 } 405 if (val & DMA_CLRCOMPLETE) { 406 next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE; 407 } 408 409 if (val & DMA_RESET) { 410 next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 411 DMA_ENABLE | DMA_DEV2M); 412 } 413 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 414 break; 415 416 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 417 next_state->dma[NEXTDMA_ENRX].next_initbuf = val; 418 break; 419 420 case NEXTDMA_ENRX(NEXTDMA_NEXT): 421 next_state->dma[NEXTDMA_ENRX].next = val; 422 break; 423 424 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 425 next_state->dma[NEXTDMA_ENRX].limit = val; 426 break; 427 428 case NEXTDMA_SCSI(NEXTDMA_CSR): 429 if (val & DMA_DEV2M) { 430 next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M; 431 } 432 if (val & DMA_SETENABLE) { 433 /* DPRINTF("SCSI DMA ENABLE\n"); */ 434 next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE; 435 } 436 if (val & DMA_SETSUPDATE) { 437 next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE; 438 } 439 if (val & DMA_CLRCOMPLETE) { 440 next_state->dma[NEXTDMA_SCSI].csr &= ~DMA_COMPLETE; 441 } 442 443 if (val & DMA_RESET) { 444 next_state->dma[NEXTDMA_SCSI].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 445 DMA_ENABLE | DMA_DEV2M); 446 /* DPRINTF("SCSI DMA RESET\n"); */ 447 } 448 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 449 break; 450 451 case NEXTDMA_SCSI(NEXTDMA_NEXT): 452 next_state->dma[NEXTDMA_SCSI].next = val; 453 break; 454 455 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 456 next_state->dma[NEXTDMA_SCSI].limit = val; 457 break; 458 459 case NEXTDMA_SCSI(NEXTDMA_START): 460 next_state->dma[NEXTDMA_SCSI].start = val; 461 break; 462 463 case NEXTDMA_SCSI(NEXTDMA_STOP): 464 next_state->dma[NEXTDMA_SCSI].stop = val; 465 break; 466 467 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 468 next_state->dma[NEXTDMA_SCSI].next_initbuf = val; 469 break; 470 471 default: 472 DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)val); 473 } 474 } 475 476 static uint64_t next_dma_read(void *opaque, hwaddr addr, unsigned int size) 477 { 478 NeXTState *next_state = NEXT_MACHINE(opaque); 479 uint64_t val; 480 481 switch (addr) { 482 case NEXTDMA_SCSI(NEXTDMA_CSR): 483 DPRINTF("SCSI DMA CSR READ\n"); 484 val = next_state->dma[NEXTDMA_SCSI].csr; 485 break; 486 487 case NEXTDMA_ENRX(NEXTDMA_CSR): 488 val = next_state->dma[NEXTDMA_ENRX].csr; 489 break; 490 491 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 492 val = next_state->dma[NEXTDMA_ENRX].next_initbuf; 493 break; 494 495 case NEXTDMA_ENRX(NEXTDMA_NEXT): 496 val = next_state->dma[NEXTDMA_ENRX].next; 497 break; 498 499 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 500 val = next_state->dma[NEXTDMA_ENRX].limit; 501 break; 502 503 case NEXTDMA_SCSI(NEXTDMA_NEXT): 504 val = next_state->dma[NEXTDMA_SCSI].next; 505 break; 506 507 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 508 val = next_state->dma[NEXTDMA_SCSI].next_initbuf; 509 break; 510 511 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 512 val = next_state->dma[NEXTDMA_SCSI].limit; 513 break; 514 515 case NEXTDMA_SCSI(NEXTDMA_START): 516 val = next_state->dma[NEXTDMA_SCSI].start; 517 break; 518 519 case NEXTDMA_SCSI(NEXTDMA_STOP): 520 val = next_state->dma[NEXTDMA_SCSI].stop; 521 break; 522 523 default: 524 DPRINTF("DMA read @ %x\n", (unsigned int)addr); 525 val = 0; 526 } 527 528 /* 529 * once the csr's are done, subtract 0x3FEC from the addr, and that will 530 * normalize the upper registers 531 */ 532 533 return val; 534 } 535 536 static const MemoryRegionOps next_dma_ops = { 537 .read = next_dma_read, 538 .write = next_dma_write, 539 .impl.min_access_size = 4, 540 .valid.min_access_size = 4, 541 .valid.max_access_size = 4, 542 .endianness = DEVICE_BIG_ENDIAN, 543 }; 544 545 static void next_irq(void *opaque, int number, int level) 546 { 547 NeXTPC *s = NEXT_PC(opaque); 548 M68kCPU *cpu = s->cpu; 549 int shift = 0; 550 551 /* first switch sets interrupt status */ 552 /* DPRINTF("IRQ %i\n",number); */ 553 switch (number) { 554 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 555 case NEXT_FD_I: 556 shift = 7; 557 break; 558 case NEXT_KBD_I: 559 shift = 3; 560 break; 561 case NEXT_PWR_I: 562 shift = 2; 563 break; 564 case NEXT_ENRX_I: 565 shift = 9; 566 break; 567 case NEXT_ENTX_I: 568 shift = 10; 569 break; 570 case NEXT_SCSI_I: 571 shift = 12; 572 break; 573 case NEXT_CLK_I: 574 shift = 5; 575 break; 576 577 /* level 5 - scc (serial) */ 578 case NEXT_SCC_I: 579 shift = 17; 580 break; 581 582 /* level 6 - audio etherrx/tx dma */ 583 case NEXT_ENTX_DMA_I: 584 shift = 28; 585 break; 586 case NEXT_ENRX_DMA_I: 587 shift = 27; 588 break; 589 case NEXT_SCSI_DMA_I: 590 shift = 26; 591 break; 592 case NEXT_SND_I: 593 shift = 23; 594 break; 595 case NEXT_SCC_DMA_I: 596 shift = 21; 597 break; 598 599 } 600 /* 601 * this HAS to be wrong, the interrupt handlers in mach and together 602 * int_status and int_mask and return if there is a hit 603 */ 604 if (s->int_mask & (1 << shift)) { 605 DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc); 606 /* return; */ 607 } 608 609 /* second switch triggers the correct interrupt */ 610 if (level) { 611 s->int_status |= 1 << shift; 612 613 switch (number) { 614 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 615 case NEXT_FD_I: 616 case NEXT_KBD_I: 617 case NEXT_PWR_I: 618 case NEXT_ENRX_I: 619 case NEXT_ENTX_I: 620 case NEXT_SCSI_I: 621 case NEXT_CLK_I: 622 m68k_set_irq_level(cpu, 3, 27); 623 break; 624 625 /* level 5 - scc (serial) */ 626 case NEXT_SCC_I: 627 m68k_set_irq_level(cpu, 5, 29); 628 break; 629 630 /* level 6 - audio etherrx/tx dma */ 631 case NEXT_ENTX_DMA_I: 632 case NEXT_ENRX_DMA_I: 633 case NEXT_SCSI_DMA_I: 634 case NEXT_SND_I: 635 case NEXT_SCC_DMA_I: 636 m68k_set_irq_level(cpu, 6, 30); 637 break; 638 } 639 } else { 640 s->int_status &= ~(1 << shift); 641 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); 642 } 643 } 644 645 static void nextdma_write(void *opaque, uint8_t *buf, int size, int type) 646 { 647 uint32_t base_addr; 648 int irq = 0; 649 uint8_t align = 16; 650 NeXTState *next_state = NEXT_MACHINE(qdev_get_machine()); 651 652 if (type == NEXTDMA_ENRX || type == NEXTDMA_ENTX) { 653 align = 32; 654 } 655 /* Most DMA is supposedly 16 byte aligned */ 656 if ((size % align) != 0) { 657 size -= size % align; 658 size += align; 659 } 660 661 /* 662 * prom sets the dma start using initbuf while the bootloader uses next 663 * so we check to see if initbuf is 0 664 */ 665 if (next_state->dma[type].next_initbuf == 0) { 666 base_addr = next_state->dma[type].next; 667 } else { 668 base_addr = next_state->dma[type].next_initbuf; 669 } 670 671 cpu_physical_memory_write(base_addr, buf, size); 672 673 next_state->dma[type].next_initbuf = 0; 674 675 /* saved limit is checked to calculate packet size by both, rom and netbsd */ 676 next_state->dma[type].saved_limit = (next_state->dma[type].next + size); 677 next_state->dma[type].saved_next = (next_state->dma[type].next); 678 679 /* 680 * 32 bytes under savedbase seems to be some kind of register 681 * of which the purpose is unknown as of yet 682 */ 683 /* stl_phys(s->rx_dma.base-32,0xFFFFFFFF); */ 684 685 if (!(next_state->dma[type].csr & DMA_SUPDATE)) { 686 next_state->dma[type].next = next_state->dma[type].start; 687 next_state->dma[type].limit = next_state->dma[type].stop; 688 } 689 690 /* Set dma registers and raise an irq */ 691 next_state->dma[type].csr |= DMA_COMPLETE; /* DON'T CHANGE THIS! */ 692 693 switch (type) { 694 case NEXTDMA_SCSI: 695 irq = NEXT_SCSI_DMA_I; 696 break; 697 } 698 699 next_irq(opaque, irq, 1); 700 next_irq(opaque, irq, 0); 701 } 702 703 static void nextscsi_read(void *opaque, uint8_t *buf, int len) 704 { 705 DPRINTF("SCSI READ: %x\n", len); 706 abort(); 707 } 708 709 static void nextscsi_write(void *opaque, uint8_t *buf, int size) 710 { 711 DPRINTF("SCSI WRITE: %i\n", size); 712 nextdma_write(opaque, buf, size, NEXTDMA_SCSI); 713 } 714 715 static void next_scsi_csr_write(void *opaque, hwaddr addr, uint64_t val, 716 unsigned size) 717 { 718 NeXTSCSI *s = NEXT_SCSI(opaque); 719 NeXTPC *pc = NEXT_PC(container_of(s, NeXTPC, next_scsi)); 720 721 switch (addr) { 722 case 0: 723 if (val & SCSICSR_FIFOFL) { 724 DPRINTF("SCSICSR FIFO Flush\n"); 725 /* will have to add another irq to the esp if this is needed */ 726 /* esp_puflush_fifo(esp_g); */ 727 } 728 729 if (val & SCSICSR_ENABLE) { 730 DPRINTF("SCSICSR Enable\n"); 731 /* 732 * qemu_irq_raise(s->scsi_dma); 733 * s->scsi_csr_1 = 0xc0; 734 * s->scsi_csr_1 |= 0x1; 735 * qemu_irq_pulse(s->scsi_dma); 736 */ 737 } 738 /* 739 * else 740 * s->scsi_csr_1 &= ~SCSICSR_ENABLE; 741 */ 742 743 if (val & SCSICSR_RESET) { 744 DPRINTF("SCSICSR Reset\n"); 745 /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */ 746 qemu_irq_raise(pc->scsi_reset); 747 s->scsi_csr_1 &= ~(SCSICSR_INTMASK | 0x80 | 0x1); 748 qemu_irq_lower(pc->scsi_reset); 749 } 750 if (val & SCSICSR_DMADIR) { 751 DPRINTF("SCSICSR DMAdir\n"); 752 } 753 if (val & SCSICSR_CPUDMA) { 754 DPRINTF("SCSICSR CPUDMA\n"); 755 /* qemu_irq_raise(s->scsi_dma); */ 756 pc->int_status |= 0x4000000; 757 } else { 758 /* fprintf(stderr,"SCSICSR CPUDMA disabled\n"); */ 759 pc->int_status &= ~(0x4000000); 760 /* qemu_irq_lower(s->scsi_dma); */ 761 } 762 if (val & SCSICSR_INTMASK) { 763 DPRINTF("SCSICSR INTMASK\n"); 764 /* 765 * int_mask &= ~0x1000; 766 * s->scsi_csr_1 |= val; 767 * s->scsi_csr_1 &= ~SCSICSR_INTMASK; 768 * if (s->scsi_queued) { 769 * s->scsi_queued = 0; 770 * next_irq(s, NEXT_SCSI_I, level); 771 * } 772 */ 773 } else { 774 /* int_mask |= 0x1000; */ 775 } 776 if (val & 0x80) { 777 /* int_mask |= 0x1000; */ 778 /* s->scsi_csr_1 |= 0x80; */ 779 } 780 DPRINTF("SCSICSR1 Write: %"PRIx64 "\n", val); 781 s->scsi_csr_1 = val; 782 break; 783 784 case 1: 785 DPRINTF("SCSICSR2 Write: %"PRIx64 "\n", val); 786 s->scsi_csr_2 = val; 787 break; 788 789 default: 790 g_assert_not_reached(); 791 } 792 } 793 794 static uint64_t next_scsi_csr_read(void *opaque, hwaddr addr, unsigned size) 795 { 796 NeXTSCSI *s = NEXT_SCSI(opaque); 797 uint64_t val; 798 799 switch (addr) { 800 case 0: 801 DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1); 802 val = s->scsi_csr_1; 803 break; 804 805 case 1: 806 DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2); 807 val = s->scsi_csr_2; 808 break; 809 810 default: 811 g_assert_not_reached(); 812 } 813 814 return val; 815 } 816 817 static const MemoryRegionOps next_scsi_csr_ops = { 818 .read = next_scsi_csr_read, 819 .write = next_scsi_csr_write, 820 .valid.min_access_size = 1, 821 .valid.max_access_size = 1, 822 .endianness = DEVICE_BIG_ENDIAN, 823 }; 824 825 static void next_scsi_init(Object *obj) 826 { 827 NeXTSCSI *s = NEXT_SCSI(obj); 828 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 829 830 object_initialize_child(obj, "esp", &s->sysbus_esp, TYPE_SYSBUS_ESP); 831 832 memory_region_init_io(&s->scsi_csr_mem, obj, &next_scsi_csr_ops, 833 s, "csrs", 2); 834 835 memory_region_init(&s->scsi_mem, obj, "next.scsi", 0x40); 836 sysbus_init_mmio(sbd, &s->scsi_mem); 837 } 838 839 static void next_scsi_realize(DeviceState *dev, Error **errp) 840 { 841 NeXTSCSI *s = NEXT_SCSI(dev); 842 SysBusESPState *sysbus_esp; 843 SysBusDevice *sbd; 844 ESPState *esp; 845 NeXTPC *pcdev; 846 847 pcdev = NEXT_PC(container_of(s, NeXTPC, next_scsi)); 848 849 /* ESP */ 850 sysbus_esp = SYSBUS_ESP(&s->sysbus_esp); 851 esp = &sysbus_esp->esp; 852 esp->dma_memory_read = nextscsi_read; 853 esp->dma_memory_write = nextscsi_write; 854 esp->dma_opaque = pcdev; 855 sysbus_esp->it_shift = 0; 856 esp->dma_enabled = 1; 857 sbd = SYS_BUS_DEVICE(sysbus_esp); 858 if (!sysbus_realize(sbd, errp)) { 859 return; 860 } 861 memory_region_add_subregion(&s->scsi_mem, 0x0, 862 sysbus_mmio_get_region(sbd, 0)); 863 864 /* SCSI CSRs */ 865 memory_region_add_subregion(&s->scsi_mem, 0x20, &s->scsi_csr_mem); 866 867 scsi_bus_legacy_handle_cmdline(&s->sysbus_esp.esp.bus); 868 } 869 870 static const VMStateDescription next_scsi_vmstate = { 871 .name = "next-scsi", 872 .version_id = 0, 873 .minimum_version_id = 0, 874 .fields = (const VMStateField[]) { 875 VMSTATE_UINT8(scsi_csr_1, NeXTSCSI), 876 VMSTATE_UINT8(scsi_csr_2, NeXTSCSI), 877 VMSTATE_END_OF_LIST() 878 }, 879 }; 880 881 static void next_scsi_class_init(ObjectClass *klass, void *data) 882 { 883 DeviceClass *dc = DEVICE_CLASS(klass); 884 885 dc->desc = "NeXT SCSI Controller"; 886 dc->realize = next_scsi_realize; 887 dc->vmsd = &next_scsi_vmstate; 888 } 889 890 static const TypeInfo next_scsi_info = { 891 .name = TYPE_NEXT_SCSI, 892 .parent = TYPE_SYS_BUS_DEVICE, 893 .instance_init = next_scsi_init, 894 .instance_size = sizeof(NeXTSCSI), 895 .class_init = next_scsi_class_init, 896 }; 897 898 static void next_floppy_write(void *opaque, hwaddr addr, uint64_t val, 899 unsigned size) 900 { 901 switch (addr) { 902 case 0: 903 DPRINTF("FDCSR Write: %"PRIx64 "\n", val); 904 if (val == 0x0) { 905 /* qemu_irq_raise(s->fd_irq[0]); */ 906 } 907 break; 908 909 default: 910 g_assert_not_reached(); 911 } 912 } 913 914 static uint64_t next_floppy_read(void *opaque, hwaddr addr, unsigned size) 915 { 916 uint64_t val; 917 918 switch (addr) { 919 case 0: 920 DPRINTF("FD read @ %x\n", (unsigned int)addr); 921 val = 0x40 | 0x04 | 0x2 | 0x1; 922 break; 923 924 default: 925 g_assert_not_reached(); 926 } 927 928 return val; 929 } 930 931 static const MemoryRegionOps next_floppy_ops = { 932 .read = next_floppy_read, 933 .write = next_floppy_write, 934 .valid.min_access_size = 1, 935 .valid.max_access_size = 4, 936 .endianness = DEVICE_BIG_ENDIAN, 937 }; 938 939 static void next_timer_write(void *opaque, hwaddr addr, uint64_t val, 940 unsigned size) 941 { 942 switch (addr) { 943 case 0 ... 3: 944 /* Hardware timer latch - not implemented yet */ 945 break; 946 947 default: 948 g_assert_not_reached(); 949 } 950 } 951 952 static uint64_t next_timer_read(void *opaque, hwaddr addr, unsigned size) 953 { 954 uint64_t val; 955 956 switch (addr) { 957 case 0 ... 3: 958 /* 959 * These 4 registers are the hardware timer, not sure which register 960 * is the latch instead of data, but no problems so far. 961 * 962 * Hack: We need to have the LSB change consistently to make it work 963 */ 964 val = extract32(clock(), (4 - addr - size) << 3, 965 size << 3); 966 break; 967 968 default: 969 g_assert_not_reached(); 970 } 971 972 return val; 973 } 974 975 static const MemoryRegionOps next_timer_ops = { 976 .read = next_timer_read, 977 .write = next_timer_write, 978 .valid.min_access_size = 1, 979 .valid.max_access_size = 4, 980 .endianness = DEVICE_BIG_ENDIAN, 981 }; 982 983 static void next_dummy_en_write(void *opaque, hwaddr addr, uint64_t val, 984 unsigned size) 985 { 986 /* Do nothing */ 987 return; 988 } 989 990 static uint64_t next_dummy_en_read(void *opaque, hwaddr addr, unsigned size) 991 { 992 uint64_t val; 993 994 switch (addr) { 995 case 0: 996 /* For now return dummy byte to allow the Ethernet test to timeout */ 997 val = 0xff; 998 break; 999 1000 default: 1001 val = 0; 1002 } 1003 1004 return val; 1005 } 1006 1007 static const MemoryRegionOps next_dummy_en_ops = { 1008 .read = next_dummy_en_read, 1009 .write = next_dummy_en_write, 1010 .valid.min_access_size = 1, 1011 .valid.max_access_size = 4, 1012 .endianness = DEVICE_BIG_ENDIAN, 1013 }; 1014 1015 static void next_pc_rtc_data_in_irq(void *opaque, int n, int level) 1016 { 1017 NeXTPC *s = NEXT_PC(opaque); 1018 uint8_t scr2_2 = extract32(s->scr2, 8, 8); 1019 1020 if (level) { 1021 scr2_2 |= SCR2_RTDATA; 1022 } else { 1023 scr2_2 &= ~SCR2_RTDATA; 1024 } 1025 1026 s->scr2 = deposit32(s->scr2, 8, 8, scr2_2); 1027 } 1028 1029 static void next_pc_reset_hold(Object *obj, ResetType type) 1030 { 1031 NeXTPC *s = NEXT_PC(obj); 1032 1033 /* Set internal registers to initial values */ 1034 /* 0x0000XX00 << vital bits */ 1035 s->scr1 = 0x00011102; 1036 s->scr2 = 0x00ff0c80; 1037 s->old_scr2 = s->scr2; 1038 1039 s->rtc.status = 0x90; 1040 1041 /* Load RTC RAM - TODO: provide possibility to load contents from file */ 1042 memcpy(s->rtc.ram, rtc_ram2, 32); 1043 } 1044 1045 static void next_pc_realize(DeviceState *dev, Error **errp) 1046 { 1047 NeXTPC *s = NEXT_PC(dev); 1048 SysBusDevice *sbd; 1049 DeviceState *d; 1050 1051 /* SCSI */ 1052 sbd = SYS_BUS_DEVICE(&s->next_scsi); 1053 if (!sysbus_realize(sbd, errp)) { 1054 return; 1055 } 1056 1057 d = DEVICE(object_resolve_path_component(OBJECT(&s->next_scsi), "esp")); 1058 sysbus_connect_irq(SYS_BUS_DEVICE(d), 0, 1059 qdev_get_gpio_in(DEVICE(s), NEXT_SCSI_I)); 1060 1061 s->scsi_reset = qdev_get_gpio_in(d, 0); 1062 s->scsi_dma = qdev_get_gpio_in(d, 1); 1063 1064 /* ESCC */ 1065 d = DEVICE(&s->escc); 1066 qdev_prop_set_uint32(d, "disabled", 0); 1067 qdev_prop_set_uint32(d, "frequency", 9600 * 384); 1068 qdev_prop_set_uint32(d, "it_shift", 0); 1069 qdev_prop_set_bit(d, "bit_swap", true); 1070 qdev_prop_set_chr(d, "chrB", serial_hd(1)); 1071 qdev_prop_set_chr(d, "chrA", serial_hd(0)); 1072 qdev_prop_set_uint32(d, "chnBtype", escc_serial); 1073 qdev_prop_set_uint32(d, "chnAtype", escc_serial); 1074 1075 sbd = SYS_BUS_DEVICE(d); 1076 if (!sysbus_realize(sbd, errp)) { 1077 return; 1078 } 1079 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(dev, NEXT_SCC_I)); 1080 sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(dev, NEXT_SCC_DMA_I)); 1081 } 1082 1083 static void next_pc_init(Object *obj) 1084 { 1085 NeXTPC *s = NEXT_PC(obj); 1086 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1087 1088 qdev_init_gpio_in(DEVICE(obj), next_irq, NEXT_NUM_IRQS); 1089 1090 memory_region_init_io(&s->mmiomem, OBJECT(s), &next_mmio_ops, s, 1091 "next.mmio", 0x9000); 1092 sysbus_init_mmio(sbd, &s->mmiomem); 1093 1094 memory_region_init_io(&s->dummyen_mem, OBJECT(s), &next_dummy_en_ops, s, 1095 "next.en", 0x20); 1096 sysbus_init_mmio(sbd, &s->dummyen_mem); 1097 1098 object_initialize_child(obj, "next-scsi", &s->next_scsi, TYPE_NEXT_SCSI); 1099 sysbus_init_mmio(sbd, 1100 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->next_scsi), 0)); 1101 1102 memory_region_init_io(&s->floppy_mem, OBJECT(s), &next_floppy_ops, s, 1103 "next.floppy", 4); 1104 sysbus_init_mmio(sbd, &s->floppy_mem); 1105 1106 object_initialize_child(obj, "escc", &s->escc, TYPE_ESCC); 1107 sysbus_init_mmio(sbd, 1108 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->escc), 0)); 1109 1110 memory_region_init_io(&s->timer_mem, OBJECT(s), &next_timer_ops, s, 1111 "next.timer", 4); 1112 sysbus_init_mmio(sbd, &s->timer_mem); 1113 1114 s->rtc_power_irq = qdev_get_gpio_in(DEVICE(obj), NEXT_PWR_I); 1115 qdev_init_gpio_in_named(DEVICE(obj), next_pc_rtc_data_in_irq, 1116 "pc-rtc-data-in", 1); 1117 qdev_init_gpio_in_named(DEVICE(obj), next_rtc_data_in_irq, 1118 "rtc-data-in", 1); 1119 } 1120 1121 /* 1122 * If the m68k CPU implemented its inbound irq lines as GPIO lines 1123 * rather than via the m68k_set_irq_level() function we would not need 1124 * this cpu link property and could instead provide outbound IRQ lines 1125 * that the board could wire up to the CPU. 1126 */ 1127 static const Property next_pc_properties[] = { 1128 DEFINE_PROP_LINK("cpu", NeXTPC, cpu, TYPE_M68K_CPU, M68kCPU *), 1129 }; 1130 1131 static const VMStateDescription next_rtc_vmstate = { 1132 .name = "next-rtc", 1133 .version_id = 2, 1134 .minimum_version_id = 2, 1135 .fields = (const VMStateField[]) { 1136 VMSTATE_INT8(phase, NeXTRTC), 1137 VMSTATE_UINT8_ARRAY(ram, NeXTRTC, 32), 1138 VMSTATE_UINT8(command, NeXTRTC), 1139 VMSTATE_UINT8(value, NeXTRTC), 1140 VMSTATE_UINT8(status, NeXTRTC), 1141 VMSTATE_UINT8(control, NeXTRTC), 1142 VMSTATE_UINT8(retval, NeXTRTC), 1143 VMSTATE_END_OF_LIST() 1144 }, 1145 }; 1146 1147 static const VMStateDescription next_pc_vmstate = { 1148 .name = "next-pc", 1149 .version_id = 3, 1150 .minimum_version_id = 3, 1151 .fields = (const VMStateField[]) { 1152 VMSTATE_UINT32(scr1, NeXTPC), 1153 VMSTATE_UINT32(scr2, NeXTPC), 1154 VMSTATE_UINT32(old_scr2, NeXTPC), 1155 VMSTATE_UINT32(int_mask, NeXTPC), 1156 VMSTATE_UINT32(int_status, NeXTPC), 1157 VMSTATE_UINT32(led, NeXTPC), 1158 VMSTATE_STRUCT(rtc, NeXTPC, 0, next_rtc_vmstate, NeXTRTC), 1159 VMSTATE_END_OF_LIST() 1160 }, 1161 }; 1162 1163 static void next_pc_class_init(ObjectClass *klass, void *data) 1164 { 1165 DeviceClass *dc = DEVICE_CLASS(klass); 1166 ResettableClass *rc = RESETTABLE_CLASS(klass); 1167 1168 dc->desc = "NeXT Peripheral Controller"; 1169 dc->realize = next_pc_realize; 1170 device_class_set_props(dc, next_pc_properties); 1171 dc->vmsd = &next_pc_vmstate; 1172 rc->phases.hold = next_pc_reset_hold; 1173 } 1174 1175 static const TypeInfo next_pc_info = { 1176 .name = TYPE_NEXT_PC, 1177 .parent = TYPE_SYS_BUS_DEVICE, 1178 .instance_init = next_pc_init, 1179 .instance_size = sizeof(NeXTPC), 1180 .class_init = next_pc_class_init, 1181 }; 1182 1183 static void next_cube_init(MachineState *machine) 1184 { 1185 NeXTState *m = NEXT_MACHINE(machine); 1186 M68kCPU *cpu; 1187 CPUM68KState *env; 1188 MemoryRegion *sysmem = get_system_memory(); 1189 const char *bios_name = machine->firmware ?: ROM_FILE; 1190 DeviceState *pcdev; 1191 1192 /* Initialize the cpu core */ 1193 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 1194 if (!cpu) { 1195 error_report("Unable to find m68k CPU definition"); 1196 exit(1); 1197 } 1198 env = &cpu->env; 1199 1200 /* Initialize CPU registers. */ 1201 env->vbr = 0; 1202 env->sr = 0x2700; 1203 1204 /* Peripheral Controller */ 1205 pcdev = qdev_new(TYPE_NEXT_PC); 1206 object_property_set_link(OBJECT(pcdev), "cpu", OBJECT(cpu), &error_abort); 1207 sysbus_realize_and_unref(SYS_BUS_DEVICE(pcdev), &error_fatal); 1208 1209 /* 64MB RAM starting at 0x04000000 */ 1210 memory_region_add_subregion(sysmem, 0x04000000, machine->ram); 1211 1212 /* Framebuffer */ 1213 sysbus_create_simple(TYPE_NEXTFB, 0x0B000000, NULL); 1214 1215 /* MMIO */ 1216 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02005000); 1217 1218 /* BMAP IO - acts as a catch-all for now */ 1219 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02100000); 1220 1221 /* en network (dummy) */ 1222 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02106000); 1223 1224 /* unknown: Brightness control register? */ 1225 empty_slot_init("next.unknown.0", 0x02110000, 0x10); 1226 /* unknown: Magneto-Optical drive controller? */ 1227 empty_slot_init("next.unknown.1", 0x02112000, 0x10); 1228 1229 /* SCSI */ 1230 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 2, 0x02114000); 1231 /* Floppy */ 1232 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 3, 0x02114108); 1233 /* ESCC */ 1234 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 4, 0x02118000); 1235 1236 /* unknown: Serial clock configuration register? */ 1237 empty_slot_init("next.unknown.2", 0x02118004, 0x10); 1238 1239 /* Timer */ 1240 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 5, 0x0211a000); 1241 1242 /* BMAP memory */ 1243 memory_region_init_ram_flags_nomigrate(&m->bmapm1, NULL, "next.bmapmem", 1244 64, RAM_SHARED, &error_fatal); 1245 memory_region_add_subregion(sysmem, 0x020c0000, &m->bmapm1); 1246 /* The Rev_2.5_v66.bin firmware accesses it at 0x820c0020, too */ 1247 memory_region_init_alias(&m->bmapm2, NULL, "next.bmapmem2", &m->bmapm1, 1248 0x0, 64); 1249 memory_region_add_subregion(sysmem, 0x820c0000, &m->bmapm2); 1250 1251 /* KBD */ 1252 sysbus_create_simple(TYPE_NEXTKBD, 0x0200e000, NULL); 1253 1254 /* Load ROM here */ 1255 memory_region_init_rom(&m->rom, NULL, "next.rom", 0x20000, &error_fatal); 1256 memory_region_add_subregion(sysmem, 0x01000000, &m->rom); 1257 memory_region_init_alias(&m->rom2, NULL, "next.rom2", &m->rom, 0x0, 1258 0x20000); 1259 memory_region_add_subregion(sysmem, 0x0, &m->rom2); 1260 if (load_image_targphys(bios_name, 0x01000000, 0x20000) < 8) { 1261 if (!qtest_enabled()) { 1262 error_report("Failed to load firmware '%s'.", bios_name); 1263 } 1264 } else { 1265 uint8_t *ptr; 1266 /* Initial PC is always at offset 4 in firmware binaries */ 1267 ptr = rom_ptr(0x01000004, 4); 1268 g_assert(ptr != NULL); 1269 env->pc = ldl_be_p(ptr); 1270 if (env->pc >= 0x01020000) { 1271 error_report("'%s' does not seem to be a valid firmware image.", 1272 bios_name); 1273 exit(1); 1274 } 1275 } 1276 1277 /* DMA */ 1278 memory_region_init_io(&m->dmamem, NULL, &next_dma_ops, machine, 1279 "next.dma", 0x5000); 1280 memory_region_add_subregion(sysmem, 0x02000000, &m->dmamem); 1281 } 1282 1283 static void next_machine_class_init(ObjectClass *oc, void *data) 1284 { 1285 MachineClass *mc = MACHINE_CLASS(oc); 1286 1287 mc->desc = "NeXT Cube"; 1288 mc->init = next_cube_init; 1289 mc->block_default_type = IF_SCSI; 1290 mc->default_ram_size = RAM_SIZE; 1291 mc->default_ram_id = "next.ram"; 1292 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); 1293 mc->no_cdrom = true; 1294 } 1295 1296 static const TypeInfo next_typeinfo = { 1297 .name = TYPE_NEXT_MACHINE, 1298 .parent = TYPE_MACHINE, 1299 .class_init = next_machine_class_init, 1300 .instance_size = sizeof(NeXTState), 1301 }; 1302 1303 static void next_register_type(void) 1304 { 1305 type_register_static(&next_typeinfo); 1306 type_register_static(&next_pc_info); 1307 type_register_static(&next_scsi_info); 1308 } 1309 1310 type_init(next_register_type) 1311