1 /* 2 * NeXT Cube System Driver 3 * 4 * Copyright (c) 2011 Bryce Lanham 5 * 6 * This code is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published 8 * by the Free Software Foundation; either version 2 of the License, 9 * or (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "exec/hwaddr.h" 14 #include "system/system.h" 15 #include "system/qtest.h" 16 #include "hw/irq.h" 17 #include "hw/m68k/next-cube.h" 18 #include "hw/boards.h" 19 #include "hw/loader.h" 20 #include "hw/scsi/esp.h" 21 #include "hw/sysbus.h" 22 #include "qom/object.h" 23 #include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */ 24 #include "hw/block/fdc.h" 25 #include "hw/misc/empty_slot.h" 26 #include "hw/qdev-properties.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "ui/console.h" 30 #include "target/m68k/cpu.h" 31 #include "migration/vmstate.h" 32 33 /* #define DEBUG_NEXT */ 34 #ifdef DEBUG_NEXT 35 #define DPRINTF(fmt, ...) \ 36 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0) 37 #else 38 #define DPRINTF(fmt, ...) do { } while (0) 39 #endif 40 41 #define ENTRY 0x0100001e 42 #define RAM_SIZE 0x4000000 43 #define ROM_FILE "Rev_2.5_v66.bin" 44 45 46 #define TYPE_NEXT_RTC "next-rtc" 47 OBJECT_DECLARE_SIMPLE_TYPE(NeXTRTC, NEXT_RTC) 48 49 struct NeXTRTC { 50 SysBusDevice parent_obj; 51 52 int8_t phase; 53 uint8_t ram[32]; 54 uint8_t command; 55 uint8_t value; 56 uint8_t status; 57 uint8_t control; 58 uint8_t retval; 59 }; 60 61 #define TYPE_NEXT_SCSI "next-scsi" 62 OBJECT_DECLARE_SIMPLE_TYPE(NeXTSCSI, NEXT_SCSI) 63 64 /* NeXT SCSI Controller */ 65 struct NeXTSCSI { 66 SysBusDevice parent_obj; 67 68 MemoryRegion scsi_mem; 69 70 SysBusESPState sysbus_esp; 71 72 MemoryRegion scsi_csr_mem; 73 uint8_t scsi_csr_1; 74 uint8_t scsi_csr_2; 75 }; 76 77 #define TYPE_NEXT_PC "next-pc" 78 OBJECT_DECLARE_SIMPLE_TYPE(NeXTPC, NEXT_PC) 79 80 /* NeXT Peripheral Controller */ 81 struct NeXTPC { 82 SysBusDevice parent_obj; 83 84 M68kCPU *cpu; 85 86 MemoryRegion floppy_mem; 87 MemoryRegion timer_mem; 88 MemoryRegion dummyen_mem; 89 MemoryRegion mmiomem; 90 MemoryRegion scrmem; 91 92 uint32_t scr1; 93 uint32_t scr2; 94 uint32_t old_scr2; 95 uint32_t int_mask; 96 uint32_t int_status; 97 uint32_t led; 98 99 NeXTSCSI next_scsi; 100 101 qemu_irq scsi_reset; 102 qemu_irq scsi_dma; 103 104 ESCCState escc; 105 106 NeXTRTC rtc; 107 qemu_irq rtc_power_irq; 108 }; 109 110 typedef struct next_dma { 111 uint32_t csr; 112 113 uint32_t saved_next; 114 uint32_t saved_limit; 115 uint32_t saved_start; 116 uint32_t saved_stop; 117 118 uint32_t next; 119 uint32_t limit; 120 uint32_t start; 121 uint32_t stop; 122 123 uint32_t next_initbuf; 124 uint32_t size; 125 } next_dma; 126 127 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube") 128 OBJECT_DECLARE_SIMPLE_TYPE(NeXTState, NEXT_MACHINE) 129 130 struct NeXTState { 131 MachineState parent; 132 133 MemoryRegion rom; 134 MemoryRegion rom2; 135 MemoryRegion dmamem; 136 MemoryRegion bmapm1; 137 MemoryRegion bmapm2; 138 139 next_dma dma[10]; 140 }; 141 142 /* Thanks to NeXT forums for this */ 143 /* 144 static const uint8_t rtc_ram3[32] = { 145 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 146 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00, 147 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00, 148 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13 149 }; 150 */ 151 static const uint8_t rtc_ram2[32] = { 152 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00, 153 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00, 154 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 155 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e, 156 }; 157 158 #define SCR2_RTCLK 0x2 159 #define SCR2_RTDATA 0x4 160 #define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10)) 161 162 static void next_scr2_led_update(NeXTPC *s) 163 { 164 if (s->scr2 & 0x1) { 165 DPRINTF("fault!\n"); 166 s->led++; 167 if (s->led == 10) { 168 DPRINTF("LED flashing, possible fault!\n"); 169 s->led = 0; 170 } 171 } 172 } 173 174 static bool next_rtc_cmd_is_write(uint8_t cmd) 175 { 176 return (cmd >= 0x80 && cmd <= 0x9f) || 177 (cmd == 0xb1); 178 } 179 180 static void next_rtc_data_in_irq(void *opaque, int n, int level) 181 { 182 NeXTPC *s = NEXT_PC(opaque); 183 NeXTRTC *rtc = &s->rtc; 184 185 if (rtc->phase < 8) { 186 rtc->command = (rtc->command << 1) | level; 187 188 if (rtc->phase == 7 && !next_rtc_cmd_is_write(rtc->command)) { 189 if (rtc->command <= 0x1f) { 190 /* RAM registers */ 191 rtc->retval = rtc->ram[rtc->command]; 192 } 193 if ((rtc->command >= 0x20) && (rtc->command <= 0x2f)) { 194 /* RTC */ 195 time_t time_h = time(NULL); 196 struct tm *info = localtime(&time_h); 197 rtc->retval = 0; 198 199 switch (rtc->command) { 200 case 0x20: 201 rtc->retval = SCR2_TOBCD(info->tm_sec); 202 break; 203 case 0x21: 204 rtc->retval = SCR2_TOBCD(info->tm_min); 205 break; 206 case 0x22: 207 rtc->retval = SCR2_TOBCD(info->tm_hour); 208 break; 209 case 0x24: 210 rtc->retval = SCR2_TOBCD(info->tm_mday); 211 break; 212 case 0x25: 213 rtc->retval = SCR2_TOBCD((info->tm_mon + 1)); 214 break; 215 case 0x26: 216 rtc->retval = SCR2_TOBCD((info->tm_year - 100)); 217 break; 218 } 219 } 220 if (rtc->command == 0x30) { 221 /* read the status 0x30 */ 222 rtc->retval = rtc->status; 223 } 224 if (rtc->command == 0x31) { 225 /* read the control 0x31 */ 226 rtc->retval = rtc->control; 227 } 228 } 229 } 230 if (rtc->phase >= 8 && rtc->phase < 16) { 231 if (next_rtc_cmd_is_write(rtc->command)) { 232 /* Shift in value to write */ 233 rtc->value = (rtc->value << 1) | level; 234 } else { 235 /* Shift out value to read */ 236 qemu_irq rtc_data_in_irq = qdev_get_gpio_in_named( 237 DEVICE(s), "pc-rtc-data-in", 0); 238 239 if (rtc->retval & (0x80 >> (rtc->phase - 8))) { 240 qemu_irq_raise(rtc_data_in_irq); 241 } else { 242 qemu_irq_lower(rtc_data_in_irq); 243 } 244 } 245 } 246 247 rtc->phase++; 248 if (rtc->phase == 16 && next_rtc_cmd_is_write(rtc->command)) { 249 if (rtc->command >= 0x80 && rtc->command <= 0x9f) { 250 /* RAM registers */ 251 rtc->ram[rtc->command - 0x80] = rtc->value; 252 } 253 if (rtc->command == 0xb1) { 254 /* write to 0x30 register */ 255 if (rtc->value & 0x04) { 256 /* clear FTU */ 257 rtc->status = rtc->status & (~0x18); 258 qemu_irq_lower(s->rtc_power_irq); 259 } 260 } 261 } 262 } 263 264 static void next_scr2_rtc_update(NeXTPC *s) 265 { 266 uint8_t old_scr2, scr2_2; 267 NeXTRTC *rtc = &s->rtc; 268 269 old_scr2 = extract32(s->old_scr2, 8, 8); 270 scr2_2 = extract32(s->scr2, 8, 8); 271 272 if (scr2_2 & 0x1) { 273 /* DPRINTF("RTC %x phase %i\n", scr2_2, rtc->phase); */ 274 /* If we are in going down clock... do something */ 275 if (((old_scr2 & SCR2_RTCLK) != (scr2_2 & SCR2_RTCLK)) && 276 ((scr2_2 & SCR2_RTCLK) == 0)) { 277 qemu_irq rtc_data_in_irq = qdev_get_gpio_in_named( 278 DEVICE(s), "rtc-data-in", 0); 279 280 if (scr2_2 & SCR2_RTDATA) { 281 qemu_irq_raise(rtc_data_in_irq); 282 } else { 283 qemu_irq_lower(rtc_data_in_irq); 284 } 285 } 286 } else { 287 /* else end or abort */ 288 rtc->phase = 0; 289 rtc->command = 0; 290 rtc->value = 0; 291 } 292 } 293 294 static uint64_t next_mmio_read(void *opaque, hwaddr addr, unsigned size) 295 { 296 NeXTPC *s = NEXT_PC(opaque); 297 uint64_t val; 298 299 switch (addr) { 300 case 0x2000: /* 0x2007000 */ 301 /* DPRINTF("Read INT status: %x\n", s->int_status); */ 302 val = s->int_status; 303 break; 304 305 case 0x2800: /* 0x2007800 */ 306 DPRINTF("MMIO Read INT mask: %x\n", s->int_mask); 307 val = s->int_mask; 308 break; 309 310 case 0x7000 ... 0x7003: /* 0x200c000 */ 311 val = extract32(s->scr1, (4 - (addr - 0x7000) - size) << 3, 312 size << 3); 313 break; 314 315 case 0x8000 ... 0x8003: /* 0x200d000 */ 316 val = extract32(s->scr2, (4 - (addr - 0x8000) - size) << 3, 317 size << 3); 318 break; 319 320 default: 321 val = 0; 322 DPRINTF("MMIO Read @ 0x%"HWADDR_PRIx" size %d\n", addr, size); 323 break; 324 } 325 326 return val; 327 } 328 329 static void next_mmio_write(void *opaque, hwaddr addr, uint64_t val, 330 unsigned size) 331 { 332 NeXTPC *s = NEXT_PC(opaque); 333 334 switch (addr) { 335 case 0x2000: /* 0x2007000 */ 336 DPRINTF("INT Status old: %x new: %x\n", s->int_status, 337 (unsigned int)val); 338 s->int_status = val; 339 break; 340 341 case 0x2800: /* 0x2007800 */ 342 DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, (unsigned int)val); 343 s->int_mask = val; 344 break; 345 346 case 0x7000 ... 0x7003: /* 0x200c000 */ 347 DPRINTF("SCR1 Write: %x\n", (unsigned int)val); 348 s->scr1 = deposit32(s->scr1, (4 - (addr - 0x7000) - size) << 3, 349 size << 3, val); 350 break; 351 352 case 0x8000 ... 0x8003: /* 0x200d000 */ 353 s->scr2 = deposit32(s->scr2, (4 - (addr - 0x8000) - size) << 3, 354 size << 3, val); 355 next_scr2_led_update(s); 356 next_scr2_rtc_update(s); 357 s->old_scr2 = s->scr2; 358 break; 359 360 default: 361 DPRINTF("MMIO Write @ 0x%"HWADDR_PRIx " with 0x%x size %u\n", addr, 362 (unsigned int)val, size); 363 } 364 } 365 366 static const MemoryRegionOps next_mmio_ops = { 367 .read = next_mmio_read, 368 .write = next_mmio_write, 369 .valid.min_access_size = 1, 370 .valid.max_access_size = 4, 371 .endianness = DEVICE_BIG_ENDIAN, 372 }; 373 374 #define SCSICSR_ENABLE 0x01 375 #define SCSICSR_RESET 0x02 /* reset scsi dma */ 376 #define SCSICSR_FIFOFL 0x04 377 #define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */ 378 #define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */ 379 #define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */ 380 381 #define NEXTDMA_SCSI(x) (0x10 + x) 382 #define NEXTDMA_FD(x) (0x10 + x) 383 #define NEXTDMA_ENTX(x) (0x110 + x) 384 #define NEXTDMA_ENRX(x) (0x150 + x) 385 #define NEXTDMA_CSR 0x0 386 #define NEXTDMA_NEXT 0x4000 387 #define NEXTDMA_LIMIT 0x4004 388 #define NEXTDMA_START 0x4008 389 #define NEXTDMA_STOP 0x400c 390 #define NEXTDMA_NEXT_INIT 0x4200 391 #define NEXTDMA_SIZE 0x4204 392 393 static void next_dma_write(void *opaque, hwaddr addr, uint64_t val, 394 unsigned int size) 395 { 396 NeXTState *next_state = NEXT_MACHINE(opaque); 397 398 switch (addr) { 399 case NEXTDMA_ENRX(NEXTDMA_CSR): 400 if (val & DMA_DEV2M) { 401 next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M; 402 } 403 404 if (val & DMA_SETENABLE) { 405 /* DPRINTF("SCSI DMA ENABLE\n"); */ 406 next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE; 407 } 408 if (val & DMA_SETSUPDATE) { 409 next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE; 410 } 411 if (val & DMA_CLRCOMPLETE) { 412 next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE; 413 } 414 415 if (val & DMA_RESET) { 416 next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 417 DMA_ENABLE | DMA_DEV2M); 418 } 419 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 420 break; 421 422 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 423 next_state->dma[NEXTDMA_ENRX].next_initbuf = val; 424 break; 425 426 case NEXTDMA_ENRX(NEXTDMA_NEXT): 427 next_state->dma[NEXTDMA_ENRX].next = val; 428 break; 429 430 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 431 next_state->dma[NEXTDMA_ENRX].limit = val; 432 break; 433 434 case NEXTDMA_SCSI(NEXTDMA_CSR): 435 if (val & DMA_DEV2M) { 436 next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M; 437 } 438 if (val & DMA_SETENABLE) { 439 /* DPRINTF("SCSI DMA ENABLE\n"); */ 440 next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE; 441 } 442 if (val & DMA_SETSUPDATE) { 443 next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE; 444 } 445 if (val & DMA_CLRCOMPLETE) { 446 next_state->dma[NEXTDMA_SCSI].csr &= ~DMA_COMPLETE; 447 } 448 449 if (val & DMA_RESET) { 450 next_state->dma[NEXTDMA_SCSI].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 451 DMA_ENABLE | DMA_DEV2M); 452 /* DPRINTF("SCSI DMA RESET\n"); */ 453 } 454 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 455 break; 456 457 case NEXTDMA_SCSI(NEXTDMA_NEXT): 458 next_state->dma[NEXTDMA_SCSI].next = val; 459 break; 460 461 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 462 next_state->dma[NEXTDMA_SCSI].limit = val; 463 break; 464 465 case NEXTDMA_SCSI(NEXTDMA_START): 466 next_state->dma[NEXTDMA_SCSI].start = val; 467 break; 468 469 case NEXTDMA_SCSI(NEXTDMA_STOP): 470 next_state->dma[NEXTDMA_SCSI].stop = val; 471 break; 472 473 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 474 next_state->dma[NEXTDMA_SCSI].next_initbuf = val; 475 break; 476 477 default: 478 DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)val); 479 } 480 } 481 482 static uint64_t next_dma_read(void *opaque, hwaddr addr, unsigned int size) 483 { 484 NeXTState *next_state = NEXT_MACHINE(opaque); 485 uint64_t val; 486 487 switch (addr) { 488 case NEXTDMA_SCSI(NEXTDMA_CSR): 489 DPRINTF("SCSI DMA CSR READ\n"); 490 val = next_state->dma[NEXTDMA_SCSI].csr; 491 break; 492 493 case NEXTDMA_ENRX(NEXTDMA_CSR): 494 val = next_state->dma[NEXTDMA_ENRX].csr; 495 break; 496 497 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 498 val = next_state->dma[NEXTDMA_ENRX].next_initbuf; 499 break; 500 501 case NEXTDMA_ENRX(NEXTDMA_NEXT): 502 val = next_state->dma[NEXTDMA_ENRX].next; 503 break; 504 505 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 506 val = next_state->dma[NEXTDMA_ENRX].limit; 507 break; 508 509 case NEXTDMA_SCSI(NEXTDMA_NEXT): 510 val = next_state->dma[NEXTDMA_SCSI].next; 511 break; 512 513 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 514 val = next_state->dma[NEXTDMA_SCSI].next_initbuf; 515 break; 516 517 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 518 val = next_state->dma[NEXTDMA_SCSI].limit; 519 break; 520 521 case NEXTDMA_SCSI(NEXTDMA_START): 522 val = next_state->dma[NEXTDMA_SCSI].start; 523 break; 524 525 case NEXTDMA_SCSI(NEXTDMA_STOP): 526 val = next_state->dma[NEXTDMA_SCSI].stop; 527 break; 528 529 default: 530 DPRINTF("DMA read @ %x\n", (unsigned int)addr); 531 val = 0; 532 } 533 534 /* 535 * once the csr's are done, subtract 0x3FEC from the addr, and that will 536 * normalize the upper registers 537 */ 538 539 return val; 540 } 541 542 static const MemoryRegionOps next_dma_ops = { 543 .read = next_dma_read, 544 .write = next_dma_write, 545 .impl.min_access_size = 4, 546 .valid.min_access_size = 4, 547 .valid.max_access_size = 4, 548 .endianness = DEVICE_BIG_ENDIAN, 549 }; 550 551 static void next_irq(void *opaque, int number, int level) 552 { 553 NeXTPC *s = NEXT_PC(opaque); 554 M68kCPU *cpu = s->cpu; 555 int shift = 0; 556 557 /* first switch sets interrupt status */ 558 /* DPRINTF("IRQ %i\n",number); */ 559 switch (number) { 560 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 561 case NEXT_FD_I: 562 shift = 7; 563 break; 564 case NEXT_KBD_I: 565 shift = 3; 566 break; 567 case NEXT_PWR_I: 568 shift = 2; 569 break; 570 case NEXT_ENRX_I: 571 shift = 9; 572 break; 573 case NEXT_ENTX_I: 574 shift = 10; 575 break; 576 case NEXT_SCSI_I: 577 shift = 12; 578 break; 579 case NEXT_CLK_I: 580 shift = 5; 581 break; 582 583 /* level 5 - scc (serial) */ 584 case NEXT_SCC_I: 585 shift = 17; 586 break; 587 588 /* level 6 - audio etherrx/tx dma */ 589 case NEXT_ENTX_DMA_I: 590 shift = 28; 591 break; 592 case NEXT_ENRX_DMA_I: 593 shift = 27; 594 break; 595 case NEXT_SCSI_DMA_I: 596 shift = 26; 597 break; 598 case NEXT_SND_I: 599 shift = 23; 600 break; 601 case NEXT_SCC_DMA_I: 602 shift = 21; 603 break; 604 605 } 606 /* 607 * this HAS to be wrong, the interrupt handlers in mach and together 608 * int_status and int_mask and return if there is a hit 609 */ 610 if (s->int_mask & (1 << shift)) { 611 DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc); 612 /* return; */ 613 } 614 615 /* second switch triggers the correct interrupt */ 616 if (level) { 617 s->int_status |= 1 << shift; 618 619 switch (number) { 620 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 621 case NEXT_FD_I: 622 case NEXT_KBD_I: 623 case NEXT_PWR_I: 624 case NEXT_ENRX_I: 625 case NEXT_ENTX_I: 626 case NEXT_SCSI_I: 627 case NEXT_CLK_I: 628 m68k_set_irq_level(cpu, 3, 27); 629 break; 630 631 /* level 5 - scc (serial) */ 632 case NEXT_SCC_I: 633 m68k_set_irq_level(cpu, 5, 29); 634 break; 635 636 /* level 6 - audio etherrx/tx dma */ 637 case NEXT_ENTX_DMA_I: 638 case NEXT_ENRX_DMA_I: 639 case NEXT_SCSI_DMA_I: 640 case NEXT_SND_I: 641 case NEXT_SCC_DMA_I: 642 m68k_set_irq_level(cpu, 6, 30); 643 break; 644 } 645 } else { 646 s->int_status &= ~(1 << shift); 647 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); 648 } 649 } 650 651 static void nextdma_write(void *opaque, uint8_t *buf, int size, int type) 652 { 653 uint32_t base_addr; 654 int irq = 0; 655 uint8_t align = 16; 656 NeXTState *next_state = NEXT_MACHINE(qdev_get_machine()); 657 658 if (type == NEXTDMA_ENRX || type == NEXTDMA_ENTX) { 659 align = 32; 660 } 661 /* Most DMA is supposedly 16 byte aligned */ 662 if ((size % align) != 0) { 663 size -= size % align; 664 size += align; 665 } 666 667 /* 668 * prom sets the dma start using initbuf while the bootloader uses next 669 * so we check to see if initbuf is 0 670 */ 671 if (next_state->dma[type].next_initbuf == 0) { 672 base_addr = next_state->dma[type].next; 673 } else { 674 base_addr = next_state->dma[type].next_initbuf; 675 } 676 677 cpu_physical_memory_write(base_addr, buf, size); 678 679 next_state->dma[type].next_initbuf = 0; 680 681 /* saved limit is checked to calculate packet size by both, rom and netbsd */ 682 next_state->dma[type].saved_limit = (next_state->dma[type].next + size); 683 next_state->dma[type].saved_next = (next_state->dma[type].next); 684 685 /* 686 * 32 bytes under savedbase seems to be some kind of register 687 * of which the purpose is unknown as of yet 688 */ 689 /* stl_phys(s->rx_dma.base-32,0xFFFFFFFF); */ 690 691 if (!(next_state->dma[type].csr & DMA_SUPDATE)) { 692 next_state->dma[type].next = next_state->dma[type].start; 693 next_state->dma[type].limit = next_state->dma[type].stop; 694 } 695 696 /* Set dma registers and raise an irq */ 697 next_state->dma[type].csr |= DMA_COMPLETE; /* DON'T CHANGE THIS! */ 698 699 switch (type) { 700 case NEXTDMA_SCSI: 701 irq = NEXT_SCSI_DMA_I; 702 break; 703 } 704 705 next_irq(opaque, irq, 1); 706 next_irq(opaque, irq, 0); 707 } 708 709 static void nextscsi_read(void *opaque, uint8_t *buf, int len) 710 { 711 DPRINTF("SCSI READ: %x\n", len); 712 abort(); 713 } 714 715 static void nextscsi_write(void *opaque, uint8_t *buf, int size) 716 { 717 DPRINTF("SCSI WRITE: %i\n", size); 718 nextdma_write(opaque, buf, size, NEXTDMA_SCSI); 719 } 720 721 static void next_scsi_csr_write(void *opaque, hwaddr addr, uint64_t val, 722 unsigned size) 723 { 724 NeXTSCSI *s = NEXT_SCSI(opaque); 725 NeXTPC *pc = NEXT_PC(container_of(s, NeXTPC, next_scsi)); 726 727 switch (addr) { 728 case 0: 729 if (val & SCSICSR_FIFOFL) { 730 DPRINTF("SCSICSR FIFO Flush\n"); 731 /* will have to add another irq to the esp if this is needed */ 732 /* esp_puflush_fifo(esp_g); */ 733 } 734 735 if (val & SCSICSR_ENABLE) { 736 DPRINTF("SCSICSR Enable\n"); 737 /* 738 * qemu_irq_raise(s->scsi_dma); 739 * s->scsi_csr_1 = 0xc0; 740 * s->scsi_csr_1 |= 0x1; 741 * qemu_irq_pulse(s->scsi_dma); 742 */ 743 } 744 /* 745 * else 746 * s->scsi_csr_1 &= ~SCSICSR_ENABLE; 747 */ 748 749 if (val & SCSICSR_RESET) { 750 DPRINTF("SCSICSR Reset\n"); 751 /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */ 752 qemu_irq_raise(pc->scsi_reset); 753 s->scsi_csr_1 &= ~(SCSICSR_INTMASK | 0x80 | 0x1); 754 qemu_irq_lower(pc->scsi_reset); 755 } 756 if (val & SCSICSR_DMADIR) { 757 DPRINTF("SCSICSR DMAdir\n"); 758 } 759 if (val & SCSICSR_CPUDMA) { 760 DPRINTF("SCSICSR CPUDMA\n"); 761 /* qemu_irq_raise(s->scsi_dma); */ 762 pc->int_status |= 0x4000000; 763 } else { 764 /* fprintf(stderr,"SCSICSR CPUDMA disabled\n"); */ 765 pc->int_status &= ~(0x4000000); 766 /* qemu_irq_lower(s->scsi_dma); */ 767 } 768 if (val & SCSICSR_INTMASK) { 769 DPRINTF("SCSICSR INTMASK\n"); 770 /* 771 * int_mask &= ~0x1000; 772 * s->scsi_csr_1 |= val; 773 * s->scsi_csr_1 &= ~SCSICSR_INTMASK; 774 * if (s->scsi_queued) { 775 * s->scsi_queued = 0; 776 * next_irq(s, NEXT_SCSI_I, level); 777 * } 778 */ 779 } else { 780 /* int_mask |= 0x1000; */ 781 } 782 if (val & 0x80) { 783 /* int_mask |= 0x1000; */ 784 /* s->scsi_csr_1 |= 0x80; */ 785 } 786 DPRINTF("SCSICSR1 Write: %"PRIx64 "\n", val); 787 s->scsi_csr_1 = val; 788 break; 789 790 case 1: 791 DPRINTF("SCSICSR2 Write: %"PRIx64 "\n", val); 792 s->scsi_csr_2 = val; 793 break; 794 795 default: 796 g_assert_not_reached(); 797 } 798 } 799 800 static uint64_t next_scsi_csr_read(void *opaque, hwaddr addr, unsigned size) 801 { 802 NeXTSCSI *s = NEXT_SCSI(opaque); 803 uint64_t val; 804 805 switch (addr) { 806 case 0: 807 DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1); 808 val = s->scsi_csr_1; 809 break; 810 811 case 1: 812 DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2); 813 val = s->scsi_csr_2; 814 break; 815 816 default: 817 g_assert_not_reached(); 818 } 819 820 return val; 821 } 822 823 static const MemoryRegionOps next_scsi_csr_ops = { 824 .read = next_scsi_csr_read, 825 .write = next_scsi_csr_write, 826 .valid.min_access_size = 1, 827 .valid.max_access_size = 1, 828 .endianness = DEVICE_BIG_ENDIAN, 829 }; 830 831 static void next_scsi_init(Object *obj) 832 { 833 NeXTSCSI *s = NEXT_SCSI(obj); 834 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 835 836 object_initialize_child(obj, "esp", &s->sysbus_esp, TYPE_SYSBUS_ESP); 837 838 memory_region_init_io(&s->scsi_csr_mem, obj, &next_scsi_csr_ops, 839 s, "csrs", 2); 840 841 memory_region_init(&s->scsi_mem, obj, "next.scsi", 0x40); 842 sysbus_init_mmio(sbd, &s->scsi_mem); 843 } 844 845 static void next_scsi_realize(DeviceState *dev, Error **errp) 846 { 847 NeXTSCSI *s = NEXT_SCSI(dev); 848 SysBusESPState *sysbus_esp; 849 SysBusDevice *sbd; 850 ESPState *esp; 851 NeXTPC *pcdev; 852 853 pcdev = NEXT_PC(container_of(s, NeXTPC, next_scsi)); 854 855 /* ESP */ 856 sysbus_esp = SYSBUS_ESP(&s->sysbus_esp); 857 esp = &sysbus_esp->esp; 858 esp->dma_memory_read = nextscsi_read; 859 esp->dma_memory_write = nextscsi_write; 860 esp->dma_opaque = pcdev; 861 sysbus_esp->it_shift = 0; 862 esp->dma_enabled = 1; 863 sbd = SYS_BUS_DEVICE(sysbus_esp); 864 if (!sysbus_realize(sbd, errp)) { 865 return; 866 } 867 memory_region_add_subregion(&s->scsi_mem, 0x0, 868 sysbus_mmio_get_region(sbd, 0)); 869 870 /* SCSI CSRs */ 871 memory_region_add_subregion(&s->scsi_mem, 0x20, &s->scsi_csr_mem); 872 873 scsi_bus_legacy_handle_cmdline(&s->sysbus_esp.esp.bus); 874 } 875 876 static const VMStateDescription next_scsi_vmstate = { 877 .name = "next-scsi", 878 .version_id = 0, 879 .minimum_version_id = 0, 880 .fields = (const VMStateField[]) { 881 VMSTATE_UINT8(scsi_csr_1, NeXTSCSI), 882 VMSTATE_UINT8(scsi_csr_2, NeXTSCSI), 883 VMSTATE_END_OF_LIST() 884 }, 885 }; 886 887 static void next_scsi_class_init(ObjectClass *klass, void *data) 888 { 889 DeviceClass *dc = DEVICE_CLASS(klass); 890 891 dc->desc = "NeXT SCSI Controller"; 892 dc->realize = next_scsi_realize; 893 dc->vmsd = &next_scsi_vmstate; 894 } 895 896 static const TypeInfo next_scsi_info = { 897 .name = TYPE_NEXT_SCSI, 898 .parent = TYPE_SYS_BUS_DEVICE, 899 .instance_init = next_scsi_init, 900 .instance_size = sizeof(NeXTSCSI), 901 .class_init = next_scsi_class_init, 902 }; 903 904 static void next_floppy_write(void *opaque, hwaddr addr, uint64_t val, 905 unsigned size) 906 { 907 switch (addr) { 908 case 0: 909 DPRINTF("FDCSR Write: %"PRIx64 "\n", val); 910 if (val == 0x0) { 911 /* qemu_irq_raise(s->fd_irq[0]); */ 912 } 913 break; 914 915 default: 916 g_assert_not_reached(); 917 } 918 } 919 920 static uint64_t next_floppy_read(void *opaque, hwaddr addr, unsigned size) 921 { 922 uint64_t val; 923 924 switch (addr) { 925 case 0: 926 DPRINTF("FD read @ %x\n", (unsigned int)addr); 927 val = 0x40 | 0x04 | 0x2 | 0x1; 928 break; 929 930 default: 931 g_assert_not_reached(); 932 } 933 934 return val; 935 } 936 937 static const MemoryRegionOps next_floppy_ops = { 938 .read = next_floppy_read, 939 .write = next_floppy_write, 940 .valid.min_access_size = 1, 941 .valid.max_access_size = 4, 942 .endianness = DEVICE_BIG_ENDIAN, 943 }; 944 945 static void next_timer_write(void *opaque, hwaddr addr, uint64_t val, 946 unsigned size) 947 { 948 switch (addr) { 949 case 0 ... 3: 950 /* Hardware timer latch - not implemented yet */ 951 break; 952 953 default: 954 g_assert_not_reached(); 955 } 956 } 957 958 static uint64_t next_timer_read(void *opaque, hwaddr addr, unsigned size) 959 { 960 uint64_t val; 961 962 switch (addr) { 963 case 0 ... 3: 964 /* 965 * These 4 registers are the hardware timer, not sure which register 966 * is the latch instead of data, but no problems so far. 967 * 968 * Hack: We need to have the LSB change consistently to make it work 969 */ 970 val = extract32(clock(), (4 - addr - size) << 3, 971 size << 3); 972 break; 973 974 default: 975 g_assert_not_reached(); 976 } 977 978 return val; 979 } 980 981 static const MemoryRegionOps next_timer_ops = { 982 .read = next_timer_read, 983 .write = next_timer_write, 984 .valid.min_access_size = 1, 985 .valid.max_access_size = 4, 986 .endianness = DEVICE_BIG_ENDIAN, 987 }; 988 989 static void next_dummy_en_write(void *opaque, hwaddr addr, uint64_t val, 990 unsigned size) 991 { 992 /* Do nothing */ 993 return; 994 } 995 996 static uint64_t next_dummy_en_read(void *opaque, hwaddr addr, unsigned size) 997 { 998 uint64_t val; 999 1000 switch (addr) { 1001 case 0: 1002 /* For now return dummy byte to allow the Ethernet test to timeout */ 1003 val = 0xff; 1004 break; 1005 1006 default: 1007 val = 0; 1008 } 1009 1010 return val; 1011 } 1012 1013 static const MemoryRegionOps next_dummy_en_ops = { 1014 .read = next_dummy_en_read, 1015 .write = next_dummy_en_write, 1016 .valid.min_access_size = 1, 1017 .valid.max_access_size = 4, 1018 .endianness = DEVICE_BIG_ENDIAN, 1019 }; 1020 1021 static const VMStateDescription next_rtc_vmstate = { 1022 .name = "next-rtc", 1023 .version_id = 3, 1024 .minimum_version_id = 3, 1025 .fields = (const VMStateField[]) { 1026 VMSTATE_INT8(phase, NeXTRTC), 1027 VMSTATE_UINT8_ARRAY(ram, NeXTRTC, 32), 1028 VMSTATE_UINT8(command, NeXTRTC), 1029 VMSTATE_UINT8(value, NeXTRTC), 1030 VMSTATE_UINT8(status, NeXTRTC), 1031 VMSTATE_UINT8(control, NeXTRTC), 1032 VMSTATE_UINT8(retval, NeXTRTC), 1033 VMSTATE_END_OF_LIST() 1034 }, 1035 }; 1036 1037 static void next_rtc_class_init(ObjectClass *klass, void *data) 1038 { 1039 DeviceClass *dc = DEVICE_CLASS(klass); 1040 1041 dc->desc = "NeXT RTC"; 1042 dc->vmsd = &next_rtc_vmstate; 1043 } 1044 1045 static const TypeInfo next_rtc_info = { 1046 .name = TYPE_NEXT_RTC, 1047 .parent = TYPE_SYS_BUS_DEVICE, 1048 .instance_size = sizeof(NeXTRTC), 1049 .class_init = next_rtc_class_init, 1050 }; 1051 1052 static void next_pc_rtc_data_in_irq(void *opaque, int n, int level) 1053 { 1054 NeXTPC *s = NEXT_PC(opaque); 1055 uint8_t scr2_2 = extract32(s->scr2, 8, 8); 1056 1057 if (level) { 1058 scr2_2 |= SCR2_RTDATA; 1059 } else { 1060 scr2_2 &= ~SCR2_RTDATA; 1061 } 1062 1063 s->scr2 = deposit32(s->scr2, 8, 8, scr2_2); 1064 } 1065 1066 static void next_pc_reset_hold(Object *obj, ResetType type) 1067 { 1068 NeXTPC *s = NEXT_PC(obj); 1069 1070 /* Set internal registers to initial values */ 1071 /* 0x0000XX00 << vital bits */ 1072 s->scr1 = 0x00011102; 1073 s->scr2 = 0x00ff0c80; 1074 s->old_scr2 = s->scr2; 1075 1076 s->rtc.status = 0x90; 1077 1078 /* Load RTC RAM - TODO: provide possibility to load contents from file */ 1079 memcpy(s->rtc.ram, rtc_ram2, 32); 1080 } 1081 1082 static void next_pc_realize(DeviceState *dev, Error **errp) 1083 { 1084 NeXTPC *s = NEXT_PC(dev); 1085 SysBusDevice *sbd; 1086 DeviceState *d; 1087 1088 /* SCSI */ 1089 sbd = SYS_BUS_DEVICE(&s->next_scsi); 1090 if (!sysbus_realize(sbd, errp)) { 1091 return; 1092 } 1093 1094 d = DEVICE(object_resolve_path_component(OBJECT(&s->next_scsi), "esp")); 1095 sysbus_connect_irq(SYS_BUS_DEVICE(d), 0, 1096 qdev_get_gpio_in(DEVICE(s), NEXT_SCSI_I)); 1097 1098 s->scsi_reset = qdev_get_gpio_in(d, 0); 1099 s->scsi_dma = qdev_get_gpio_in(d, 1); 1100 1101 /* ESCC */ 1102 d = DEVICE(&s->escc); 1103 qdev_prop_set_uint32(d, "disabled", 0); 1104 qdev_prop_set_uint32(d, "frequency", 9600 * 384); 1105 qdev_prop_set_uint32(d, "it_shift", 0); 1106 qdev_prop_set_bit(d, "bit_swap", true); 1107 qdev_prop_set_chr(d, "chrB", serial_hd(1)); 1108 qdev_prop_set_chr(d, "chrA", serial_hd(0)); 1109 qdev_prop_set_uint32(d, "chnBtype", escc_serial); 1110 qdev_prop_set_uint32(d, "chnAtype", escc_serial); 1111 1112 sbd = SYS_BUS_DEVICE(d); 1113 if (!sysbus_realize(sbd, errp)) { 1114 return; 1115 } 1116 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(dev, NEXT_SCC_I)); 1117 sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(dev, NEXT_SCC_DMA_I)); 1118 1119 /* RTC */ 1120 d = DEVICE(&s->rtc); 1121 if (!sysbus_realize(SYS_BUS_DEVICE(d), errp)) { 1122 return; 1123 } 1124 } 1125 1126 static void next_pc_init(Object *obj) 1127 { 1128 NeXTPC *s = NEXT_PC(obj); 1129 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1130 1131 qdev_init_gpio_in(DEVICE(obj), next_irq, NEXT_NUM_IRQS); 1132 1133 memory_region_init_io(&s->mmiomem, OBJECT(s), &next_mmio_ops, s, 1134 "next.mmio", 0x9000); 1135 sysbus_init_mmio(sbd, &s->mmiomem); 1136 1137 memory_region_init_io(&s->dummyen_mem, OBJECT(s), &next_dummy_en_ops, s, 1138 "next.en", 0x20); 1139 sysbus_init_mmio(sbd, &s->dummyen_mem); 1140 1141 object_initialize_child(obj, "next-scsi", &s->next_scsi, TYPE_NEXT_SCSI); 1142 sysbus_init_mmio(sbd, 1143 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->next_scsi), 0)); 1144 1145 memory_region_init_io(&s->floppy_mem, OBJECT(s), &next_floppy_ops, s, 1146 "next.floppy", 4); 1147 sysbus_init_mmio(sbd, &s->floppy_mem); 1148 1149 object_initialize_child(obj, "escc", &s->escc, TYPE_ESCC); 1150 sysbus_init_mmio(sbd, 1151 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->escc), 0)); 1152 1153 memory_region_init_io(&s->timer_mem, OBJECT(s), &next_timer_ops, s, 1154 "next.timer", 4); 1155 sysbus_init_mmio(sbd, &s->timer_mem); 1156 1157 object_initialize_child(obj, "rtc", &s->rtc, TYPE_NEXT_RTC); 1158 1159 s->rtc_power_irq = qdev_get_gpio_in(DEVICE(obj), NEXT_PWR_I); 1160 qdev_init_gpio_in_named(DEVICE(obj), next_pc_rtc_data_in_irq, 1161 "pc-rtc-data-in", 1); 1162 qdev_init_gpio_in_named(DEVICE(obj), next_rtc_data_in_irq, 1163 "rtc-data-in", 1); 1164 } 1165 1166 /* 1167 * If the m68k CPU implemented its inbound irq lines as GPIO lines 1168 * rather than via the m68k_set_irq_level() function we would not need 1169 * this cpu link property and could instead provide outbound IRQ lines 1170 * that the board could wire up to the CPU. 1171 */ 1172 static const Property next_pc_properties[] = { 1173 DEFINE_PROP_LINK("cpu", NeXTPC, cpu, TYPE_M68K_CPU, M68kCPU *), 1174 }; 1175 1176 static const VMStateDescription next_pc_vmstate = { 1177 .name = "next-pc", 1178 .version_id = 4, 1179 .minimum_version_id = 4, 1180 .fields = (const VMStateField[]) { 1181 VMSTATE_UINT32(scr1, NeXTPC), 1182 VMSTATE_UINT32(scr2, NeXTPC), 1183 VMSTATE_UINT32(old_scr2, NeXTPC), 1184 VMSTATE_UINT32(int_mask, NeXTPC), 1185 VMSTATE_UINT32(int_status, NeXTPC), 1186 VMSTATE_UINT32(led, NeXTPC), 1187 VMSTATE_END_OF_LIST() 1188 }, 1189 }; 1190 1191 static void next_pc_class_init(ObjectClass *klass, void *data) 1192 { 1193 DeviceClass *dc = DEVICE_CLASS(klass); 1194 ResettableClass *rc = RESETTABLE_CLASS(klass); 1195 1196 dc->desc = "NeXT Peripheral Controller"; 1197 dc->realize = next_pc_realize; 1198 device_class_set_props(dc, next_pc_properties); 1199 dc->vmsd = &next_pc_vmstate; 1200 rc->phases.hold = next_pc_reset_hold; 1201 } 1202 1203 static const TypeInfo next_pc_info = { 1204 .name = TYPE_NEXT_PC, 1205 .parent = TYPE_SYS_BUS_DEVICE, 1206 .instance_init = next_pc_init, 1207 .instance_size = sizeof(NeXTPC), 1208 .class_init = next_pc_class_init, 1209 }; 1210 1211 static void next_cube_init(MachineState *machine) 1212 { 1213 NeXTState *m = NEXT_MACHINE(machine); 1214 M68kCPU *cpu; 1215 CPUM68KState *env; 1216 MemoryRegion *sysmem = get_system_memory(); 1217 const char *bios_name = machine->firmware ?: ROM_FILE; 1218 DeviceState *pcdev; 1219 1220 /* Initialize the cpu core */ 1221 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 1222 if (!cpu) { 1223 error_report("Unable to find m68k CPU definition"); 1224 exit(1); 1225 } 1226 env = &cpu->env; 1227 1228 /* Initialize CPU registers. */ 1229 env->vbr = 0; 1230 env->sr = 0x2700; 1231 1232 /* Peripheral Controller */ 1233 pcdev = qdev_new(TYPE_NEXT_PC); 1234 object_property_set_link(OBJECT(pcdev), "cpu", OBJECT(cpu), &error_abort); 1235 sysbus_realize_and_unref(SYS_BUS_DEVICE(pcdev), &error_fatal); 1236 1237 /* 64MB RAM starting at 0x04000000 */ 1238 memory_region_add_subregion(sysmem, 0x04000000, machine->ram); 1239 1240 /* Framebuffer */ 1241 sysbus_create_simple(TYPE_NEXTFB, 0x0B000000, NULL); 1242 1243 /* MMIO */ 1244 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02005000); 1245 1246 /* BMAP IO - acts as a catch-all for now */ 1247 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02100000); 1248 1249 /* en network (dummy) */ 1250 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02106000); 1251 1252 /* unknown: Brightness control register? */ 1253 empty_slot_init("next.unknown.0", 0x02110000, 0x10); 1254 /* unknown: Magneto-Optical drive controller? */ 1255 empty_slot_init("next.unknown.1", 0x02112000, 0x10); 1256 1257 /* SCSI */ 1258 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 2, 0x02114000); 1259 /* Floppy */ 1260 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 3, 0x02114108); 1261 /* ESCC */ 1262 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 4, 0x02118000); 1263 1264 /* unknown: Serial clock configuration register? */ 1265 empty_slot_init("next.unknown.2", 0x02118004, 0x10); 1266 1267 /* Timer */ 1268 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 5, 0x0211a000); 1269 1270 /* BMAP memory */ 1271 memory_region_init_ram_flags_nomigrate(&m->bmapm1, NULL, "next.bmapmem", 1272 64, RAM_SHARED, &error_fatal); 1273 memory_region_add_subregion(sysmem, 0x020c0000, &m->bmapm1); 1274 /* The Rev_2.5_v66.bin firmware accesses it at 0x820c0020, too */ 1275 memory_region_init_alias(&m->bmapm2, NULL, "next.bmapmem2", &m->bmapm1, 1276 0x0, 64); 1277 memory_region_add_subregion(sysmem, 0x820c0000, &m->bmapm2); 1278 1279 /* KBD */ 1280 sysbus_create_simple(TYPE_NEXTKBD, 0x0200e000, NULL); 1281 1282 /* Load ROM here */ 1283 memory_region_init_rom(&m->rom, NULL, "next.rom", 0x20000, &error_fatal); 1284 memory_region_add_subregion(sysmem, 0x01000000, &m->rom); 1285 memory_region_init_alias(&m->rom2, NULL, "next.rom2", &m->rom, 0x0, 1286 0x20000); 1287 memory_region_add_subregion(sysmem, 0x0, &m->rom2); 1288 if (load_image_targphys(bios_name, 0x01000000, 0x20000) < 8) { 1289 if (!qtest_enabled()) { 1290 error_report("Failed to load firmware '%s'.", bios_name); 1291 } 1292 } else { 1293 uint8_t *ptr; 1294 /* Initial PC is always at offset 4 in firmware binaries */ 1295 ptr = rom_ptr(0x01000004, 4); 1296 g_assert(ptr != NULL); 1297 env->pc = ldl_be_p(ptr); 1298 if (env->pc >= 0x01020000) { 1299 error_report("'%s' does not seem to be a valid firmware image.", 1300 bios_name); 1301 exit(1); 1302 } 1303 } 1304 1305 /* DMA */ 1306 memory_region_init_io(&m->dmamem, NULL, &next_dma_ops, machine, 1307 "next.dma", 0x5000); 1308 memory_region_add_subregion(sysmem, 0x02000000, &m->dmamem); 1309 } 1310 1311 static void next_machine_class_init(ObjectClass *oc, void *data) 1312 { 1313 MachineClass *mc = MACHINE_CLASS(oc); 1314 1315 mc->desc = "NeXT Cube"; 1316 mc->init = next_cube_init; 1317 mc->block_default_type = IF_SCSI; 1318 mc->default_ram_size = RAM_SIZE; 1319 mc->default_ram_id = "next.ram"; 1320 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); 1321 mc->no_cdrom = true; 1322 } 1323 1324 static const TypeInfo next_typeinfo = { 1325 .name = TYPE_NEXT_MACHINE, 1326 .parent = TYPE_MACHINE, 1327 .class_init = next_machine_class_init, 1328 .instance_size = sizeof(NeXTState), 1329 }; 1330 1331 static void next_register_type(void) 1332 { 1333 type_register_static(&next_typeinfo); 1334 type_register_static(&next_pc_info); 1335 type_register_static(&next_scsi_info); 1336 type_register_static(&next_rtc_info); 1337 } 1338 1339 type_init(next_register_type) 1340