1 /* 2 * NeXT Cube System Driver 3 * 4 * Copyright (c) 2011 Bryce Lanham 5 * 6 * This code is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published 8 * by the Free Software Foundation; either version 2 of the License, 9 * or (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "exec/hwaddr.h" 14 #include "system/system.h" 15 #include "system/qtest.h" 16 #include "hw/irq.h" 17 #include "hw/m68k/next-cube.h" 18 #include "hw/boards.h" 19 #include "hw/loader.h" 20 #include "hw/scsi/esp.h" 21 #include "hw/sysbus.h" 22 #include "qom/object.h" 23 #include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */ 24 #include "hw/block/fdc.h" 25 #include "hw/misc/empty_slot.h" 26 #include "hw/qdev-properties.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "ui/console.h" 30 #include "target/m68k/cpu.h" 31 #include "migration/vmstate.h" 32 33 /* #define DEBUG_NEXT */ 34 #ifdef DEBUG_NEXT 35 #define DPRINTF(fmt, ...) \ 36 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0) 37 #else 38 #define DPRINTF(fmt, ...) do { } while (0) 39 #endif 40 41 #define ENTRY 0x0100001e 42 #define RAM_SIZE 0x4000000 43 #define ROM_FILE "Rev_2.5_v66.bin" 44 45 46 #define TYPE_NEXT_RTC "next-rtc" 47 OBJECT_DECLARE_SIMPLE_TYPE(NeXTRTC, NEXT_RTC) 48 49 struct NeXTRTC { 50 SysBusDevice parent_obj; 51 52 int8_t phase; 53 uint8_t ram[32]; 54 uint8_t command; 55 uint8_t value; 56 uint8_t status; 57 uint8_t control; 58 uint8_t retval; 59 60 qemu_irq data_out_irq; 61 }; 62 63 #define TYPE_NEXT_SCSI "next-scsi" 64 OBJECT_DECLARE_SIMPLE_TYPE(NeXTSCSI, NEXT_SCSI) 65 66 /* NeXT SCSI Controller */ 67 struct NeXTSCSI { 68 SysBusDevice parent_obj; 69 70 MemoryRegion scsi_mem; 71 72 SysBusESPState sysbus_esp; 73 74 MemoryRegion scsi_csr_mem; 75 uint8_t scsi_csr_1; 76 uint8_t scsi_csr_2; 77 }; 78 79 #define TYPE_NEXT_PC "next-pc" 80 OBJECT_DECLARE_SIMPLE_TYPE(NeXTPC, NEXT_PC) 81 82 /* NeXT Peripheral Controller */ 83 struct NeXTPC { 84 SysBusDevice parent_obj; 85 86 M68kCPU *cpu; 87 88 MemoryRegion floppy_mem; 89 MemoryRegion timer_mem; 90 MemoryRegion dummyen_mem; 91 MemoryRegion mmiomem; 92 MemoryRegion scrmem; 93 94 uint32_t scr1; 95 uint32_t scr2; 96 uint32_t old_scr2; 97 uint32_t int_mask; 98 uint32_t int_status; 99 uint32_t led; 100 101 NeXTSCSI next_scsi; 102 103 qemu_irq scsi_reset; 104 qemu_irq scsi_dma; 105 106 ESCCState escc; 107 108 NeXTRTC rtc; 109 qemu_irq rtc_power_irq; 110 qemu_irq rtc_data_irq; 111 }; 112 113 typedef struct next_dma { 114 uint32_t csr; 115 116 uint32_t saved_next; 117 uint32_t saved_limit; 118 uint32_t saved_start; 119 uint32_t saved_stop; 120 121 uint32_t next; 122 uint32_t limit; 123 uint32_t start; 124 uint32_t stop; 125 126 uint32_t next_initbuf; 127 uint32_t size; 128 } next_dma; 129 130 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube") 131 OBJECT_DECLARE_SIMPLE_TYPE(NeXTState, NEXT_MACHINE) 132 133 struct NeXTState { 134 MachineState parent; 135 136 MemoryRegion rom; 137 MemoryRegion rom2; 138 MemoryRegion dmamem; 139 MemoryRegion bmapm1; 140 MemoryRegion bmapm2; 141 142 next_dma dma[10]; 143 }; 144 145 /* Thanks to NeXT forums for this */ 146 /* 147 static const uint8_t rtc_ram3[32] = { 148 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 149 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00, 150 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00, 151 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13 152 }; 153 */ 154 static const uint8_t rtc_ram2[32] = { 155 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00, 156 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00, 157 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 158 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e, 159 }; 160 161 #define SCR2_RTCLK 0x2 162 #define SCR2_RTDATA 0x4 163 #define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10)) 164 165 static void next_scr2_led_update(NeXTPC *s) 166 { 167 if (s->scr2 & 0x1) { 168 DPRINTF("fault!\n"); 169 s->led++; 170 if (s->led == 10) { 171 DPRINTF("LED flashing, possible fault!\n"); 172 s->led = 0; 173 } 174 } 175 } 176 177 static bool next_rtc_cmd_is_write(uint8_t cmd) 178 { 179 return (cmd >= 0x80 && cmd <= 0x9f) || 180 (cmd == 0xb1); 181 } 182 183 static void next_rtc_data_in_irq(void *opaque, int n, int level) 184 { 185 NeXTRTC *rtc = NEXT_RTC(opaque); 186 NeXTPC *s = NEXT_PC(container_of(rtc, NeXTPC, rtc)); 187 188 if (rtc->phase < 8) { 189 rtc->command = (rtc->command << 1) | level; 190 191 if (rtc->phase == 7 && !next_rtc_cmd_is_write(rtc->command)) { 192 if (rtc->command <= 0x1f) { 193 /* RAM registers */ 194 rtc->retval = rtc->ram[rtc->command]; 195 } 196 if ((rtc->command >= 0x20) && (rtc->command <= 0x2f)) { 197 /* RTC */ 198 time_t time_h = time(NULL); 199 struct tm *info = localtime(&time_h); 200 rtc->retval = 0; 201 202 switch (rtc->command) { 203 case 0x20: 204 rtc->retval = SCR2_TOBCD(info->tm_sec); 205 break; 206 case 0x21: 207 rtc->retval = SCR2_TOBCD(info->tm_min); 208 break; 209 case 0x22: 210 rtc->retval = SCR2_TOBCD(info->tm_hour); 211 break; 212 case 0x24: 213 rtc->retval = SCR2_TOBCD(info->tm_mday); 214 break; 215 case 0x25: 216 rtc->retval = SCR2_TOBCD((info->tm_mon + 1)); 217 break; 218 case 0x26: 219 rtc->retval = SCR2_TOBCD((info->tm_year - 100)); 220 break; 221 } 222 } 223 if (rtc->command == 0x30) { 224 /* read the status 0x30 */ 225 rtc->retval = rtc->status; 226 } 227 if (rtc->command == 0x31) { 228 /* read the control 0x31 */ 229 rtc->retval = rtc->control; 230 } 231 } 232 } 233 if (rtc->phase >= 8 && rtc->phase < 16) { 234 if (next_rtc_cmd_is_write(rtc->command)) { 235 /* Shift in value to write */ 236 rtc->value = (rtc->value << 1) | level; 237 } else { 238 /* Shift out value to read */ 239 if (rtc->retval & (0x80 >> (rtc->phase - 8))) { 240 qemu_irq_raise(rtc->data_out_irq); 241 } else { 242 qemu_irq_lower(rtc->data_out_irq); 243 } 244 } 245 } 246 247 rtc->phase++; 248 if (rtc->phase == 16 && next_rtc_cmd_is_write(rtc->command)) { 249 if (rtc->command >= 0x80 && rtc->command <= 0x9f) { 250 /* RAM registers */ 251 rtc->ram[rtc->command - 0x80] = rtc->value; 252 } 253 if (rtc->command == 0xb1) { 254 /* write to 0x30 register */ 255 if (rtc->value & 0x04) { 256 /* clear FTU */ 257 rtc->status = rtc->status & (~0x18); 258 qemu_irq_lower(s->rtc_power_irq); 259 } 260 } 261 } 262 } 263 264 static void next_scr2_rtc_update(NeXTPC *s) 265 { 266 uint8_t old_scr2, scr2_2; 267 NeXTRTC *rtc = &s->rtc; 268 269 old_scr2 = extract32(s->old_scr2, 8, 8); 270 scr2_2 = extract32(s->scr2, 8, 8); 271 272 if (scr2_2 & 0x1) { 273 /* DPRINTF("RTC %x phase %i\n", scr2_2, rtc->phase); */ 274 /* If we are in going down clock... do something */ 275 if (((old_scr2 & SCR2_RTCLK) != (scr2_2 & SCR2_RTCLK)) && 276 ((scr2_2 & SCR2_RTCLK) == 0)) { 277 if (scr2_2 & SCR2_RTDATA) { 278 qemu_irq_raise(s->rtc_data_irq); 279 } else { 280 qemu_irq_lower(s->rtc_data_irq); 281 } 282 } 283 } else { 284 /* else end or abort */ 285 rtc->phase = 0; 286 rtc->command = 0; 287 rtc->value = 0; 288 } 289 } 290 291 static uint64_t next_mmio_read(void *opaque, hwaddr addr, unsigned size) 292 { 293 NeXTPC *s = NEXT_PC(opaque); 294 uint64_t val; 295 296 switch (addr) { 297 case 0x2000: /* 0x2007000 */ 298 /* DPRINTF("Read INT status: %x\n", s->int_status); */ 299 val = s->int_status; 300 break; 301 302 case 0x2800: /* 0x2007800 */ 303 DPRINTF("MMIO Read INT mask: %x\n", s->int_mask); 304 val = s->int_mask; 305 break; 306 307 case 0x7000 ... 0x7003: /* 0x200c000 */ 308 val = extract32(s->scr1, (4 - (addr - 0x7000) - size) << 3, 309 size << 3); 310 break; 311 312 case 0x8000 ... 0x8003: /* 0x200d000 */ 313 val = extract32(s->scr2, (4 - (addr - 0x8000) - size) << 3, 314 size << 3); 315 break; 316 317 default: 318 val = 0; 319 DPRINTF("MMIO Read @ 0x%"HWADDR_PRIx" size %d\n", addr, size); 320 break; 321 } 322 323 return val; 324 } 325 326 static void next_mmio_write(void *opaque, hwaddr addr, uint64_t val, 327 unsigned size) 328 { 329 NeXTPC *s = NEXT_PC(opaque); 330 331 switch (addr) { 332 case 0x2000: /* 0x2007000 */ 333 DPRINTF("INT Status old: %x new: %x\n", s->int_status, 334 (unsigned int)val); 335 s->int_status = val; 336 break; 337 338 case 0x2800: /* 0x2007800 */ 339 DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, (unsigned int)val); 340 s->int_mask = val; 341 break; 342 343 case 0x7000 ... 0x7003: /* 0x200c000 */ 344 DPRINTF("SCR1 Write: %x\n", (unsigned int)val); 345 s->scr1 = deposit32(s->scr1, (4 - (addr - 0x7000) - size) << 3, 346 size << 3, val); 347 break; 348 349 case 0x8000 ... 0x8003: /* 0x200d000 */ 350 s->scr2 = deposit32(s->scr2, (4 - (addr - 0x8000) - size) << 3, 351 size << 3, val); 352 next_scr2_led_update(s); 353 next_scr2_rtc_update(s); 354 s->old_scr2 = s->scr2; 355 break; 356 357 default: 358 DPRINTF("MMIO Write @ 0x%"HWADDR_PRIx " with 0x%x size %u\n", addr, 359 (unsigned int)val, size); 360 } 361 } 362 363 static const MemoryRegionOps next_mmio_ops = { 364 .read = next_mmio_read, 365 .write = next_mmio_write, 366 .valid.min_access_size = 1, 367 .valid.max_access_size = 4, 368 .endianness = DEVICE_BIG_ENDIAN, 369 }; 370 371 #define SCSICSR_ENABLE 0x01 372 #define SCSICSR_RESET 0x02 /* reset scsi dma */ 373 #define SCSICSR_FIFOFL 0x04 374 #define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */ 375 #define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */ 376 #define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */ 377 378 #define NEXTDMA_SCSI(x) (0x10 + x) 379 #define NEXTDMA_FD(x) (0x10 + x) 380 #define NEXTDMA_ENTX(x) (0x110 + x) 381 #define NEXTDMA_ENRX(x) (0x150 + x) 382 #define NEXTDMA_CSR 0x0 383 #define NEXTDMA_NEXT 0x4000 384 #define NEXTDMA_LIMIT 0x4004 385 #define NEXTDMA_START 0x4008 386 #define NEXTDMA_STOP 0x400c 387 #define NEXTDMA_NEXT_INIT 0x4200 388 #define NEXTDMA_SIZE 0x4204 389 390 static void next_dma_write(void *opaque, hwaddr addr, uint64_t val, 391 unsigned int size) 392 { 393 NeXTState *next_state = NEXT_MACHINE(opaque); 394 395 switch (addr) { 396 case NEXTDMA_ENRX(NEXTDMA_CSR): 397 if (val & DMA_DEV2M) { 398 next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M; 399 } 400 401 if (val & DMA_SETENABLE) { 402 /* DPRINTF("SCSI DMA ENABLE\n"); */ 403 next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE; 404 } 405 if (val & DMA_SETSUPDATE) { 406 next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE; 407 } 408 if (val & DMA_CLRCOMPLETE) { 409 next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE; 410 } 411 412 if (val & DMA_RESET) { 413 next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 414 DMA_ENABLE | DMA_DEV2M); 415 } 416 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 417 break; 418 419 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 420 next_state->dma[NEXTDMA_ENRX].next_initbuf = val; 421 break; 422 423 case NEXTDMA_ENRX(NEXTDMA_NEXT): 424 next_state->dma[NEXTDMA_ENRX].next = val; 425 break; 426 427 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 428 next_state->dma[NEXTDMA_ENRX].limit = val; 429 break; 430 431 case NEXTDMA_SCSI(NEXTDMA_CSR): 432 if (val & DMA_DEV2M) { 433 next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M; 434 } 435 if (val & DMA_SETENABLE) { 436 /* DPRINTF("SCSI DMA ENABLE\n"); */ 437 next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE; 438 } 439 if (val & DMA_SETSUPDATE) { 440 next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE; 441 } 442 if (val & DMA_CLRCOMPLETE) { 443 next_state->dma[NEXTDMA_SCSI].csr &= ~DMA_COMPLETE; 444 } 445 446 if (val & DMA_RESET) { 447 next_state->dma[NEXTDMA_SCSI].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 448 DMA_ENABLE | DMA_DEV2M); 449 /* DPRINTF("SCSI DMA RESET\n"); */ 450 } 451 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 452 break; 453 454 case NEXTDMA_SCSI(NEXTDMA_NEXT): 455 next_state->dma[NEXTDMA_SCSI].next = val; 456 break; 457 458 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 459 next_state->dma[NEXTDMA_SCSI].limit = val; 460 break; 461 462 case NEXTDMA_SCSI(NEXTDMA_START): 463 next_state->dma[NEXTDMA_SCSI].start = val; 464 break; 465 466 case NEXTDMA_SCSI(NEXTDMA_STOP): 467 next_state->dma[NEXTDMA_SCSI].stop = val; 468 break; 469 470 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 471 next_state->dma[NEXTDMA_SCSI].next_initbuf = val; 472 break; 473 474 default: 475 DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)val); 476 } 477 } 478 479 static uint64_t next_dma_read(void *opaque, hwaddr addr, unsigned int size) 480 { 481 NeXTState *next_state = NEXT_MACHINE(opaque); 482 uint64_t val; 483 484 switch (addr) { 485 case NEXTDMA_SCSI(NEXTDMA_CSR): 486 DPRINTF("SCSI DMA CSR READ\n"); 487 val = next_state->dma[NEXTDMA_SCSI].csr; 488 break; 489 490 case NEXTDMA_ENRX(NEXTDMA_CSR): 491 val = next_state->dma[NEXTDMA_ENRX].csr; 492 break; 493 494 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 495 val = next_state->dma[NEXTDMA_ENRX].next_initbuf; 496 break; 497 498 case NEXTDMA_ENRX(NEXTDMA_NEXT): 499 val = next_state->dma[NEXTDMA_ENRX].next; 500 break; 501 502 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 503 val = next_state->dma[NEXTDMA_ENRX].limit; 504 break; 505 506 case NEXTDMA_SCSI(NEXTDMA_NEXT): 507 val = next_state->dma[NEXTDMA_SCSI].next; 508 break; 509 510 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 511 val = next_state->dma[NEXTDMA_SCSI].next_initbuf; 512 break; 513 514 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 515 val = next_state->dma[NEXTDMA_SCSI].limit; 516 break; 517 518 case NEXTDMA_SCSI(NEXTDMA_START): 519 val = next_state->dma[NEXTDMA_SCSI].start; 520 break; 521 522 case NEXTDMA_SCSI(NEXTDMA_STOP): 523 val = next_state->dma[NEXTDMA_SCSI].stop; 524 break; 525 526 default: 527 DPRINTF("DMA read @ %x\n", (unsigned int)addr); 528 val = 0; 529 } 530 531 /* 532 * once the csr's are done, subtract 0x3FEC from the addr, and that will 533 * normalize the upper registers 534 */ 535 536 return val; 537 } 538 539 static const MemoryRegionOps next_dma_ops = { 540 .read = next_dma_read, 541 .write = next_dma_write, 542 .impl.min_access_size = 4, 543 .valid.min_access_size = 4, 544 .valid.max_access_size = 4, 545 .endianness = DEVICE_BIG_ENDIAN, 546 }; 547 548 static void next_irq(void *opaque, int number, int level) 549 { 550 NeXTPC *s = NEXT_PC(opaque); 551 M68kCPU *cpu = s->cpu; 552 int shift = 0; 553 554 /* first switch sets interrupt status */ 555 /* DPRINTF("IRQ %i\n",number); */ 556 switch (number) { 557 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 558 case NEXT_FD_I: 559 shift = 7; 560 break; 561 case NEXT_KBD_I: 562 shift = 3; 563 break; 564 case NEXT_PWR_I: 565 shift = 2; 566 break; 567 case NEXT_ENRX_I: 568 shift = 9; 569 break; 570 case NEXT_ENTX_I: 571 shift = 10; 572 break; 573 case NEXT_SCSI_I: 574 shift = 12; 575 break; 576 case NEXT_CLK_I: 577 shift = 5; 578 break; 579 580 /* level 5 - scc (serial) */ 581 case NEXT_SCC_I: 582 shift = 17; 583 break; 584 585 /* level 6 - audio etherrx/tx dma */ 586 case NEXT_ENTX_DMA_I: 587 shift = 28; 588 break; 589 case NEXT_ENRX_DMA_I: 590 shift = 27; 591 break; 592 case NEXT_SCSI_DMA_I: 593 shift = 26; 594 break; 595 case NEXT_SND_I: 596 shift = 23; 597 break; 598 case NEXT_SCC_DMA_I: 599 shift = 21; 600 break; 601 602 } 603 /* 604 * this HAS to be wrong, the interrupt handlers in mach and together 605 * int_status and int_mask and return if there is a hit 606 */ 607 if (s->int_mask & (1 << shift)) { 608 DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc); 609 /* return; */ 610 } 611 612 /* second switch triggers the correct interrupt */ 613 if (level) { 614 s->int_status |= 1 << shift; 615 616 switch (number) { 617 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 618 case NEXT_FD_I: 619 case NEXT_KBD_I: 620 case NEXT_PWR_I: 621 case NEXT_ENRX_I: 622 case NEXT_ENTX_I: 623 case NEXT_SCSI_I: 624 case NEXT_CLK_I: 625 m68k_set_irq_level(cpu, 3, 27); 626 break; 627 628 /* level 5 - scc (serial) */ 629 case NEXT_SCC_I: 630 m68k_set_irq_level(cpu, 5, 29); 631 break; 632 633 /* level 6 - audio etherrx/tx dma */ 634 case NEXT_ENTX_DMA_I: 635 case NEXT_ENRX_DMA_I: 636 case NEXT_SCSI_DMA_I: 637 case NEXT_SND_I: 638 case NEXT_SCC_DMA_I: 639 m68k_set_irq_level(cpu, 6, 30); 640 break; 641 } 642 } else { 643 s->int_status &= ~(1 << shift); 644 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); 645 } 646 } 647 648 static void nextdma_write(void *opaque, uint8_t *buf, int size, int type) 649 { 650 uint32_t base_addr; 651 int irq = 0; 652 uint8_t align = 16; 653 NeXTState *next_state = NEXT_MACHINE(qdev_get_machine()); 654 655 if (type == NEXTDMA_ENRX || type == NEXTDMA_ENTX) { 656 align = 32; 657 } 658 /* Most DMA is supposedly 16 byte aligned */ 659 if ((size % align) != 0) { 660 size -= size % align; 661 size += align; 662 } 663 664 /* 665 * prom sets the dma start using initbuf while the bootloader uses next 666 * so we check to see if initbuf is 0 667 */ 668 if (next_state->dma[type].next_initbuf == 0) { 669 base_addr = next_state->dma[type].next; 670 } else { 671 base_addr = next_state->dma[type].next_initbuf; 672 } 673 674 cpu_physical_memory_write(base_addr, buf, size); 675 676 next_state->dma[type].next_initbuf = 0; 677 678 /* saved limit is checked to calculate packet size by both, rom and netbsd */ 679 next_state->dma[type].saved_limit = (next_state->dma[type].next + size); 680 next_state->dma[type].saved_next = (next_state->dma[type].next); 681 682 /* 683 * 32 bytes under savedbase seems to be some kind of register 684 * of which the purpose is unknown as of yet 685 */ 686 /* stl_phys(s->rx_dma.base-32,0xFFFFFFFF); */ 687 688 if (!(next_state->dma[type].csr & DMA_SUPDATE)) { 689 next_state->dma[type].next = next_state->dma[type].start; 690 next_state->dma[type].limit = next_state->dma[type].stop; 691 } 692 693 /* Set dma registers and raise an irq */ 694 next_state->dma[type].csr |= DMA_COMPLETE; /* DON'T CHANGE THIS! */ 695 696 switch (type) { 697 case NEXTDMA_SCSI: 698 irq = NEXT_SCSI_DMA_I; 699 break; 700 } 701 702 next_irq(opaque, irq, 1); 703 next_irq(opaque, irq, 0); 704 } 705 706 static void nextscsi_read(void *opaque, uint8_t *buf, int len) 707 { 708 DPRINTF("SCSI READ: %x\n", len); 709 abort(); 710 } 711 712 static void nextscsi_write(void *opaque, uint8_t *buf, int size) 713 { 714 DPRINTF("SCSI WRITE: %i\n", size); 715 nextdma_write(opaque, buf, size, NEXTDMA_SCSI); 716 } 717 718 static void next_scsi_csr_write(void *opaque, hwaddr addr, uint64_t val, 719 unsigned size) 720 { 721 NeXTSCSI *s = NEXT_SCSI(opaque); 722 NeXTPC *pc = NEXT_PC(container_of(s, NeXTPC, next_scsi)); 723 724 switch (addr) { 725 case 0: 726 if (val & SCSICSR_FIFOFL) { 727 DPRINTF("SCSICSR FIFO Flush\n"); 728 /* will have to add another irq to the esp if this is needed */ 729 /* esp_puflush_fifo(esp_g); */ 730 } 731 732 if (val & SCSICSR_ENABLE) { 733 DPRINTF("SCSICSR Enable\n"); 734 /* 735 * qemu_irq_raise(s->scsi_dma); 736 * s->scsi_csr_1 = 0xc0; 737 * s->scsi_csr_1 |= 0x1; 738 * qemu_irq_pulse(s->scsi_dma); 739 */ 740 } 741 /* 742 * else 743 * s->scsi_csr_1 &= ~SCSICSR_ENABLE; 744 */ 745 746 if (val & SCSICSR_RESET) { 747 DPRINTF("SCSICSR Reset\n"); 748 /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */ 749 qemu_irq_raise(pc->scsi_reset); 750 s->scsi_csr_1 &= ~(SCSICSR_INTMASK | 0x80 | 0x1); 751 qemu_irq_lower(pc->scsi_reset); 752 } 753 if (val & SCSICSR_DMADIR) { 754 DPRINTF("SCSICSR DMAdir\n"); 755 } 756 if (val & SCSICSR_CPUDMA) { 757 DPRINTF("SCSICSR CPUDMA\n"); 758 /* qemu_irq_raise(s->scsi_dma); */ 759 pc->int_status |= 0x4000000; 760 } else { 761 /* fprintf(stderr,"SCSICSR CPUDMA disabled\n"); */ 762 pc->int_status &= ~(0x4000000); 763 /* qemu_irq_lower(s->scsi_dma); */ 764 } 765 if (val & SCSICSR_INTMASK) { 766 DPRINTF("SCSICSR INTMASK\n"); 767 /* 768 * int_mask &= ~0x1000; 769 * s->scsi_csr_1 |= val; 770 * s->scsi_csr_1 &= ~SCSICSR_INTMASK; 771 * if (s->scsi_queued) { 772 * s->scsi_queued = 0; 773 * next_irq(s, NEXT_SCSI_I, level); 774 * } 775 */ 776 } else { 777 /* int_mask |= 0x1000; */ 778 } 779 if (val & 0x80) { 780 /* int_mask |= 0x1000; */ 781 /* s->scsi_csr_1 |= 0x80; */ 782 } 783 DPRINTF("SCSICSR1 Write: %"PRIx64 "\n", val); 784 s->scsi_csr_1 = val; 785 break; 786 787 case 1: 788 DPRINTF("SCSICSR2 Write: %"PRIx64 "\n", val); 789 s->scsi_csr_2 = val; 790 break; 791 792 default: 793 g_assert_not_reached(); 794 } 795 } 796 797 static uint64_t next_scsi_csr_read(void *opaque, hwaddr addr, unsigned size) 798 { 799 NeXTSCSI *s = NEXT_SCSI(opaque); 800 uint64_t val; 801 802 switch (addr) { 803 case 0: 804 DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1); 805 val = s->scsi_csr_1; 806 break; 807 808 case 1: 809 DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2); 810 val = s->scsi_csr_2; 811 break; 812 813 default: 814 g_assert_not_reached(); 815 } 816 817 return val; 818 } 819 820 static const MemoryRegionOps next_scsi_csr_ops = { 821 .read = next_scsi_csr_read, 822 .write = next_scsi_csr_write, 823 .valid.min_access_size = 1, 824 .valid.max_access_size = 1, 825 .endianness = DEVICE_BIG_ENDIAN, 826 }; 827 828 static void next_scsi_init(Object *obj) 829 { 830 NeXTSCSI *s = NEXT_SCSI(obj); 831 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 832 833 object_initialize_child(obj, "esp", &s->sysbus_esp, TYPE_SYSBUS_ESP); 834 835 memory_region_init_io(&s->scsi_csr_mem, obj, &next_scsi_csr_ops, 836 s, "csrs", 2); 837 838 memory_region_init(&s->scsi_mem, obj, "next.scsi", 0x40); 839 sysbus_init_mmio(sbd, &s->scsi_mem); 840 } 841 842 static void next_scsi_realize(DeviceState *dev, Error **errp) 843 { 844 NeXTSCSI *s = NEXT_SCSI(dev); 845 SysBusESPState *sysbus_esp; 846 SysBusDevice *sbd; 847 ESPState *esp; 848 NeXTPC *pcdev; 849 850 pcdev = NEXT_PC(container_of(s, NeXTPC, next_scsi)); 851 852 /* ESP */ 853 sysbus_esp = SYSBUS_ESP(&s->sysbus_esp); 854 esp = &sysbus_esp->esp; 855 esp->dma_memory_read = nextscsi_read; 856 esp->dma_memory_write = nextscsi_write; 857 esp->dma_opaque = pcdev; 858 sysbus_esp->it_shift = 0; 859 esp->dma_enabled = 1; 860 sbd = SYS_BUS_DEVICE(sysbus_esp); 861 if (!sysbus_realize(sbd, errp)) { 862 return; 863 } 864 memory_region_add_subregion(&s->scsi_mem, 0x0, 865 sysbus_mmio_get_region(sbd, 0)); 866 867 /* SCSI CSRs */ 868 memory_region_add_subregion(&s->scsi_mem, 0x20, &s->scsi_csr_mem); 869 870 scsi_bus_legacy_handle_cmdline(&s->sysbus_esp.esp.bus); 871 } 872 873 static const VMStateDescription next_scsi_vmstate = { 874 .name = "next-scsi", 875 .version_id = 0, 876 .minimum_version_id = 0, 877 .fields = (const VMStateField[]) { 878 VMSTATE_UINT8(scsi_csr_1, NeXTSCSI), 879 VMSTATE_UINT8(scsi_csr_2, NeXTSCSI), 880 VMSTATE_END_OF_LIST() 881 }, 882 }; 883 884 static void next_scsi_class_init(ObjectClass *klass, void *data) 885 { 886 DeviceClass *dc = DEVICE_CLASS(klass); 887 888 dc->desc = "NeXT SCSI Controller"; 889 dc->realize = next_scsi_realize; 890 dc->vmsd = &next_scsi_vmstate; 891 } 892 893 static const TypeInfo next_scsi_info = { 894 .name = TYPE_NEXT_SCSI, 895 .parent = TYPE_SYS_BUS_DEVICE, 896 .instance_init = next_scsi_init, 897 .instance_size = sizeof(NeXTSCSI), 898 .class_init = next_scsi_class_init, 899 }; 900 901 static void next_floppy_write(void *opaque, hwaddr addr, uint64_t val, 902 unsigned size) 903 { 904 switch (addr) { 905 case 0: 906 DPRINTF("FDCSR Write: %"PRIx64 "\n", val); 907 if (val == 0x0) { 908 /* qemu_irq_raise(s->fd_irq[0]); */ 909 } 910 break; 911 912 default: 913 g_assert_not_reached(); 914 } 915 } 916 917 static uint64_t next_floppy_read(void *opaque, hwaddr addr, unsigned size) 918 { 919 uint64_t val; 920 921 switch (addr) { 922 case 0: 923 DPRINTF("FD read @ %x\n", (unsigned int)addr); 924 val = 0x40 | 0x04 | 0x2 | 0x1; 925 break; 926 927 default: 928 g_assert_not_reached(); 929 } 930 931 return val; 932 } 933 934 static const MemoryRegionOps next_floppy_ops = { 935 .read = next_floppy_read, 936 .write = next_floppy_write, 937 .valid.min_access_size = 1, 938 .valid.max_access_size = 4, 939 .endianness = DEVICE_BIG_ENDIAN, 940 }; 941 942 static void next_timer_write(void *opaque, hwaddr addr, uint64_t val, 943 unsigned size) 944 { 945 switch (addr) { 946 case 0 ... 3: 947 /* Hardware timer latch - not implemented yet */ 948 break; 949 950 default: 951 g_assert_not_reached(); 952 } 953 } 954 955 static uint64_t next_timer_read(void *opaque, hwaddr addr, unsigned size) 956 { 957 uint64_t val; 958 959 switch (addr) { 960 case 0 ... 3: 961 /* 962 * These 4 registers are the hardware timer, not sure which register 963 * is the latch instead of data, but no problems so far. 964 * 965 * Hack: We need to have the LSB change consistently to make it work 966 */ 967 val = extract32(clock(), (4 - addr - size) << 3, 968 size << 3); 969 break; 970 971 default: 972 g_assert_not_reached(); 973 } 974 975 return val; 976 } 977 978 static const MemoryRegionOps next_timer_ops = { 979 .read = next_timer_read, 980 .write = next_timer_write, 981 .valid.min_access_size = 1, 982 .valid.max_access_size = 4, 983 .endianness = DEVICE_BIG_ENDIAN, 984 }; 985 986 static void next_dummy_en_write(void *opaque, hwaddr addr, uint64_t val, 987 unsigned size) 988 { 989 /* Do nothing */ 990 return; 991 } 992 993 static uint64_t next_dummy_en_read(void *opaque, hwaddr addr, unsigned size) 994 { 995 uint64_t val; 996 997 switch (addr) { 998 case 0: 999 /* For now return dummy byte to allow the Ethernet test to timeout */ 1000 val = 0xff; 1001 break; 1002 1003 default: 1004 val = 0; 1005 } 1006 1007 return val; 1008 } 1009 1010 static const MemoryRegionOps next_dummy_en_ops = { 1011 .read = next_dummy_en_read, 1012 .write = next_dummy_en_write, 1013 .valid.min_access_size = 1, 1014 .valid.max_access_size = 4, 1015 .endianness = DEVICE_BIG_ENDIAN, 1016 }; 1017 1018 static void next_rtc_reset_hold(Object *obj, ResetType type) 1019 { 1020 NeXTRTC *rtc = NEXT_RTC(obj); 1021 1022 rtc->status = 0x90; 1023 1024 /* Load RTC RAM - TODO: provide possibility to load contents from file */ 1025 memcpy(rtc->ram, rtc_ram2, 32); 1026 } 1027 1028 static void next_rtc_init(Object *obj) 1029 { 1030 NeXTRTC *rtc = NEXT_RTC(obj); 1031 1032 qdev_init_gpio_in_named(DEVICE(obj), next_rtc_data_in_irq, 1033 "rtc-data-in", 1); 1034 qdev_init_gpio_out_named(DEVICE(obj), &rtc->data_out_irq, 1035 "rtc-data-out", 1); 1036 } 1037 1038 static const VMStateDescription next_rtc_vmstate = { 1039 .name = "next-rtc", 1040 .version_id = 3, 1041 .minimum_version_id = 3, 1042 .fields = (const VMStateField[]) { 1043 VMSTATE_INT8(phase, NeXTRTC), 1044 VMSTATE_UINT8_ARRAY(ram, NeXTRTC, 32), 1045 VMSTATE_UINT8(command, NeXTRTC), 1046 VMSTATE_UINT8(value, NeXTRTC), 1047 VMSTATE_UINT8(status, NeXTRTC), 1048 VMSTATE_UINT8(control, NeXTRTC), 1049 VMSTATE_UINT8(retval, NeXTRTC), 1050 VMSTATE_END_OF_LIST() 1051 }, 1052 }; 1053 1054 static void next_rtc_class_init(ObjectClass *klass, void *data) 1055 { 1056 DeviceClass *dc = DEVICE_CLASS(klass); 1057 ResettableClass *rc = RESETTABLE_CLASS(klass); 1058 1059 dc->desc = "NeXT RTC"; 1060 dc->vmsd = &next_rtc_vmstate; 1061 rc->phases.hold = next_rtc_reset_hold; 1062 } 1063 1064 static const TypeInfo next_rtc_info = { 1065 .name = TYPE_NEXT_RTC, 1066 .parent = TYPE_SYS_BUS_DEVICE, 1067 .instance_init = next_rtc_init, 1068 .instance_size = sizeof(NeXTRTC), 1069 .class_init = next_rtc_class_init, 1070 }; 1071 1072 static void next_pc_rtc_data_in_irq(void *opaque, int n, int level) 1073 { 1074 NeXTPC *s = NEXT_PC(opaque); 1075 uint8_t scr2_2 = extract32(s->scr2, 8, 8); 1076 1077 if (level) { 1078 scr2_2 |= SCR2_RTDATA; 1079 } else { 1080 scr2_2 &= ~SCR2_RTDATA; 1081 } 1082 1083 s->scr2 = deposit32(s->scr2, 8, 8, scr2_2); 1084 } 1085 1086 static void next_pc_reset_hold(Object *obj, ResetType type) 1087 { 1088 NeXTPC *s = NEXT_PC(obj); 1089 1090 /* Set internal registers to initial values */ 1091 /* 0x0000XX00 << vital bits */ 1092 s->scr1 = 0x00011102; 1093 s->scr2 = 0x00ff0c80; 1094 s->old_scr2 = s->scr2; 1095 } 1096 1097 static void next_pc_realize(DeviceState *dev, Error **errp) 1098 { 1099 NeXTPC *s = NEXT_PC(dev); 1100 SysBusDevice *sbd; 1101 DeviceState *d; 1102 1103 /* SCSI */ 1104 sbd = SYS_BUS_DEVICE(&s->next_scsi); 1105 if (!sysbus_realize(sbd, errp)) { 1106 return; 1107 } 1108 1109 d = DEVICE(object_resolve_path_component(OBJECT(&s->next_scsi), "esp")); 1110 sysbus_connect_irq(SYS_BUS_DEVICE(d), 0, 1111 qdev_get_gpio_in(DEVICE(s), NEXT_SCSI_I)); 1112 1113 s->scsi_reset = qdev_get_gpio_in(d, 0); 1114 s->scsi_dma = qdev_get_gpio_in(d, 1); 1115 1116 /* ESCC */ 1117 d = DEVICE(&s->escc); 1118 qdev_prop_set_uint32(d, "disabled", 0); 1119 qdev_prop_set_uint32(d, "frequency", 9600 * 384); 1120 qdev_prop_set_uint32(d, "it_shift", 0); 1121 qdev_prop_set_bit(d, "bit_swap", true); 1122 qdev_prop_set_chr(d, "chrB", serial_hd(1)); 1123 qdev_prop_set_chr(d, "chrA", serial_hd(0)); 1124 qdev_prop_set_uint32(d, "chnBtype", escc_serial); 1125 qdev_prop_set_uint32(d, "chnAtype", escc_serial); 1126 1127 sbd = SYS_BUS_DEVICE(d); 1128 if (!sysbus_realize(sbd, errp)) { 1129 return; 1130 } 1131 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(dev, NEXT_SCC_I)); 1132 sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(dev, NEXT_SCC_DMA_I)); 1133 1134 /* RTC */ 1135 d = DEVICE(&s->rtc); 1136 if (!sysbus_realize(SYS_BUS_DEVICE(d), errp)) { 1137 return; 1138 } 1139 /* Data from NeXTPC to RTC */ 1140 qdev_connect_gpio_out_named(dev, "rtc-data-out", 0, 1141 qdev_get_gpio_in_named(d, "rtc-data-in", 0)); 1142 /* Data from RTC to NeXTPC */ 1143 qdev_connect_gpio_out_named(d, "rtc-data-out", 0, 1144 qdev_get_gpio_in_named(dev, 1145 "rtc-data-in", 0)); 1146 } 1147 1148 static void next_pc_init(Object *obj) 1149 { 1150 NeXTPC *s = NEXT_PC(obj); 1151 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1152 1153 qdev_init_gpio_in(DEVICE(obj), next_irq, NEXT_NUM_IRQS); 1154 1155 memory_region_init_io(&s->mmiomem, OBJECT(s), &next_mmio_ops, s, 1156 "next.mmio", 0x9000); 1157 sysbus_init_mmio(sbd, &s->mmiomem); 1158 1159 memory_region_init_io(&s->dummyen_mem, OBJECT(s), &next_dummy_en_ops, s, 1160 "next.en", 0x20); 1161 sysbus_init_mmio(sbd, &s->dummyen_mem); 1162 1163 object_initialize_child(obj, "next-scsi", &s->next_scsi, TYPE_NEXT_SCSI); 1164 sysbus_init_mmio(sbd, 1165 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->next_scsi), 0)); 1166 1167 memory_region_init_io(&s->floppy_mem, OBJECT(s), &next_floppy_ops, s, 1168 "next.floppy", 4); 1169 sysbus_init_mmio(sbd, &s->floppy_mem); 1170 1171 object_initialize_child(obj, "escc", &s->escc, TYPE_ESCC); 1172 sysbus_init_mmio(sbd, 1173 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->escc), 0)); 1174 1175 memory_region_init_io(&s->timer_mem, OBJECT(s), &next_timer_ops, s, 1176 "next.timer", 4); 1177 sysbus_init_mmio(sbd, &s->timer_mem); 1178 1179 object_initialize_child(obj, "rtc", &s->rtc, TYPE_NEXT_RTC); 1180 1181 s->rtc_power_irq = qdev_get_gpio_in(DEVICE(obj), NEXT_PWR_I); 1182 qdev_init_gpio_in_named(DEVICE(obj), next_pc_rtc_data_in_irq, 1183 "rtc-data-in", 1); 1184 qdev_init_gpio_out_named(DEVICE(obj), &s->rtc_data_irq, 1185 "rtc-data-out", 1); 1186 } 1187 1188 /* 1189 * If the m68k CPU implemented its inbound irq lines as GPIO lines 1190 * rather than via the m68k_set_irq_level() function we would not need 1191 * this cpu link property and could instead provide outbound IRQ lines 1192 * that the board could wire up to the CPU. 1193 */ 1194 static const Property next_pc_properties[] = { 1195 DEFINE_PROP_LINK("cpu", NeXTPC, cpu, TYPE_M68K_CPU, M68kCPU *), 1196 }; 1197 1198 static const VMStateDescription next_pc_vmstate = { 1199 .name = "next-pc", 1200 .version_id = 4, 1201 .minimum_version_id = 4, 1202 .fields = (const VMStateField[]) { 1203 VMSTATE_UINT32(scr1, NeXTPC), 1204 VMSTATE_UINT32(scr2, NeXTPC), 1205 VMSTATE_UINT32(old_scr2, NeXTPC), 1206 VMSTATE_UINT32(int_mask, NeXTPC), 1207 VMSTATE_UINT32(int_status, NeXTPC), 1208 VMSTATE_UINT32(led, NeXTPC), 1209 VMSTATE_END_OF_LIST() 1210 }, 1211 }; 1212 1213 static void next_pc_class_init(ObjectClass *klass, void *data) 1214 { 1215 DeviceClass *dc = DEVICE_CLASS(klass); 1216 ResettableClass *rc = RESETTABLE_CLASS(klass); 1217 1218 dc->desc = "NeXT Peripheral Controller"; 1219 dc->realize = next_pc_realize; 1220 device_class_set_props(dc, next_pc_properties); 1221 dc->vmsd = &next_pc_vmstate; 1222 rc->phases.hold = next_pc_reset_hold; 1223 } 1224 1225 static const TypeInfo next_pc_info = { 1226 .name = TYPE_NEXT_PC, 1227 .parent = TYPE_SYS_BUS_DEVICE, 1228 .instance_init = next_pc_init, 1229 .instance_size = sizeof(NeXTPC), 1230 .class_init = next_pc_class_init, 1231 }; 1232 1233 static void next_cube_init(MachineState *machine) 1234 { 1235 NeXTState *m = NEXT_MACHINE(machine); 1236 M68kCPU *cpu; 1237 CPUM68KState *env; 1238 MemoryRegion *sysmem = get_system_memory(); 1239 const char *bios_name = machine->firmware ?: ROM_FILE; 1240 DeviceState *pcdev; 1241 1242 /* Initialize the cpu core */ 1243 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 1244 if (!cpu) { 1245 error_report("Unable to find m68k CPU definition"); 1246 exit(1); 1247 } 1248 env = &cpu->env; 1249 1250 /* Initialize CPU registers. */ 1251 env->vbr = 0; 1252 env->sr = 0x2700; 1253 1254 /* Peripheral Controller */ 1255 pcdev = qdev_new(TYPE_NEXT_PC); 1256 object_property_set_link(OBJECT(pcdev), "cpu", OBJECT(cpu), &error_abort); 1257 sysbus_realize_and_unref(SYS_BUS_DEVICE(pcdev), &error_fatal); 1258 1259 /* 64MB RAM starting at 0x04000000 */ 1260 memory_region_add_subregion(sysmem, 0x04000000, machine->ram); 1261 1262 /* Framebuffer */ 1263 sysbus_create_simple(TYPE_NEXTFB, 0x0B000000, NULL); 1264 1265 /* MMIO */ 1266 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02005000); 1267 1268 /* BMAP IO - acts as a catch-all for now */ 1269 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02100000); 1270 1271 /* en network (dummy) */ 1272 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02106000); 1273 1274 /* unknown: Brightness control register? */ 1275 empty_slot_init("next.unknown.0", 0x02110000, 0x10); 1276 /* unknown: Magneto-Optical drive controller? */ 1277 empty_slot_init("next.unknown.1", 0x02112000, 0x10); 1278 1279 /* SCSI */ 1280 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 2, 0x02114000); 1281 /* Floppy */ 1282 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 3, 0x02114108); 1283 /* ESCC */ 1284 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 4, 0x02118000); 1285 1286 /* unknown: Serial clock configuration register? */ 1287 empty_slot_init("next.unknown.2", 0x02118004, 0x10); 1288 1289 /* Timer */ 1290 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 5, 0x0211a000); 1291 1292 /* BMAP memory */ 1293 memory_region_init_ram_flags_nomigrate(&m->bmapm1, NULL, "next.bmapmem", 1294 64, RAM_SHARED, &error_fatal); 1295 memory_region_add_subregion(sysmem, 0x020c0000, &m->bmapm1); 1296 /* The Rev_2.5_v66.bin firmware accesses it at 0x820c0020, too */ 1297 memory_region_init_alias(&m->bmapm2, NULL, "next.bmapmem2", &m->bmapm1, 1298 0x0, 64); 1299 memory_region_add_subregion(sysmem, 0x820c0000, &m->bmapm2); 1300 1301 /* KBD */ 1302 sysbus_create_simple(TYPE_NEXTKBD, 0x0200e000, NULL); 1303 1304 /* Load ROM here */ 1305 memory_region_init_rom(&m->rom, NULL, "next.rom", 0x20000, &error_fatal); 1306 memory_region_add_subregion(sysmem, 0x01000000, &m->rom); 1307 memory_region_init_alias(&m->rom2, NULL, "next.rom2", &m->rom, 0x0, 1308 0x20000); 1309 memory_region_add_subregion(sysmem, 0x0, &m->rom2); 1310 if (load_image_targphys(bios_name, 0x01000000, 0x20000) < 8) { 1311 if (!qtest_enabled()) { 1312 error_report("Failed to load firmware '%s'.", bios_name); 1313 } 1314 } else { 1315 uint8_t *ptr; 1316 /* Initial PC is always at offset 4 in firmware binaries */ 1317 ptr = rom_ptr(0x01000004, 4); 1318 g_assert(ptr != NULL); 1319 env->pc = ldl_be_p(ptr); 1320 if (env->pc >= 0x01020000) { 1321 error_report("'%s' does not seem to be a valid firmware image.", 1322 bios_name); 1323 exit(1); 1324 } 1325 } 1326 1327 /* DMA */ 1328 memory_region_init_io(&m->dmamem, NULL, &next_dma_ops, machine, 1329 "next.dma", 0x5000); 1330 memory_region_add_subregion(sysmem, 0x02000000, &m->dmamem); 1331 } 1332 1333 static void next_machine_class_init(ObjectClass *oc, void *data) 1334 { 1335 MachineClass *mc = MACHINE_CLASS(oc); 1336 1337 mc->desc = "NeXT Cube"; 1338 mc->init = next_cube_init; 1339 mc->block_default_type = IF_SCSI; 1340 mc->default_ram_size = RAM_SIZE; 1341 mc->default_ram_id = "next.ram"; 1342 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); 1343 mc->no_cdrom = true; 1344 } 1345 1346 static const TypeInfo next_typeinfo = { 1347 .name = TYPE_NEXT_MACHINE, 1348 .parent = TYPE_MACHINE, 1349 .class_init = next_machine_class_init, 1350 .instance_size = sizeof(NeXTState), 1351 }; 1352 1353 static void next_register_type(void) 1354 { 1355 type_register_static(&next_typeinfo); 1356 type_register_static(&next_pc_info); 1357 type_register_static(&next_scsi_info); 1358 type_register_static(&next_rtc_info); 1359 } 1360 1361 type_init(next_register_type) 1362