1 /* 2 * NeXT Cube System Driver 3 * 4 * Copyright (c) 2011 Bryce Lanham 5 * 6 * This code is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published 8 * by the Free Software Foundation; either version 2 of the License, 9 * or (at your option) any later version. 10 */ 11 12 #include "qemu/osdep.h" 13 #include "exec/hwaddr.h" 14 #include "system/system.h" 15 #include "system/qtest.h" 16 #include "hw/irq.h" 17 #include "hw/m68k/next-cube.h" 18 #include "hw/boards.h" 19 #include "hw/loader.h" 20 #include "hw/scsi/esp.h" 21 #include "hw/sysbus.h" 22 #include "qom/object.h" 23 #include "hw/char/escc.h" /* ZILOG 8530 Serial Emulation */ 24 #include "hw/block/fdc.h" 25 #include "hw/misc/empty_slot.h" 26 #include "hw/qdev-properties.h" 27 #include "qapi/error.h" 28 #include "qemu/error-report.h" 29 #include "ui/console.h" 30 #include "target/m68k/cpu.h" 31 #include "migration/vmstate.h" 32 33 /* #define DEBUG_NEXT */ 34 #ifdef DEBUG_NEXT 35 #define DPRINTF(fmt, ...) \ 36 do { printf("NeXT: " fmt , ## __VA_ARGS__); } while (0) 37 #else 38 #define DPRINTF(fmt, ...) do { } while (0) 39 #endif 40 41 #define ENTRY 0x0100001e 42 #define RAM_SIZE 0x4000000 43 #define ROM_FILE "Rev_2.5_v66.bin" 44 45 46 #define TYPE_NEXT_RTC "next-rtc" 47 OBJECT_DECLARE_SIMPLE_TYPE(NeXTRTC, NEXT_RTC) 48 49 struct NeXTRTC { 50 SysBusDevice parent_obj; 51 52 int8_t phase; 53 uint8_t ram[32]; 54 uint8_t command; 55 uint8_t value; 56 uint8_t status; 57 uint8_t control; 58 uint8_t retval; 59 }; 60 61 #define TYPE_NEXT_SCSI "next-scsi" 62 OBJECT_DECLARE_SIMPLE_TYPE(NeXTSCSI, NEXT_SCSI) 63 64 /* NeXT SCSI Controller */ 65 struct NeXTSCSI { 66 SysBusDevice parent_obj; 67 68 MemoryRegion scsi_mem; 69 70 SysBusESPState sysbus_esp; 71 72 MemoryRegion scsi_csr_mem; 73 uint8_t scsi_csr_1; 74 uint8_t scsi_csr_2; 75 }; 76 77 #define TYPE_NEXT_PC "next-pc" 78 OBJECT_DECLARE_SIMPLE_TYPE(NeXTPC, NEXT_PC) 79 80 /* NeXT Peripheral Controller */ 81 struct NeXTPC { 82 SysBusDevice parent_obj; 83 84 M68kCPU *cpu; 85 86 MemoryRegion floppy_mem; 87 MemoryRegion timer_mem; 88 MemoryRegion dummyen_mem; 89 MemoryRegion mmiomem; 90 MemoryRegion scrmem; 91 92 uint32_t scr1; 93 uint32_t scr2; 94 uint32_t old_scr2; 95 uint32_t int_mask; 96 uint32_t int_status; 97 uint32_t led; 98 99 NeXTSCSI next_scsi; 100 101 qemu_irq scsi_reset; 102 qemu_irq scsi_dma; 103 104 ESCCState escc; 105 106 NeXTRTC rtc; 107 qemu_irq rtc_power_irq; 108 qemu_irq rtc_data_irq; 109 }; 110 111 typedef struct next_dma { 112 uint32_t csr; 113 114 uint32_t saved_next; 115 uint32_t saved_limit; 116 uint32_t saved_start; 117 uint32_t saved_stop; 118 119 uint32_t next; 120 uint32_t limit; 121 uint32_t start; 122 uint32_t stop; 123 124 uint32_t next_initbuf; 125 uint32_t size; 126 } next_dma; 127 128 #define TYPE_NEXT_MACHINE MACHINE_TYPE_NAME("next-cube") 129 OBJECT_DECLARE_SIMPLE_TYPE(NeXTState, NEXT_MACHINE) 130 131 struct NeXTState { 132 MachineState parent; 133 134 MemoryRegion rom; 135 MemoryRegion rom2; 136 MemoryRegion dmamem; 137 MemoryRegion bmapm1; 138 MemoryRegion bmapm2; 139 140 next_dma dma[10]; 141 }; 142 143 /* Thanks to NeXT forums for this */ 144 /* 145 static const uint8_t rtc_ram3[32] = { 146 0x94, 0x0f, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 147 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x7B, 0x00, 148 0x00, 0x00, 0x65, 0x6e, 0x00, 0x00, 0x00, 0x00, 149 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x13 150 }; 151 */ 152 static const uint8_t rtc_ram2[32] = { 153 0x94, 0x0f, 0x40, 0x03, 0x00, 0x00, 0x00, 0x00, 154 0x00, 0x00, 0xfb, 0x6d, 0x00, 0x00, 0x4b, 0x00, 155 0x41, 0x00, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 156 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x84, 0x7e, 157 }; 158 159 #define SCR2_RTCLK 0x2 160 #define SCR2_RTDATA 0x4 161 #define SCR2_TOBCD(x) (((x / 10) << 4) + (x % 10)) 162 163 static void next_scr2_led_update(NeXTPC *s) 164 { 165 if (s->scr2 & 0x1) { 166 DPRINTF("fault!\n"); 167 s->led++; 168 if (s->led == 10) { 169 DPRINTF("LED flashing, possible fault!\n"); 170 s->led = 0; 171 } 172 } 173 } 174 175 static bool next_rtc_cmd_is_write(uint8_t cmd) 176 { 177 return (cmd >= 0x80 && cmd <= 0x9f) || 178 (cmd == 0xb1); 179 } 180 181 static void next_rtc_data_in_irq(void *opaque, int n, int level) 182 { 183 NeXTRTC *rtc = NEXT_RTC(opaque); 184 NeXTPC *s = NEXT_PC(container_of(rtc, NeXTPC, rtc)); 185 186 if (rtc->phase < 8) { 187 rtc->command = (rtc->command << 1) | level; 188 189 if (rtc->phase == 7 && !next_rtc_cmd_is_write(rtc->command)) { 190 if (rtc->command <= 0x1f) { 191 /* RAM registers */ 192 rtc->retval = rtc->ram[rtc->command]; 193 } 194 if ((rtc->command >= 0x20) && (rtc->command <= 0x2f)) { 195 /* RTC */ 196 time_t time_h = time(NULL); 197 struct tm *info = localtime(&time_h); 198 rtc->retval = 0; 199 200 switch (rtc->command) { 201 case 0x20: 202 rtc->retval = SCR2_TOBCD(info->tm_sec); 203 break; 204 case 0x21: 205 rtc->retval = SCR2_TOBCD(info->tm_min); 206 break; 207 case 0x22: 208 rtc->retval = SCR2_TOBCD(info->tm_hour); 209 break; 210 case 0x24: 211 rtc->retval = SCR2_TOBCD(info->tm_mday); 212 break; 213 case 0x25: 214 rtc->retval = SCR2_TOBCD((info->tm_mon + 1)); 215 break; 216 case 0x26: 217 rtc->retval = SCR2_TOBCD((info->tm_year - 100)); 218 break; 219 } 220 } 221 if (rtc->command == 0x30) { 222 /* read the status 0x30 */ 223 rtc->retval = rtc->status; 224 } 225 if (rtc->command == 0x31) { 226 /* read the control 0x31 */ 227 rtc->retval = rtc->control; 228 } 229 } 230 } 231 if (rtc->phase >= 8 && rtc->phase < 16) { 232 if (next_rtc_cmd_is_write(rtc->command)) { 233 /* Shift in value to write */ 234 rtc->value = (rtc->value << 1) | level; 235 } else { 236 /* Shift out value to read */ 237 qemu_irq rtc_data_in_irq = qdev_get_gpio_in_named( 238 DEVICE(s), "pc-rtc-data-in", 0); 239 240 if (rtc->retval & (0x80 >> (rtc->phase - 8))) { 241 qemu_irq_raise(rtc_data_in_irq); 242 } else { 243 qemu_irq_lower(rtc_data_in_irq); 244 } 245 } 246 } 247 248 rtc->phase++; 249 if (rtc->phase == 16 && next_rtc_cmd_is_write(rtc->command)) { 250 if (rtc->command >= 0x80 && rtc->command <= 0x9f) { 251 /* RAM registers */ 252 rtc->ram[rtc->command - 0x80] = rtc->value; 253 } 254 if (rtc->command == 0xb1) { 255 /* write to 0x30 register */ 256 if (rtc->value & 0x04) { 257 /* clear FTU */ 258 rtc->status = rtc->status & (~0x18); 259 qemu_irq_lower(s->rtc_power_irq); 260 } 261 } 262 } 263 } 264 265 static void next_scr2_rtc_update(NeXTPC *s) 266 { 267 uint8_t old_scr2, scr2_2; 268 NeXTRTC *rtc = &s->rtc; 269 270 old_scr2 = extract32(s->old_scr2, 8, 8); 271 scr2_2 = extract32(s->scr2, 8, 8); 272 273 if (scr2_2 & 0x1) { 274 /* DPRINTF("RTC %x phase %i\n", scr2_2, rtc->phase); */ 275 /* If we are in going down clock... do something */ 276 if (((old_scr2 & SCR2_RTCLK) != (scr2_2 & SCR2_RTCLK)) && 277 ((scr2_2 & SCR2_RTCLK) == 0)) { 278 if (scr2_2 & SCR2_RTDATA) { 279 qemu_irq_raise(s->rtc_data_irq); 280 } else { 281 qemu_irq_lower(s->rtc_data_irq); 282 } 283 } 284 } else { 285 /* else end or abort */ 286 rtc->phase = 0; 287 rtc->command = 0; 288 rtc->value = 0; 289 } 290 } 291 292 static uint64_t next_mmio_read(void *opaque, hwaddr addr, unsigned size) 293 { 294 NeXTPC *s = NEXT_PC(opaque); 295 uint64_t val; 296 297 switch (addr) { 298 case 0x2000: /* 0x2007000 */ 299 /* DPRINTF("Read INT status: %x\n", s->int_status); */ 300 val = s->int_status; 301 break; 302 303 case 0x2800: /* 0x2007800 */ 304 DPRINTF("MMIO Read INT mask: %x\n", s->int_mask); 305 val = s->int_mask; 306 break; 307 308 case 0x7000 ... 0x7003: /* 0x200c000 */ 309 val = extract32(s->scr1, (4 - (addr - 0x7000) - size) << 3, 310 size << 3); 311 break; 312 313 case 0x8000 ... 0x8003: /* 0x200d000 */ 314 val = extract32(s->scr2, (4 - (addr - 0x8000) - size) << 3, 315 size << 3); 316 break; 317 318 default: 319 val = 0; 320 DPRINTF("MMIO Read @ 0x%"HWADDR_PRIx" size %d\n", addr, size); 321 break; 322 } 323 324 return val; 325 } 326 327 static void next_mmio_write(void *opaque, hwaddr addr, uint64_t val, 328 unsigned size) 329 { 330 NeXTPC *s = NEXT_PC(opaque); 331 332 switch (addr) { 333 case 0x2000: /* 0x2007000 */ 334 DPRINTF("INT Status old: %x new: %x\n", s->int_status, 335 (unsigned int)val); 336 s->int_status = val; 337 break; 338 339 case 0x2800: /* 0x2007800 */ 340 DPRINTF("INT Mask old: %x new: %x\n", s->int_mask, (unsigned int)val); 341 s->int_mask = val; 342 break; 343 344 case 0x7000 ... 0x7003: /* 0x200c000 */ 345 DPRINTF("SCR1 Write: %x\n", (unsigned int)val); 346 s->scr1 = deposit32(s->scr1, (4 - (addr - 0x7000) - size) << 3, 347 size << 3, val); 348 break; 349 350 case 0x8000 ... 0x8003: /* 0x200d000 */ 351 s->scr2 = deposit32(s->scr2, (4 - (addr - 0x8000) - size) << 3, 352 size << 3, val); 353 next_scr2_led_update(s); 354 next_scr2_rtc_update(s); 355 s->old_scr2 = s->scr2; 356 break; 357 358 default: 359 DPRINTF("MMIO Write @ 0x%"HWADDR_PRIx " with 0x%x size %u\n", addr, 360 (unsigned int)val, size); 361 } 362 } 363 364 static const MemoryRegionOps next_mmio_ops = { 365 .read = next_mmio_read, 366 .write = next_mmio_write, 367 .valid.min_access_size = 1, 368 .valid.max_access_size = 4, 369 .endianness = DEVICE_BIG_ENDIAN, 370 }; 371 372 #define SCSICSR_ENABLE 0x01 373 #define SCSICSR_RESET 0x02 /* reset scsi dma */ 374 #define SCSICSR_FIFOFL 0x04 375 #define SCSICSR_DMADIR 0x08 /* if set, scsi to mem */ 376 #define SCSICSR_CPUDMA 0x10 /* if set, dma enabled */ 377 #define SCSICSR_INTMASK 0x20 /* if set, interrupt enabled */ 378 379 #define NEXTDMA_SCSI(x) (0x10 + x) 380 #define NEXTDMA_FD(x) (0x10 + x) 381 #define NEXTDMA_ENTX(x) (0x110 + x) 382 #define NEXTDMA_ENRX(x) (0x150 + x) 383 #define NEXTDMA_CSR 0x0 384 #define NEXTDMA_NEXT 0x4000 385 #define NEXTDMA_LIMIT 0x4004 386 #define NEXTDMA_START 0x4008 387 #define NEXTDMA_STOP 0x400c 388 #define NEXTDMA_NEXT_INIT 0x4200 389 #define NEXTDMA_SIZE 0x4204 390 391 static void next_dma_write(void *opaque, hwaddr addr, uint64_t val, 392 unsigned int size) 393 { 394 NeXTState *next_state = NEXT_MACHINE(opaque); 395 396 switch (addr) { 397 case NEXTDMA_ENRX(NEXTDMA_CSR): 398 if (val & DMA_DEV2M) { 399 next_state->dma[NEXTDMA_ENRX].csr |= DMA_DEV2M; 400 } 401 402 if (val & DMA_SETENABLE) { 403 /* DPRINTF("SCSI DMA ENABLE\n"); */ 404 next_state->dma[NEXTDMA_ENRX].csr |= DMA_ENABLE; 405 } 406 if (val & DMA_SETSUPDATE) { 407 next_state->dma[NEXTDMA_ENRX].csr |= DMA_SUPDATE; 408 } 409 if (val & DMA_CLRCOMPLETE) { 410 next_state->dma[NEXTDMA_ENRX].csr &= ~DMA_COMPLETE; 411 } 412 413 if (val & DMA_RESET) { 414 next_state->dma[NEXTDMA_ENRX].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 415 DMA_ENABLE | DMA_DEV2M); 416 } 417 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 418 break; 419 420 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 421 next_state->dma[NEXTDMA_ENRX].next_initbuf = val; 422 break; 423 424 case NEXTDMA_ENRX(NEXTDMA_NEXT): 425 next_state->dma[NEXTDMA_ENRX].next = val; 426 break; 427 428 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 429 next_state->dma[NEXTDMA_ENRX].limit = val; 430 break; 431 432 case NEXTDMA_SCSI(NEXTDMA_CSR): 433 if (val & DMA_DEV2M) { 434 next_state->dma[NEXTDMA_SCSI].csr |= DMA_DEV2M; 435 } 436 if (val & DMA_SETENABLE) { 437 /* DPRINTF("SCSI DMA ENABLE\n"); */ 438 next_state->dma[NEXTDMA_SCSI].csr |= DMA_ENABLE; 439 } 440 if (val & DMA_SETSUPDATE) { 441 next_state->dma[NEXTDMA_SCSI].csr |= DMA_SUPDATE; 442 } 443 if (val & DMA_CLRCOMPLETE) { 444 next_state->dma[NEXTDMA_SCSI].csr &= ~DMA_COMPLETE; 445 } 446 447 if (val & DMA_RESET) { 448 next_state->dma[NEXTDMA_SCSI].csr &= ~(DMA_COMPLETE | DMA_SUPDATE | 449 DMA_ENABLE | DMA_DEV2M); 450 /* DPRINTF("SCSI DMA RESET\n"); */ 451 } 452 /* DPRINTF("RXCSR \tWrite: %x\n",value); */ 453 break; 454 455 case NEXTDMA_SCSI(NEXTDMA_NEXT): 456 next_state->dma[NEXTDMA_SCSI].next = val; 457 break; 458 459 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 460 next_state->dma[NEXTDMA_SCSI].limit = val; 461 break; 462 463 case NEXTDMA_SCSI(NEXTDMA_START): 464 next_state->dma[NEXTDMA_SCSI].start = val; 465 break; 466 467 case NEXTDMA_SCSI(NEXTDMA_STOP): 468 next_state->dma[NEXTDMA_SCSI].stop = val; 469 break; 470 471 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 472 next_state->dma[NEXTDMA_SCSI].next_initbuf = val; 473 break; 474 475 default: 476 DPRINTF("DMA write @ %x w/ %x\n", (unsigned)addr, (unsigned)val); 477 } 478 } 479 480 static uint64_t next_dma_read(void *opaque, hwaddr addr, unsigned int size) 481 { 482 NeXTState *next_state = NEXT_MACHINE(opaque); 483 uint64_t val; 484 485 switch (addr) { 486 case NEXTDMA_SCSI(NEXTDMA_CSR): 487 DPRINTF("SCSI DMA CSR READ\n"); 488 val = next_state->dma[NEXTDMA_SCSI].csr; 489 break; 490 491 case NEXTDMA_ENRX(NEXTDMA_CSR): 492 val = next_state->dma[NEXTDMA_ENRX].csr; 493 break; 494 495 case NEXTDMA_ENRX(NEXTDMA_NEXT_INIT): 496 val = next_state->dma[NEXTDMA_ENRX].next_initbuf; 497 break; 498 499 case NEXTDMA_ENRX(NEXTDMA_NEXT): 500 val = next_state->dma[NEXTDMA_ENRX].next; 501 break; 502 503 case NEXTDMA_ENRX(NEXTDMA_LIMIT): 504 val = next_state->dma[NEXTDMA_ENRX].limit; 505 break; 506 507 case NEXTDMA_SCSI(NEXTDMA_NEXT): 508 val = next_state->dma[NEXTDMA_SCSI].next; 509 break; 510 511 case NEXTDMA_SCSI(NEXTDMA_NEXT_INIT): 512 val = next_state->dma[NEXTDMA_SCSI].next_initbuf; 513 break; 514 515 case NEXTDMA_SCSI(NEXTDMA_LIMIT): 516 val = next_state->dma[NEXTDMA_SCSI].limit; 517 break; 518 519 case NEXTDMA_SCSI(NEXTDMA_START): 520 val = next_state->dma[NEXTDMA_SCSI].start; 521 break; 522 523 case NEXTDMA_SCSI(NEXTDMA_STOP): 524 val = next_state->dma[NEXTDMA_SCSI].stop; 525 break; 526 527 default: 528 DPRINTF("DMA read @ %x\n", (unsigned int)addr); 529 val = 0; 530 } 531 532 /* 533 * once the csr's are done, subtract 0x3FEC from the addr, and that will 534 * normalize the upper registers 535 */ 536 537 return val; 538 } 539 540 static const MemoryRegionOps next_dma_ops = { 541 .read = next_dma_read, 542 .write = next_dma_write, 543 .impl.min_access_size = 4, 544 .valid.min_access_size = 4, 545 .valid.max_access_size = 4, 546 .endianness = DEVICE_BIG_ENDIAN, 547 }; 548 549 static void next_irq(void *opaque, int number, int level) 550 { 551 NeXTPC *s = NEXT_PC(opaque); 552 M68kCPU *cpu = s->cpu; 553 int shift = 0; 554 555 /* first switch sets interrupt status */ 556 /* DPRINTF("IRQ %i\n",number); */ 557 switch (number) { 558 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 559 case NEXT_FD_I: 560 shift = 7; 561 break; 562 case NEXT_KBD_I: 563 shift = 3; 564 break; 565 case NEXT_PWR_I: 566 shift = 2; 567 break; 568 case NEXT_ENRX_I: 569 shift = 9; 570 break; 571 case NEXT_ENTX_I: 572 shift = 10; 573 break; 574 case NEXT_SCSI_I: 575 shift = 12; 576 break; 577 case NEXT_CLK_I: 578 shift = 5; 579 break; 580 581 /* level 5 - scc (serial) */ 582 case NEXT_SCC_I: 583 shift = 17; 584 break; 585 586 /* level 6 - audio etherrx/tx dma */ 587 case NEXT_ENTX_DMA_I: 588 shift = 28; 589 break; 590 case NEXT_ENRX_DMA_I: 591 shift = 27; 592 break; 593 case NEXT_SCSI_DMA_I: 594 shift = 26; 595 break; 596 case NEXT_SND_I: 597 shift = 23; 598 break; 599 case NEXT_SCC_DMA_I: 600 shift = 21; 601 break; 602 603 } 604 /* 605 * this HAS to be wrong, the interrupt handlers in mach and together 606 * int_status and int_mask and return if there is a hit 607 */ 608 if (s->int_mask & (1 << shift)) { 609 DPRINTF("%x interrupt masked @ %x\n", 1 << shift, cpu->env.pc); 610 /* return; */ 611 } 612 613 /* second switch triggers the correct interrupt */ 614 if (level) { 615 s->int_status |= 1 << shift; 616 617 switch (number) { 618 /* level 3 - floppy, kbd/mouse, power, ether rx/tx, scsi, clock */ 619 case NEXT_FD_I: 620 case NEXT_KBD_I: 621 case NEXT_PWR_I: 622 case NEXT_ENRX_I: 623 case NEXT_ENTX_I: 624 case NEXT_SCSI_I: 625 case NEXT_CLK_I: 626 m68k_set_irq_level(cpu, 3, 27); 627 break; 628 629 /* level 5 - scc (serial) */ 630 case NEXT_SCC_I: 631 m68k_set_irq_level(cpu, 5, 29); 632 break; 633 634 /* level 6 - audio etherrx/tx dma */ 635 case NEXT_ENTX_DMA_I: 636 case NEXT_ENRX_DMA_I: 637 case NEXT_SCSI_DMA_I: 638 case NEXT_SND_I: 639 case NEXT_SCC_DMA_I: 640 m68k_set_irq_level(cpu, 6, 30); 641 break; 642 } 643 } else { 644 s->int_status &= ~(1 << shift); 645 cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); 646 } 647 } 648 649 static void nextdma_write(void *opaque, uint8_t *buf, int size, int type) 650 { 651 uint32_t base_addr; 652 int irq = 0; 653 uint8_t align = 16; 654 NeXTState *next_state = NEXT_MACHINE(qdev_get_machine()); 655 656 if (type == NEXTDMA_ENRX || type == NEXTDMA_ENTX) { 657 align = 32; 658 } 659 /* Most DMA is supposedly 16 byte aligned */ 660 if ((size % align) != 0) { 661 size -= size % align; 662 size += align; 663 } 664 665 /* 666 * prom sets the dma start using initbuf while the bootloader uses next 667 * so we check to see if initbuf is 0 668 */ 669 if (next_state->dma[type].next_initbuf == 0) { 670 base_addr = next_state->dma[type].next; 671 } else { 672 base_addr = next_state->dma[type].next_initbuf; 673 } 674 675 cpu_physical_memory_write(base_addr, buf, size); 676 677 next_state->dma[type].next_initbuf = 0; 678 679 /* saved limit is checked to calculate packet size by both, rom and netbsd */ 680 next_state->dma[type].saved_limit = (next_state->dma[type].next + size); 681 next_state->dma[type].saved_next = (next_state->dma[type].next); 682 683 /* 684 * 32 bytes under savedbase seems to be some kind of register 685 * of which the purpose is unknown as of yet 686 */ 687 /* stl_phys(s->rx_dma.base-32,0xFFFFFFFF); */ 688 689 if (!(next_state->dma[type].csr & DMA_SUPDATE)) { 690 next_state->dma[type].next = next_state->dma[type].start; 691 next_state->dma[type].limit = next_state->dma[type].stop; 692 } 693 694 /* Set dma registers and raise an irq */ 695 next_state->dma[type].csr |= DMA_COMPLETE; /* DON'T CHANGE THIS! */ 696 697 switch (type) { 698 case NEXTDMA_SCSI: 699 irq = NEXT_SCSI_DMA_I; 700 break; 701 } 702 703 next_irq(opaque, irq, 1); 704 next_irq(opaque, irq, 0); 705 } 706 707 static void nextscsi_read(void *opaque, uint8_t *buf, int len) 708 { 709 DPRINTF("SCSI READ: %x\n", len); 710 abort(); 711 } 712 713 static void nextscsi_write(void *opaque, uint8_t *buf, int size) 714 { 715 DPRINTF("SCSI WRITE: %i\n", size); 716 nextdma_write(opaque, buf, size, NEXTDMA_SCSI); 717 } 718 719 static void next_scsi_csr_write(void *opaque, hwaddr addr, uint64_t val, 720 unsigned size) 721 { 722 NeXTSCSI *s = NEXT_SCSI(opaque); 723 NeXTPC *pc = NEXT_PC(container_of(s, NeXTPC, next_scsi)); 724 725 switch (addr) { 726 case 0: 727 if (val & SCSICSR_FIFOFL) { 728 DPRINTF("SCSICSR FIFO Flush\n"); 729 /* will have to add another irq to the esp if this is needed */ 730 /* esp_puflush_fifo(esp_g); */ 731 } 732 733 if (val & SCSICSR_ENABLE) { 734 DPRINTF("SCSICSR Enable\n"); 735 /* 736 * qemu_irq_raise(s->scsi_dma); 737 * s->scsi_csr_1 = 0xc0; 738 * s->scsi_csr_1 |= 0x1; 739 * qemu_irq_pulse(s->scsi_dma); 740 */ 741 } 742 /* 743 * else 744 * s->scsi_csr_1 &= ~SCSICSR_ENABLE; 745 */ 746 747 if (val & SCSICSR_RESET) { 748 DPRINTF("SCSICSR Reset\n"); 749 /* I think this should set DMADIR. CPUDMA and INTMASK to 0 */ 750 qemu_irq_raise(pc->scsi_reset); 751 s->scsi_csr_1 &= ~(SCSICSR_INTMASK | 0x80 | 0x1); 752 qemu_irq_lower(pc->scsi_reset); 753 } 754 if (val & SCSICSR_DMADIR) { 755 DPRINTF("SCSICSR DMAdir\n"); 756 } 757 if (val & SCSICSR_CPUDMA) { 758 DPRINTF("SCSICSR CPUDMA\n"); 759 /* qemu_irq_raise(s->scsi_dma); */ 760 pc->int_status |= 0x4000000; 761 } else { 762 /* fprintf(stderr,"SCSICSR CPUDMA disabled\n"); */ 763 pc->int_status &= ~(0x4000000); 764 /* qemu_irq_lower(s->scsi_dma); */ 765 } 766 if (val & SCSICSR_INTMASK) { 767 DPRINTF("SCSICSR INTMASK\n"); 768 /* 769 * int_mask &= ~0x1000; 770 * s->scsi_csr_1 |= val; 771 * s->scsi_csr_1 &= ~SCSICSR_INTMASK; 772 * if (s->scsi_queued) { 773 * s->scsi_queued = 0; 774 * next_irq(s, NEXT_SCSI_I, level); 775 * } 776 */ 777 } else { 778 /* int_mask |= 0x1000; */ 779 } 780 if (val & 0x80) { 781 /* int_mask |= 0x1000; */ 782 /* s->scsi_csr_1 |= 0x80; */ 783 } 784 DPRINTF("SCSICSR1 Write: %"PRIx64 "\n", val); 785 s->scsi_csr_1 = val; 786 break; 787 788 case 1: 789 DPRINTF("SCSICSR2 Write: %"PRIx64 "\n", val); 790 s->scsi_csr_2 = val; 791 break; 792 793 default: 794 g_assert_not_reached(); 795 } 796 } 797 798 static uint64_t next_scsi_csr_read(void *opaque, hwaddr addr, unsigned size) 799 { 800 NeXTSCSI *s = NEXT_SCSI(opaque); 801 uint64_t val; 802 803 switch (addr) { 804 case 0: 805 DPRINTF("SCSI 4020 STATUS READ %X\n", s->scsi_csr_1); 806 val = s->scsi_csr_1; 807 break; 808 809 case 1: 810 DPRINTF("SCSI 4021 STATUS READ %X\n", s->scsi_csr_2); 811 val = s->scsi_csr_2; 812 break; 813 814 default: 815 g_assert_not_reached(); 816 } 817 818 return val; 819 } 820 821 static const MemoryRegionOps next_scsi_csr_ops = { 822 .read = next_scsi_csr_read, 823 .write = next_scsi_csr_write, 824 .valid.min_access_size = 1, 825 .valid.max_access_size = 1, 826 .endianness = DEVICE_BIG_ENDIAN, 827 }; 828 829 static void next_scsi_init(Object *obj) 830 { 831 NeXTSCSI *s = NEXT_SCSI(obj); 832 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 833 834 object_initialize_child(obj, "esp", &s->sysbus_esp, TYPE_SYSBUS_ESP); 835 836 memory_region_init_io(&s->scsi_csr_mem, obj, &next_scsi_csr_ops, 837 s, "csrs", 2); 838 839 memory_region_init(&s->scsi_mem, obj, "next.scsi", 0x40); 840 sysbus_init_mmio(sbd, &s->scsi_mem); 841 } 842 843 static void next_scsi_realize(DeviceState *dev, Error **errp) 844 { 845 NeXTSCSI *s = NEXT_SCSI(dev); 846 SysBusESPState *sysbus_esp; 847 SysBusDevice *sbd; 848 ESPState *esp; 849 NeXTPC *pcdev; 850 851 pcdev = NEXT_PC(container_of(s, NeXTPC, next_scsi)); 852 853 /* ESP */ 854 sysbus_esp = SYSBUS_ESP(&s->sysbus_esp); 855 esp = &sysbus_esp->esp; 856 esp->dma_memory_read = nextscsi_read; 857 esp->dma_memory_write = nextscsi_write; 858 esp->dma_opaque = pcdev; 859 sysbus_esp->it_shift = 0; 860 esp->dma_enabled = 1; 861 sbd = SYS_BUS_DEVICE(sysbus_esp); 862 if (!sysbus_realize(sbd, errp)) { 863 return; 864 } 865 memory_region_add_subregion(&s->scsi_mem, 0x0, 866 sysbus_mmio_get_region(sbd, 0)); 867 868 /* SCSI CSRs */ 869 memory_region_add_subregion(&s->scsi_mem, 0x20, &s->scsi_csr_mem); 870 871 scsi_bus_legacy_handle_cmdline(&s->sysbus_esp.esp.bus); 872 } 873 874 static const VMStateDescription next_scsi_vmstate = { 875 .name = "next-scsi", 876 .version_id = 0, 877 .minimum_version_id = 0, 878 .fields = (const VMStateField[]) { 879 VMSTATE_UINT8(scsi_csr_1, NeXTSCSI), 880 VMSTATE_UINT8(scsi_csr_2, NeXTSCSI), 881 VMSTATE_END_OF_LIST() 882 }, 883 }; 884 885 static void next_scsi_class_init(ObjectClass *klass, void *data) 886 { 887 DeviceClass *dc = DEVICE_CLASS(klass); 888 889 dc->desc = "NeXT SCSI Controller"; 890 dc->realize = next_scsi_realize; 891 dc->vmsd = &next_scsi_vmstate; 892 } 893 894 static const TypeInfo next_scsi_info = { 895 .name = TYPE_NEXT_SCSI, 896 .parent = TYPE_SYS_BUS_DEVICE, 897 .instance_init = next_scsi_init, 898 .instance_size = sizeof(NeXTSCSI), 899 .class_init = next_scsi_class_init, 900 }; 901 902 static void next_floppy_write(void *opaque, hwaddr addr, uint64_t val, 903 unsigned size) 904 { 905 switch (addr) { 906 case 0: 907 DPRINTF("FDCSR Write: %"PRIx64 "\n", val); 908 if (val == 0x0) { 909 /* qemu_irq_raise(s->fd_irq[0]); */ 910 } 911 break; 912 913 default: 914 g_assert_not_reached(); 915 } 916 } 917 918 static uint64_t next_floppy_read(void *opaque, hwaddr addr, unsigned size) 919 { 920 uint64_t val; 921 922 switch (addr) { 923 case 0: 924 DPRINTF("FD read @ %x\n", (unsigned int)addr); 925 val = 0x40 | 0x04 | 0x2 | 0x1; 926 break; 927 928 default: 929 g_assert_not_reached(); 930 } 931 932 return val; 933 } 934 935 static const MemoryRegionOps next_floppy_ops = { 936 .read = next_floppy_read, 937 .write = next_floppy_write, 938 .valid.min_access_size = 1, 939 .valid.max_access_size = 4, 940 .endianness = DEVICE_BIG_ENDIAN, 941 }; 942 943 static void next_timer_write(void *opaque, hwaddr addr, uint64_t val, 944 unsigned size) 945 { 946 switch (addr) { 947 case 0 ... 3: 948 /* Hardware timer latch - not implemented yet */ 949 break; 950 951 default: 952 g_assert_not_reached(); 953 } 954 } 955 956 static uint64_t next_timer_read(void *opaque, hwaddr addr, unsigned size) 957 { 958 uint64_t val; 959 960 switch (addr) { 961 case 0 ... 3: 962 /* 963 * These 4 registers are the hardware timer, not sure which register 964 * is the latch instead of data, but no problems so far. 965 * 966 * Hack: We need to have the LSB change consistently to make it work 967 */ 968 val = extract32(clock(), (4 - addr - size) << 3, 969 size << 3); 970 break; 971 972 default: 973 g_assert_not_reached(); 974 } 975 976 return val; 977 } 978 979 static const MemoryRegionOps next_timer_ops = { 980 .read = next_timer_read, 981 .write = next_timer_write, 982 .valid.min_access_size = 1, 983 .valid.max_access_size = 4, 984 .endianness = DEVICE_BIG_ENDIAN, 985 }; 986 987 static void next_dummy_en_write(void *opaque, hwaddr addr, uint64_t val, 988 unsigned size) 989 { 990 /* Do nothing */ 991 return; 992 } 993 994 static uint64_t next_dummy_en_read(void *opaque, hwaddr addr, unsigned size) 995 { 996 uint64_t val; 997 998 switch (addr) { 999 case 0: 1000 /* For now return dummy byte to allow the Ethernet test to timeout */ 1001 val = 0xff; 1002 break; 1003 1004 default: 1005 val = 0; 1006 } 1007 1008 return val; 1009 } 1010 1011 static const MemoryRegionOps next_dummy_en_ops = { 1012 .read = next_dummy_en_read, 1013 .write = next_dummy_en_write, 1014 .valid.min_access_size = 1, 1015 .valid.max_access_size = 4, 1016 .endianness = DEVICE_BIG_ENDIAN, 1017 }; 1018 1019 static void next_rtc_reset_hold(Object *obj, ResetType type) 1020 { 1021 NeXTRTC *rtc = NEXT_RTC(obj); 1022 1023 rtc->status = 0x90; 1024 1025 /* Load RTC RAM - TODO: provide possibility to load contents from file */ 1026 memcpy(rtc->ram, rtc_ram2, 32); 1027 } 1028 1029 static void next_rtc_init(Object *obj) 1030 { 1031 qdev_init_gpio_in_named(DEVICE(obj), next_rtc_data_in_irq, 1032 "rtc-data-in", 1); 1033 } 1034 1035 static const VMStateDescription next_rtc_vmstate = { 1036 .name = "next-rtc", 1037 .version_id = 3, 1038 .minimum_version_id = 3, 1039 .fields = (const VMStateField[]) { 1040 VMSTATE_INT8(phase, NeXTRTC), 1041 VMSTATE_UINT8_ARRAY(ram, NeXTRTC, 32), 1042 VMSTATE_UINT8(command, NeXTRTC), 1043 VMSTATE_UINT8(value, NeXTRTC), 1044 VMSTATE_UINT8(status, NeXTRTC), 1045 VMSTATE_UINT8(control, NeXTRTC), 1046 VMSTATE_UINT8(retval, NeXTRTC), 1047 VMSTATE_END_OF_LIST() 1048 }, 1049 }; 1050 1051 static void next_rtc_class_init(ObjectClass *klass, void *data) 1052 { 1053 DeviceClass *dc = DEVICE_CLASS(klass); 1054 ResettableClass *rc = RESETTABLE_CLASS(klass); 1055 1056 dc->desc = "NeXT RTC"; 1057 dc->vmsd = &next_rtc_vmstate; 1058 rc->phases.hold = next_rtc_reset_hold; 1059 } 1060 1061 static const TypeInfo next_rtc_info = { 1062 .name = TYPE_NEXT_RTC, 1063 .parent = TYPE_SYS_BUS_DEVICE, 1064 .instance_init = next_rtc_init, 1065 .instance_size = sizeof(NeXTRTC), 1066 .class_init = next_rtc_class_init, 1067 }; 1068 1069 static void next_pc_rtc_data_in_irq(void *opaque, int n, int level) 1070 { 1071 NeXTPC *s = NEXT_PC(opaque); 1072 uint8_t scr2_2 = extract32(s->scr2, 8, 8); 1073 1074 if (level) { 1075 scr2_2 |= SCR2_RTDATA; 1076 } else { 1077 scr2_2 &= ~SCR2_RTDATA; 1078 } 1079 1080 s->scr2 = deposit32(s->scr2, 8, 8, scr2_2); 1081 } 1082 1083 static void next_pc_reset_hold(Object *obj, ResetType type) 1084 { 1085 NeXTPC *s = NEXT_PC(obj); 1086 1087 /* Set internal registers to initial values */ 1088 /* 0x0000XX00 << vital bits */ 1089 s->scr1 = 0x00011102; 1090 s->scr2 = 0x00ff0c80; 1091 s->old_scr2 = s->scr2; 1092 } 1093 1094 static void next_pc_realize(DeviceState *dev, Error **errp) 1095 { 1096 NeXTPC *s = NEXT_PC(dev); 1097 SysBusDevice *sbd; 1098 DeviceState *d; 1099 1100 /* SCSI */ 1101 sbd = SYS_BUS_DEVICE(&s->next_scsi); 1102 if (!sysbus_realize(sbd, errp)) { 1103 return; 1104 } 1105 1106 d = DEVICE(object_resolve_path_component(OBJECT(&s->next_scsi), "esp")); 1107 sysbus_connect_irq(SYS_BUS_DEVICE(d), 0, 1108 qdev_get_gpio_in(DEVICE(s), NEXT_SCSI_I)); 1109 1110 s->scsi_reset = qdev_get_gpio_in(d, 0); 1111 s->scsi_dma = qdev_get_gpio_in(d, 1); 1112 1113 /* ESCC */ 1114 d = DEVICE(&s->escc); 1115 qdev_prop_set_uint32(d, "disabled", 0); 1116 qdev_prop_set_uint32(d, "frequency", 9600 * 384); 1117 qdev_prop_set_uint32(d, "it_shift", 0); 1118 qdev_prop_set_bit(d, "bit_swap", true); 1119 qdev_prop_set_chr(d, "chrB", serial_hd(1)); 1120 qdev_prop_set_chr(d, "chrA", serial_hd(0)); 1121 qdev_prop_set_uint32(d, "chnBtype", escc_serial); 1122 qdev_prop_set_uint32(d, "chnAtype", escc_serial); 1123 1124 sbd = SYS_BUS_DEVICE(d); 1125 if (!sysbus_realize(sbd, errp)) { 1126 return; 1127 } 1128 sysbus_connect_irq(sbd, 0, qdev_get_gpio_in(dev, NEXT_SCC_I)); 1129 sysbus_connect_irq(sbd, 1, qdev_get_gpio_in(dev, NEXT_SCC_DMA_I)); 1130 1131 /* RTC */ 1132 d = DEVICE(&s->rtc); 1133 if (!sysbus_realize(SYS_BUS_DEVICE(d), errp)) { 1134 return; 1135 } 1136 /* Data from NeXTPC to RTC */ 1137 qdev_connect_gpio_out_named(dev, "rtc-data-out", 0, 1138 qdev_get_gpio_in_named(d, "rtc-data-in", 0)); 1139 } 1140 1141 static void next_pc_init(Object *obj) 1142 { 1143 NeXTPC *s = NEXT_PC(obj); 1144 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 1145 1146 qdev_init_gpio_in(DEVICE(obj), next_irq, NEXT_NUM_IRQS); 1147 1148 memory_region_init_io(&s->mmiomem, OBJECT(s), &next_mmio_ops, s, 1149 "next.mmio", 0x9000); 1150 sysbus_init_mmio(sbd, &s->mmiomem); 1151 1152 memory_region_init_io(&s->dummyen_mem, OBJECT(s), &next_dummy_en_ops, s, 1153 "next.en", 0x20); 1154 sysbus_init_mmio(sbd, &s->dummyen_mem); 1155 1156 object_initialize_child(obj, "next-scsi", &s->next_scsi, TYPE_NEXT_SCSI); 1157 sysbus_init_mmio(sbd, 1158 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->next_scsi), 0)); 1159 1160 memory_region_init_io(&s->floppy_mem, OBJECT(s), &next_floppy_ops, s, 1161 "next.floppy", 4); 1162 sysbus_init_mmio(sbd, &s->floppy_mem); 1163 1164 object_initialize_child(obj, "escc", &s->escc, TYPE_ESCC); 1165 sysbus_init_mmio(sbd, 1166 sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->escc), 0)); 1167 1168 memory_region_init_io(&s->timer_mem, OBJECT(s), &next_timer_ops, s, 1169 "next.timer", 4); 1170 sysbus_init_mmio(sbd, &s->timer_mem); 1171 1172 object_initialize_child(obj, "rtc", &s->rtc, TYPE_NEXT_RTC); 1173 1174 s->rtc_power_irq = qdev_get_gpio_in(DEVICE(obj), NEXT_PWR_I); 1175 qdev_init_gpio_in_named(DEVICE(obj), next_pc_rtc_data_in_irq, 1176 "pc-rtc-data-in", 1); 1177 qdev_init_gpio_out_named(DEVICE(obj), &s->rtc_data_irq, 1178 "rtc-data-out", 1); 1179 } 1180 1181 /* 1182 * If the m68k CPU implemented its inbound irq lines as GPIO lines 1183 * rather than via the m68k_set_irq_level() function we would not need 1184 * this cpu link property and could instead provide outbound IRQ lines 1185 * that the board could wire up to the CPU. 1186 */ 1187 static const Property next_pc_properties[] = { 1188 DEFINE_PROP_LINK("cpu", NeXTPC, cpu, TYPE_M68K_CPU, M68kCPU *), 1189 }; 1190 1191 static const VMStateDescription next_pc_vmstate = { 1192 .name = "next-pc", 1193 .version_id = 4, 1194 .minimum_version_id = 4, 1195 .fields = (const VMStateField[]) { 1196 VMSTATE_UINT32(scr1, NeXTPC), 1197 VMSTATE_UINT32(scr2, NeXTPC), 1198 VMSTATE_UINT32(old_scr2, NeXTPC), 1199 VMSTATE_UINT32(int_mask, NeXTPC), 1200 VMSTATE_UINT32(int_status, NeXTPC), 1201 VMSTATE_UINT32(led, NeXTPC), 1202 VMSTATE_END_OF_LIST() 1203 }, 1204 }; 1205 1206 static void next_pc_class_init(ObjectClass *klass, void *data) 1207 { 1208 DeviceClass *dc = DEVICE_CLASS(klass); 1209 ResettableClass *rc = RESETTABLE_CLASS(klass); 1210 1211 dc->desc = "NeXT Peripheral Controller"; 1212 dc->realize = next_pc_realize; 1213 device_class_set_props(dc, next_pc_properties); 1214 dc->vmsd = &next_pc_vmstate; 1215 rc->phases.hold = next_pc_reset_hold; 1216 } 1217 1218 static const TypeInfo next_pc_info = { 1219 .name = TYPE_NEXT_PC, 1220 .parent = TYPE_SYS_BUS_DEVICE, 1221 .instance_init = next_pc_init, 1222 .instance_size = sizeof(NeXTPC), 1223 .class_init = next_pc_class_init, 1224 }; 1225 1226 static void next_cube_init(MachineState *machine) 1227 { 1228 NeXTState *m = NEXT_MACHINE(machine); 1229 M68kCPU *cpu; 1230 CPUM68KState *env; 1231 MemoryRegion *sysmem = get_system_memory(); 1232 const char *bios_name = machine->firmware ?: ROM_FILE; 1233 DeviceState *pcdev; 1234 1235 /* Initialize the cpu core */ 1236 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 1237 if (!cpu) { 1238 error_report("Unable to find m68k CPU definition"); 1239 exit(1); 1240 } 1241 env = &cpu->env; 1242 1243 /* Initialize CPU registers. */ 1244 env->vbr = 0; 1245 env->sr = 0x2700; 1246 1247 /* Peripheral Controller */ 1248 pcdev = qdev_new(TYPE_NEXT_PC); 1249 object_property_set_link(OBJECT(pcdev), "cpu", OBJECT(cpu), &error_abort); 1250 sysbus_realize_and_unref(SYS_BUS_DEVICE(pcdev), &error_fatal); 1251 1252 /* 64MB RAM starting at 0x04000000 */ 1253 memory_region_add_subregion(sysmem, 0x04000000, machine->ram); 1254 1255 /* Framebuffer */ 1256 sysbus_create_simple(TYPE_NEXTFB, 0x0B000000, NULL); 1257 1258 /* MMIO */ 1259 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 0, 0x02005000); 1260 1261 /* BMAP IO - acts as a catch-all for now */ 1262 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02100000); 1263 1264 /* en network (dummy) */ 1265 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 1, 0x02106000); 1266 1267 /* unknown: Brightness control register? */ 1268 empty_slot_init("next.unknown.0", 0x02110000, 0x10); 1269 /* unknown: Magneto-Optical drive controller? */ 1270 empty_slot_init("next.unknown.1", 0x02112000, 0x10); 1271 1272 /* SCSI */ 1273 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 2, 0x02114000); 1274 /* Floppy */ 1275 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 3, 0x02114108); 1276 /* ESCC */ 1277 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 4, 0x02118000); 1278 1279 /* unknown: Serial clock configuration register? */ 1280 empty_slot_init("next.unknown.2", 0x02118004, 0x10); 1281 1282 /* Timer */ 1283 sysbus_mmio_map(SYS_BUS_DEVICE(pcdev), 5, 0x0211a000); 1284 1285 /* BMAP memory */ 1286 memory_region_init_ram_flags_nomigrate(&m->bmapm1, NULL, "next.bmapmem", 1287 64, RAM_SHARED, &error_fatal); 1288 memory_region_add_subregion(sysmem, 0x020c0000, &m->bmapm1); 1289 /* The Rev_2.5_v66.bin firmware accesses it at 0x820c0020, too */ 1290 memory_region_init_alias(&m->bmapm2, NULL, "next.bmapmem2", &m->bmapm1, 1291 0x0, 64); 1292 memory_region_add_subregion(sysmem, 0x820c0000, &m->bmapm2); 1293 1294 /* KBD */ 1295 sysbus_create_simple(TYPE_NEXTKBD, 0x0200e000, NULL); 1296 1297 /* Load ROM here */ 1298 memory_region_init_rom(&m->rom, NULL, "next.rom", 0x20000, &error_fatal); 1299 memory_region_add_subregion(sysmem, 0x01000000, &m->rom); 1300 memory_region_init_alias(&m->rom2, NULL, "next.rom2", &m->rom, 0x0, 1301 0x20000); 1302 memory_region_add_subregion(sysmem, 0x0, &m->rom2); 1303 if (load_image_targphys(bios_name, 0x01000000, 0x20000) < 8) { 1304 if (!qtest_enabled()) { 1305 error_report("Failed to load firmware '%s'.", bios_name); 1306 } 1307 } else { 1308 uint8_t *ptr; 1309 /* Initial PC is always at offset 4 in firmware binaries */ 1310 ptr = rom_ptr(0x01000004, 4); 1311 g_assert(ptr != NULL); 1312 env->pc = ldl_be_p(ptr); 1313 if (env->pc >= 0x01020000) { 1314 error_report("'%s' does not seem to be a valid firmware image.", 1315 bios_name); 1316 exit(1); 1317 } 1318 } 1319 1320 /* DMA */ 1321 memory_region_init_io(&m->dmamem, NULL, &next_dma_ops, machine, 1322 "next.dma", 0x5000); 1323 memory_region_add_subregion(sysmem, 0x02000000, &m->dmamem); 1324 } 1325 1326 static void next_machine_class_init(ObjectClass *oc, void *data) 1327 { 1328 MachineClass *mc = MACHINE_CLASS(oc); 1329 1330 mc->desc = "NeXT Cube"; 1331 mc->init = next_cube_init; 1332 mc->block_default_type = IF_SCSI; 1333 mc->default_ram_size = RAM_SIZE; 1334 mc->default_ram_id = "next.ram"; 1335 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m68040"); 1336 mc->no_cdrom = true; 1337 } 1338 1339 static const TypeInfo next_typeinfo = { 1340 .name = TYPE_NEXT_MACHINE, 1341 .parent = TYPE_MACHINE, 1342 .class_init = next_machine_class_init, 1343 .instance_size = sizeof(NeXTState), 1344 }; 1345 1346 static void next_register_type(void) 1347 { 1348 type_register_static(&next_typeinfo); 1349 type_register_static(&next_pc_info); 1350 type_register_static(&next_scsi_info); 1351 type_register_static(&next_rtc_info); 1352 } 1353 1354 type_init(next_register_type) 1355