1 /* 2 * ColdFire Interrupt Controller emulation. 3 * 4 * Copyright (c) 2007 CodeSourcery. 5 * 6 * This code is licensed under the GPL 7 */ 8 #include "qemu/osdep.h" 9 #include "hw/hw.h" 10 #include "hw/m68k/mcf.h" 11 #include "exec/address-spaces.h" 12 13 typedef struct { 14 MemoryRegion iomem; 15 uint64_t ipr; 16 uint64_t imr; 17 uint64_t ifr; 18 uint64_t enabled; 19 uint8_t icr[64]; 20 M68kCPU *cpu; 21 int active_vector; 22 } mcf_intc_state; 23 24 static void mcf_intc_update(mcf_intc_state *s) 25 { 26 uint64_t active; 27 int i; 28 int best; 29 int best_level; 30 31 active = (s->ipr | s->ifr) & s->enabled & ~s->imr; 32 best_level = 0; 33 best = 64; 34 if (active) { 35 for (i = 0; i < 64; i++) { 36 if ((active & 1) != 0 && s->icr[i] >= best_level) { 37 best_level = s->icr[i]; 38 best = i; 39 } 40 active >>= 1; 41 } 42 } 43 s->active_vector = ((best == 64) ? 24 : (best + 64)); 44 m68k_set_irq_level(s->cpu, best_level, s->active_vector); 45 } 46 47 static uint64_t mcf_intc_read(void *opaque, hwaddr addr, 48 unsigned size) 49 { 50 int offset; 51 mcf_intc_state *s = (mcf_intc_state *)opaque; 52 offset = addr & 0xff; 53 if (offset >= 0x40 && offset < 0x80) { 54 return s->icr[offset - 0x40]; 55 } 56 switch (offset) { 57 case 0x00: 58 return (uint32_t)(s->ipr >> 32); 59 case 0x04: 60 return (uint32_t)s->ipr; 61 case 0x08: 62 return (uint32_t)(s->imr >> 32); 63 case 0x0c: 64 return (uint32_t)s->imr; 65 case 0x10: 66 return (uint32_t)(s->ifr >> 32); 67 case 0x14: 68 return (uint32_t)s->ifr; 69 case 0xe0: /* SWIACK. */ 70 return s->active_vector; 71 case 0xe1: case 0xe2: case 0xe3: case 0xe4: 72 case 0xe5: case 0xe6: case 0xe7: 73 /* LnIACK */ 74 hw_error("mcf_intc_read: LnIACK not implemented\n"); 75 default: 76 return 0; 77 } 78 } 79 80 static void mcf_intc_write(void *opaque, hwaddr addr, 81 uint64_t val, unsigned size) 82 { 83 int offset; 84 mcf_intc_state *s = (mcf_intc_state *)opaque; 85 offset = addr & 0xff; 86 if (offset >= 0x40 && offset < 0x80) { 87 int n = offset - 0x40; 88 s->icr[n] = val; 89 if (val == 0) 90 s->enabled &= ~(1ull << n); 91 else 92 s->enabled |= (1ull << n); 93 mcf_intc_update(s); 94 return; 95 } 96 switch (offset) { 97 case 0x00: case 0x04: 98 /* Ignore IPR writes. */ 99 return; 100 case 0x08: 101 s->imr = (s->imr & 0xffffffff) | ((uint64_t)val << 32); 102 break; 103 case 0x0c: 104 s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val; 105 break; 106 case 0x1c: 107 if (val & 0x40) { 108 s->imr = ~0ull; 109 } else { 110 s->imr |= (0x1ull << (val & 0x3f)); 111 } 112 break; 113 case 0x1d: 114 if (val & 0x40) { 115 s->imr = 0ull; 116 } else { 117 s->imr &= ~(0x1ull << (val & 0x3f)); 118 } 119 break; 120 default: 121 hw_error("mcf_intc_write: Bad write offset %d\n", offset); 122 break; 123 } 124 mcf_intc_update(s); 125 } 126 127 static void mcf_intc_set_irq(void *opaque, int irq, int level) 128 { 129 mcf_intc_state *s = (mcf_intc_state *)opaque; 130 if (irq >= 64) 131 return; 132 if (level) 133 s->ipr |= 1ull << irq; 134 else 135 s->ipr &= ~(1ull << irq); 136 mcf_intc_update(s); 137 } 138 139 static void mcf_intc_reset(mcf_intc_state *s) 140 { 141 s->imr = ~0ull; 142 s->ipr = 0; 143 s->ifr = 0; 144 s->enabled = 0; 145 memset(s->icr, 0, 64); 146 s->active_vector = 24; 147 } 148 149 static const MemoryRegionOps mcf_intc_ops = { 150 .read = mcf_intc_read, 151 .write = mcf_intc_write, 152 .endianness = DEVICE_NATIVE_ENDIAN, 153 }; 154 155 qemu_irq *mcf_intc_init(MemoryRegion *sysmem, 156 hwaddr base, 157 M68kCPU *cpu) 158 { 159 mcf_intc_state *s; 160 161 s = g_malloc0(sizeof(mcf_intc_state)); 162 s->cpu = cpu; 163 mcf_intc_reset(s); 164 165 memory_region_init_io(&s->iomem, NULL, &mcf_intc_ops, s, "mcf", 0x100); 166 memory_region_add_subregion(sysmem, base, &s->iomem); 167 168 return qemu_allocate_irqs(mcf_intc_set_irq, s, 64); 169 } 170