1 /* 2 * ColdFire Interrupt Controller emulation. 3 * 4 * Copyright (c) 2007 CodeSourcery. 5 * 6 * This code is licensed under the GPL 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/module.h" 11 #include "qemu/log.h" 12 #include "cpu.h" 13 #include "hw/hw.h" 14 #include "hw/irq.h" 15 #include "hw/sysbus.h" 16 #include "hw/m68k/mcf.h" 17 18 #define TYPE_MCF_INTC "mcf-intc" 19 #define MCF_INTC(obj) OBJECT_CHECK(mcf_intc_state, (obj), TYPE_MCF_INTC) 20 21 typedef struct { 22 SysBusDevice parent_obj; 23 24 MemoryRegion iomem; 25 uint64_t ipr; 26 uint64_t imr; 27 uint64_t ifr; 28 uint64_t enabled; 29 uint8_t icr[64]; 30 M68kCPU *cpu; 31 int active_vector; 32 } mcf_intc_state; 33 34 static void mcf_intc_update(mcf_intc_state *s) 35 { 36 uint64_t active; 37 int i; 38 int best; 39 int best_level; 40 41 active = (s->ipr | s->ifr) & s->enabled & ~s->imr; 42 best_level = 0; 43 best = 64; 44 if (active) { 45 for (i = 0; i < 64; i++) { 46 if ((active & 1) != 0 && s->icr[i] >= best_level) { 47 best_level = s->icr[i]; 48 best = i; 49 } 50 active >>= 1; 51 } 52 } 53 s->active_vector = ((best == 64) ? 24 : (best + 64)); 54 m68k_set_irq_level(s->cpu, best_level, s->active_vector); 55 } 56 57 static uint64_t mcf_intc_read(void *opaque, hwaddr addr, 58 unsigned size) 59 { 60 int offset; 61 mcf_intc_state *s = (mcf_intc_state *)opaque; 62 offset = addr & 0xff; 63 if (offset >= 0x40 && offset < 0x80) { 64 return s->icr[offset - 0x40]; 65 } 66 switch (offset) { 67 case 0x00: 68 return (uint32_t)(s->ipr >> 32); 69 case 0x04: 70 return (uint32_t)s->ipr; 71 case 0x08: 72 return (uint32_t)(s->imr >> 32); 73 case 0x0c: 74 return (uint32_t)s->imr; 75 case 0x10: 76 return (uint32_t)(s->ifr >> 32); 77 case 0x14: 78 return (uint32_t)s->ifr; 79 case 0xe0: /* SWIACK. */ 80 return s->active_vector; 81 case 0xe1: case 0xe2: case 0xe3: case 0xe4: 82 case 0xe5: case 0xe6: case 0xe7: 83 /* LnIACK */ 84 qemu_log_mask(LOG_UNIMP, "%s: LnIACK not implemented (offset 0x%02x)\n", 85 __func__, offset); 86 /* fallthru */ 87 default: 88 return 0; 89 } 90 } 91 92 static void mcf_intc_write(void *opaque, hwaddr addr, 93 uint64_t val, unsigned size) 94 { 95 int offset; 96 mcf_intc_state *s = (mcf_intc_state *)opaque; 97 offset = addr & 0xff; 98 if (offset >= 0x40 && offset < 0x80) { 99 int n = offset - 0x40; 100 s->icr[n] = val; 101 if (val == 0) 102 s->enabled &= ~(1ull << n); 103 else 104 s->enabled |= (1ull << n); 105 mcf_intc_update(s); 106 return; 107 } 108 switch (offset) { 109 case 0x00: case 0x04: 110 /* Ignore IPR writes. */ 111 return; 112 case 0x08: 113 s->imr = (s->imr & 0xffffffff) | ((uint64_t)val << 32); 114 break; 115 case 0x0c: 116 s->imr = (s->imr & 0xffffffff00000000ull) | (uint32_t)val; 117 break; 118 case 0x1c: 119 if (val & 0x40) { 120 s->imr = ~0ull; 121 } else { 122 s->imr |= (0x1ull << (val & 0x3f)); 123 } 124 break; 125 case 0x1d: 126 if (val & 0x40) { 127 s->imr = 0ull; 128 } else { 129 s->imr &= ~(0x1ull << (val & 0x3f)); 130 } 131 break; 132 default: 133 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%02x\n", 134 __func__, offset); 135 return; 136 } 137 mcf_intc_update(s); 138 } 139 140 static void mcf_intc_set_irq(void *opaque, int irq, int level) 141 { 142 mcf_intc_state *s = (mcf_intc_state *)opaque; 143 if (irq >= 64) 144 return; 145 if (level) 146 s->ipr |= 1ull << irq; 147 else 148 s->ipr &= ~(1ull << irq); 149 mcf_intc_update(s); 150 } 151 152 static void mcf_intc_reset(DeviceState *dev) 153 { 154 mcf_intc_state *s = MCF_INTC(dev); 155 156 s->imr = ~0ull; 157 s->ipr = 0; 158 s->ifr = 0; 159 s->enabled = 0; 160 memset(s->icr, 0, 64); 161 s->active_vector = 24; 162 } 163 164 static const MemoryRegionOps mcf_intc_ops = { 165 .read = mcf_intc_read, 166 .write = mcf_intc_write, 167 .endianness = DEVICE_NATIVE_ENDIAN, 168 }; 169 170 static void mcf_intc_instance_init(Object *obj) 171 { 172 mcf_intc_state *s = MCF_INTC(obj); 173 174 memory_region_init_io(&s->iomem, obj, &mcf_intc_ops, s, "mcf", 0x100); 175 } 176 177 static void mcf_intc_class_init(ObjectClass *oc, void *data) 178 { 179 DeviceClass *dc = DEVICE_CLASS(oc); 180 181 set_bit(DEVICE_CATEGORY_MISC, dc->categories); 182 dc->reset = mcf_intc_reset; 183 } 184 185 static const TypeInfo mcf_intc_gate_info = { 186 .name = TYPE_MCF_INTC, 187 .parent = TYPE_SYS_BUS_DEVICE, 188 .instance_size = sizeof(mcf_intc_state), 189 .instance_init = mcf_intc_instance_init, 190 .class_init = mcf_intc_class_init, 191 }; 192 193 static void mcf_intc_register_types(void) 194 { 195 type_register_static(&mcf_intc_gate_info); 196 } 197 198 type_init(mcf_intc_register_types) 199 200 qemu_irq *mcf_intc_init(MemoryRegion *sysmem, 201 hwaddr base, 202 M68kCPU *cpu) 203 { 204 DeviceState *dev; 205 mcf_intc_state *s; 206 207 dev = qdev_create(NULL, TYPE_MCF_INTC); 208 qdev_init_nofail(dev); 209 210 s = MCF_INTC(dev); 211 s->cpu = cpu; 212 213 memory_region_add_subregion(sysmem, base, &s->iomem); 214 215 return qemu_allocate_irqs(mcf_intc_set_irq, s, 64); 216 } 217