1 /* 2 * Motorola ColdFire MCF5208 SoC emulation. 3 * 4 * Copyright (c) 2007 CodeSourcery. 5 * 6 * This code is licensed under the GPL 7 */ 8 #include "qemu/osdep.h" 9 #include "qapi/error.h" 10 #include "qemu-common.h" 11 #include "cpu.h" 12 #include "hw/hw.h" 13 #include "hw/m68k/mcf.h" 14 #include "hw/m68k/mcf_fec.h" 15 #include "qemu/timer.h" 16 #include "hw/ptimer.h" 17 #include "sysemu/sysemu.h" 18 #include "sysemu/qtest.h" 19 #include "net/net.h" 20 #include "hw/boards.h" 21 #include "hw/loader.h" 22 #include "hw/sysbus.h" 23 #include "elf.h" 24 #include "exec/address-spaces.h" 25 26 #define SYS_FREQ 166666666 27 28 #define PCSR_EN 0x0001 29 #define PCSR_RLD 0x0002 30 #define PCSR_PIF 0x0004 31 #define PCSR_PIE 0x0008 32 #define PCSR_OVW 0x0010 33 #define PCSR_DBG 0x0020 34 #define PCSR_DOZE 0x0040 35 #define PCSR_PRE_SHIFT 8 36 #define PCSR_PRE_MASK 0x0f00 37 38 typedef struct { 39 MemoryRegion iomem; 40 qemu_irq irq; 41 ptimer_state *timer; 42 uint16_t pcsr; 43 uint16_t pmr; 44 uint16_t pcntr; 45 } m5208_timer_state; 46 47 static void m5208_timer_update(m5208_timer_state *s) 48 { 49 if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF)) 50 qemu_irq_raise(s->irq); 51 else 52 qemu_irq_lower(s->irq); 53 } 54 55 static void m5208_timer_write(void *opaque, hwaddr offset, 56 uint64_t value, unsigned size) 57 { 58 m5208_timer_state *s = (m5208_timer_state *)opaque; 59 int prescale; 60 int limit; 61 switch (offset) { 62 case 0: 63 /* The PIF bit is set-to-clear. */ 64 if (value & PCSR_PIF) { 65 s->pcsr &= ~PCSR_PIF; 66 value &= ~PCSR_PIF; 67 } 68 /* Avoid frobbing the timer if we're just twiddling IRQ bits. */ 69 if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) { 70 s->pcsr = value; 71 m5208_timer_update(s); 72 return; 73 } 74 75 if (s->pcsr & PCSR_EN) 76 ptimer_stop(s->timer); 77 78 s->pcsr = value; 79 80 prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT); 81 ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale); 82 if (s->pcsr & PCSR_RLD) 83 limit = s->pmr; 84 else 85 limit = 0xffff; 86 ptimer_set_limit(s->timer, limit, 0); 87 88 if (s->pcsr & PCSR_EN) 89 ptimer_run(s->timer, 0); 90 break; 91 case 2: 92 s->pmr = value; 93 s->pcsr &= ~PCSR_PIF; 94 if ((s->pcsr & PCSR_RLD) == 0) { 95 if (s->pcsr & PCSR_OVW) 96 ptimer_set_count(s->timer, value); 97 } else { 98 ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW); 99 } 100 break; 101 case 4: 102 break; 103 default: 104 hw_error("m5208_timer_write: Bad offset 0x%x\n", (int)offset); 105 break; 106 } 107 m5208_timer_update(s); 108 } 109 110 static void m5208_timer_trigger(void *opaque) 111 { 112 m5208_timer_state *s = (m5208_timer_state *)opaque; 113 s->pcsr |= PCSR_PIF; 114 m5208_timer_update(s); 115 } 116 117 static uint64_t m5208_timer_read(void *opaque, hwaddr addr, 118 unsigned size) 119 { 120 m5208_timer_state *s = (m5208_timer_state *)opaque; 121 switch (addr) { 122 case 0: 123 return s->pcsr; 124 case 2: 125 return s->pmr; 126 case 4: 127 return ptimer_get_count(s->timer); 128 default: 129 hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr); 130 return 0; 131 } 132 } 133 134 static const MemoryRegionOps m5208_timer_ops = { 135 .read = m5208_timer_read, 136 .write = m5208_timer_write, 137 .endianness = DEVICE_NATIVE_ENDIAN, 138 }; 139 140 static uint64_t m5208_sys_read(void *opaque, hwaddr addr, 141 unsigned size) 142 { 143 switch (addr) { 144 case 0x110: /* SDCS0 */ 145 { 146 int n; 147 for (n = 0; n < 32; n++) { 148 if (ram_size < (2u << n)) 149 break; 150 } 151 return (n - 1) | 0x40000000; 152 } 153 case 0x114: /* SDCS1 */ 154 return 0; 155 156 default: 157 hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr); 158 return 0; 159 } 160 } 161 162 static void m5208_sys_write(void *opaque, hwaddr addr, 163 uint64_t value, unsigned size) 164 { 165 hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr); 166 } 167 168 static const MemoryRegionOps m5208_sys_ops = { 169 .read = m5208_sys_read, 170 .write = m5208_sys_write, 171 .endianness = DEVICE_NATIVE_ENDIAN, 172 }; 173 174 static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic) 175 { 176 MemoryRegion *iomem = g_new(MemoryRegion, 1); 177 m5208_timer_state *s; 178 QEMUBH *bh; 179 int i; 180 181 /* SDRAMC. */ 182 memory_region_init_io(iomem, NULL, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000); 183 memory_region_add_subregion(address_space, 0xfc0a8000, iomem); 184 /* Timers. */ 185 for (i = 0; i < 2; i++) { 186 s = (m5208_timer_state *)g_malloc0(sizeof(m5208_timer_state)); 187 bh = qemu_bh_new(m5208_timer_trigger, s); 188 s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); 189 memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s, 190 "m5208-timer", 0x00004000); 191 memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i, 192 &s->iomem); 193 s->irq = pic[4 + i]; 194 } 195 } 196 197 static void mcf_fec_init(MemoryRegion *sysmem, NICInfo *nd, hwaddr base, 198 qemu_irq *irqs) 199 { 200 DeviceState *dev; 201 SysBusDevice *s; 202 int i; 203 204 qemu_check_nic_model(nd, TYPE_MCF_FEC_NET); 205 dev = qdev_create(NULL, TYPE_MCF_FEC_NET); 206 qdev_set_nic_properties(dev, nd); 207 qdev_init_nofail(dev); 208 209 s = SYS_BUS_DEVICE(dev); 210 for (i = 0; i < FEC_NUM_IRQ; i++) { 211 sysbus_connect_irq(s, i, irqs[i]); 212 } 213 214 memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(s, 0)); 215 } 216 217 static void mcf5208evb_init(MachineState *machine) 218 { 219 ram_addr_t ram_size = machine->ram_size; 220 const char *cpu_model = machine->cpu_model; 221 const char *kernel_filename = machine->kernel_filename; 222 M68kCPU *cpu; 223 CPUM68KState *env; 224 int kernel_size; 225 uint64_t elf_entry; 226 hwaddr entry; 227 qemu_irq *pic; 228 MemoryRegion *address_space_mem = get_system_memory(); 229 MemoryRegion *ram = g_new(MemoryRegion, 1); 230 MemoryRegion *sram = g_new(MemoryRegion, 1); 231 232 if (!cpu_model) { 233 cpu_model = "m5208"; 234 } 235 cpu = cpu_m68k_init(cpu_model); 236 if (!cpu) { 237 fprintf(stderr, "Unable to find m68k CPU definition\n"); 238 exit(1); 239 } 240 env = &cpu->env; 241 242 /* Initialize CPU registers. */ 243 env->vbr = 0; 244 /* TODO: Configure BARs. */ 245 246 /* DRAM at 0x40000000 */ 247 memory_region_allocate_system_memory(ram, NULL, "mcf5208.ram", ram_size); 248 memory_region_add_subregion(address_space_mem, 0x40000000, ram); 249 250 /* Internal SRAM. */ 251 memory_region_init_ram(sram, NULL, "mcf5208.sram", 16384, &error_fatal); 252 vmstate_register_ram_global(sram); 253 memory_region_add_subregion(address_space_mem, 0x80000000, sram); 254 255 /* Internal peripherals. */ 256 pic = mcf_intc_init(address_space_mem, 0xfc048000, cpu); 257 258 mcf_uart_mm_init(0xfc060000, pic[26], serial_hds[0]); 259 mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]); 260 mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]); 261 262 mcf5208_sys_init(address_space_mem, pic); 263 264 if (nb_nics > 1) { 265 fprintf(stderr, "Too many NICs\n"); 266 exit(1); 267 } 268 if (nd_table[0].used) { 269 mcf_fec_init(address_space_mem, &nd_table[0], 270 0xfc030000, pic + 36); 271 } 272 273 /* 0xfc000000 SCM. */ 274 /* 0xfc004000 XBS. */ 275 /* 0xfc008000 FlexBus CS. */ 276 /* 0xfc030000 FEC. */ 277 /* 0xfc040000 SCM + Power management. */ 278 /* 0xfc044000 eDMA. */ 279 /* 0xfc048000 INTC. */ 280 /* 0xfc058000 I2C. */ 281 /* 0xfc05c000 QSPI. */ 282 /* 0xfc060000 UART0. */ 283 /* 0xfc064000 UART0. */ 284 /* 0xfc068000 UART0. */ 285 /* 0xfc070000 DMA timers. */ 286 /* 0xfc080000 PIT0. */ 287 /* 0xfc084000 PIT1. */ 288 /* 0xfc088000 EPORT. */ 289 /* 0xfc08c000 Watchdog. */ 290 /* 0xfc090000 clock module. */ 291 /* 0xfc0a0000 CCM + reset. */ 292 /* 0xfc0a4000 GPIO. */ 293 /* 0xfc0a8000 SDRAM controller. */ 294 295 /* Load kernel. */ 296 if (!kernel_filename) { 297 if (qtest_enabled()) { 298 return; 299 } 300 fprintf(stderr, "Kernel image must be specified\n"); 301 exit(1); 302 } 303 304 kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry, 305 NULL, NULL, 1, EM_68K, 0, 0); 306 entry = elf_entry; 307 if (kernel_size < 0) { 308 kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL, 309 NULL, NULL); 310 } 311 if (kernel_size < 0) { 312 kernel_size = load_image_targphys(kernel_filename, 0x40000000, 313 ram_size); 314 entry = 0x40000000; 315 } 316 if (kernel_size < 0) { 317 fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename); 318 exit(1); 319 } 320 321 env->pc = entry; 322 } 323 324 static void mcf5208evb_machine_init(MachineClass *mc) 325 { 326 mc->desc = "MCF5206EVB"; 327 mc->init = mcf5208evb_init; 328 mc->is_default = 1; 329 } 330 331 DEFINE_MACHINE("mcf5208evb", mcf5208evb_machine_init) 332