1 /* 2 * Motorola ColdFire MCF5208 SoC emulation. 3 * 4 * Copyright (c) 2007 CodeSourcery. 5 * 6 * This code is licensed under the GPL 7 */ 8 #include "qemu/osdep.h" 9 #include "qemu/error-report.h" 10 #include "qapi/error.h" 11 #include "qemu-common.h" 12 #include "cpu.h" 13 #include "hw/hw.h" 14 #include "hw/m68k/mcf.h" 15 #include "hw/m68k/mcf_fec.h" 16 #include "qemu/timer.h" 17 #include "hw/ptimer.h" 18 #include "sysemu/sysemu.h" 19 #include "sysemu/qtest.h" 20 #include "net/net.h" 21 #include "hw/boards.h" 22 #include "hw/loader.h" 23 #include "hw/sysbus.h" 24 #include "elf.h" 25 #include "exec/address-spaces.h" 26 27 #define SYS_FREQ 166666666 28 29 #define PCSR_EN 0x0001 30 #define PCSR_RLD 0x0002 31 #define PCSR_PIF 0x0004 32 #define PCSR_PIE 0x0008 33 #define PCSR_OVW 0x0010 34 #define PCSR_DBG 0x0020 35 #define PCSR_DOZE 0x0040 36 #define PCSR_PRE_SHIFT 8 37 #define PCSR_PRE_MASK 0x0f00 38 39 typedef struct { 40 MemoryRegion iomem; 41 qemu_irq irq; 42 ptimer_state *timer; 43 uint16_t pcsr; 44 uint16_t pmr; 45 uint16_t pcntr; 46 } m5208_timer_state; 47 48 static void m5208_timer_update(m5208_timer_state *s) 49 { 50 if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF)) 51 qemu_irq_raise(s->irq); 52 else 53 qemu_irq_lower(s->irq); 54 } 55 56 static void m5208_timer_write(void *opaque, hwaddr offset, 57 uint64_t value, unsigned size) 58 { 59 m5208_timer_state *s = (m5208_timer_state *)opaque; 60 int prescale; 61 int limit; 62 switch (offset) { 63 case 0: 64 /* The PIF bit is set-to-clear. */ 65 if (value & PCSR_PIF) { 66 s->pcsr &= ~PCSR_PIF; 67 value &= ~PCSR_PIF; 68 } 69 /* Avoid frobbing the timer if we're just twiddling IRQ bits. */ 70 if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) { 71 s->pcsr = value; 72 m5208_timer_update(s); 73 return; 74 } 75 76 if (s->pcsr & PCSR_EN) 77 ptimer_stop(s->timer); 78 79 s->pcsr = value; 80 81 prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT); 82 ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale); 83 if (s->pcsr & PCSR_RLD) 84 limit = s->pmr; 85 else 86 limit = 0xffff; 87 ptimer_set_limit(s->timer, limit, 0); 88 89 if (s->pcsr & PCSR_EN) 90 ptimer_run(s->timer, 0); 91 break; 92 case 2: 93 s->pmr = value; 94 s->pcsr &= ~PCSR_PIF; 95 if ((s->pcsr & PCSR_RLD) == 0) { 96 if (s->pcsr & PCSR_OVW) 97 ptimer_set_count(s->timer, value); 98 } else { 99 ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW); 100 } 101 break; 102 case 4: 103 break; 104 default: 105 hw_error("m5208_timer_write: Bad offset 0x%x\n", (int)offset); 106 break; 107 } 108 m5208_timer_update(s); 109 } 110 111 static void m5208_timer_trigger(void *opaque) 112 { 113 m5208_timer_state *s = (m5208_timer_state *)opaque; 114 s->pcsr |= PCSR_PIF; 115 m5208_timer_update(s); 116 } 117 118 static uint64_t m5208_timer_read(void *opaque, hwaddr addr, 119 unsigned size) 120 { 121 m5208_timer_state *s = (m5208_timer_state *)opaque; 122 switch (addr) { 123 case 0: 124 return s->pcsr; 125 case 2: 126 return s->pmr; 127 case 4: 128 return ptimer_get_count(s->timer); 129 default: 130 hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr); 131 return 0; 132 } 133 } 134 135 static const MemoryRegionOps m5208_timer_ops = { 136 .read = m5208_timer_read, 137 .write = m5208_timer_write, 138 .endianness = DEVICE_NATIVE_ENDIAN, 139 }; 140 141 static uint64_t m5208_sys_read(void *opaque, hwaddr addr, 142 unsigned size) 143 { 144 switch (addr) { 145 case 0x110: /* SDCS0 */ 146 { 147 int n; 148 for (n = 0; n < 32; n++) { 149 if (ram_size < (2u << n)) 150 break; 151 } 152 return (n - 1) | 0x40000000; 153 } 154 case 0x114: /* SDCS1 */ 155 return 0; 156 157 default: 158 hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr); 159 return 0; 160 } 161 } 162 163 static void m5208_sys_write(void *opaque, hwaddr addr, 164 uint64_t value, unsigned size) 165 { 166 hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr); 167 } 168 169 static const MemoryRegionOps m5208_sys_ops = { 170 .read = m5208_sys_read, 171 .write = m5208_sys_write, 172 .endianness = DEVICE_NATIVE_ENDIAN, 173 }; 174 175 static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic) 176 { 177 MemoryRegion *iomem = g_new(MemoryRegion, 1); 178 m5208_timer_state *s; 179 QEMUBH *bh; 180 int i; 181 182 /* SDRAMC. */ 183 memory_region_init_io(iomem, NULL, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000); 184 memory_region_add_subregion(address_space, 0xfc0a8000, iomem); 185 /* Timers. */ 186 for (i = 0; i < 2; i++) { 187 s = g_new0(m5208_timer_state, 1); 188 bh = qemu_bh_new(m5208_timer_trigger, s); 189 s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); 190 memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s, 191 "m5208-timer", 0x00004000); 192 memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i, 193 &s->iomem); 194 s->irq = pic[4 + i]; 195 } 196 } 197 198 static void mcf_fec_init(MemoryRegion *sysmem, NICInfo *nd, hwaddr base, 199 qemu_irq *irqs) 200 { 201 DeviceState *dev; 202 SysBusDevice *s; 203 int i; 204 205 qemu_check_nic_model(nd, TYPE_MCF_FEC_NET); 206 dev = qdev_create(NULL, TYPE_MCF_FEC_NET); 207 qdev_set_nic_properties(dev, nd); 208 qdev_init_nofail(dev); 209 210 s = SYS_BUS_DEVICE(dev); 211 for (i = 0; i < FEC_NUM_IRQ; i++) { 212 sysbus_connect_irq(s, i, irqs[i]); 213 } 214 215 memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(s, 0)); 216 } 217 218 static void mcf5208evb_init(MachineState *machine) 219 { 220 ram_addr_t ram_size = machine->ram_size; 221 const char *kernel_filename = machine->kernel_filename; 222 M68kCPU *cpu; 223 CPUM68KState *env; 224 int kernel_size; 225 uint64_t elf_entry; 226 hwaddr entry; 227 qemu_irq *pic; 228 MemoryRegion *address_space_mem = get_system_memory(); 229 MemoryRegion *ram = g_new(MemoryRegion, 1); 230 MemoryRegion *sram = g_new(MemoryRegion, 1); 231 232 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 233 env = &cpu->env; 234 235 /* Initialize CPU registers. */ 236 env->vbr = 0; 237 /* TODO: Configure BARs. */ 238 239 /* DRAM at 0x40000000 */ 240 memory_region_allocate_system_memory(ram, NULL, "mcf5208.ram", ram_size); 241 memory_region_add_subregion(address_space_mem, 0x40000000, ram); 242 243 /* Internal SRAM. */ 244 memory_region_init_ram(sram, NULL, "mcf5208.sram", 16384, &error_fatal); 245 memory_region_add_subregion(address_space_mem, 0x80000000, sram); 246 247 /* Internal peripherals. */ 248 pic = mcf_intc_init(address_space_mem, 0xfc048000, cpu); 249 250 mcf_uart_mm_init(0xfc060000, pic[26], serial_hds[0]); 251 mcf_uart_mm_init(0xfc064000, pic[27], serial_hds[1]); 252 mcf_uart_mm_init(0xfc068000, pic[28], serial_hds[2]); 253 254 mcf5208_sys_init(address_space_mem, pic); 255 256 if (nb_nics > 1) { 257 error_report("Too many NICs"); 258 exit(1); 259 } 260 if (nd_table[0].used) { 261 mcf_fec_init(address_space_mem, &nd_table[0], 262 0xfc030000, pic + 36); 263 } 264 265 /* 0xfc000000 SCM. */ 266 /* 0xfc004000 XBS. */ 267 /* 0xfc008000 FlexBus CS. */ 268 /* 0xfc030000 FEC. */ 269 /* 0xfc040000 SCM + Power management. */ 270 /* 0xfc044000 eDMA. */ 271 /* 0xfc048000 INTC. */ 272 /* 0xfc058000 I2C. */ 273 /* 0xfc05c000 QSPI. */ 274 /* 0xfc060000 UART0. */ 275 /* 0xfc064000 UART0. */ 276 /* 0xfc068000 UART0. */ 277 /* 0xfc070000 DMA timers. */ 278 /* 0xfc080000 PIT0. */ 279 /* 0xfc084000 PIT1. */ 280 /* 0xfc088000 EPORT. */ 281 /* 0xfc08c000 Watchdog. */ 282 /* 0xfc090000 clock module. */ 283 /* 0xfc0a0000 CCM + reset. */ 284 /* 0xfc0a4000 GPIO. */ 285 /* 0xfc0a8000 SDRAM controller. */ 286 287 /* Load kernel. */ 288 if (!kernel_filename) { 289 if (qtest_enabled()) { 290 return; 291 } 292 error_report("Kernel image must be specified"); 293 exit(1); 294 } 295 296 kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry, 297 NULL, NULL, 1, EM_68K, 0, 0); 298 entry = elf_entry; 299 if (kernel_size < 0) { 300 kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL, 301 NULL, NULL); 302 } 303 if (kernel_size < 0) { 304 kernel_size = load_image_targphys(kernel_filename, 0x40000000, 305 ram_size); 306 entry = 0x40000000; 307 } 308 if (kernel_size < 0) { 309 error_report("Could not load kernel '%s'", kernel_filename); 310 exit(1); 311 } 312 313 env->pc = entry; 314 } 315 316 static void mcf5208evb_machine_init(MachineClass *mc) 317 { 318 mc->desc = "MCF5206EVB"; 319 mc->init = mcf5208evb_init; 320 mc->is_default = 1; 321 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m5208"); 322 } 323 324 DEFINE_MACHINE("mcf5208evb", mcf5208evb_machine_init) 325