1 /* 2 * Motorola ColdFire MCF5208 SoC emulation. 3 * 4 * Copyright (c) 2007 CodeSourcery. 5 * 6 * This code is licensed under the GPL 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/units.h" 11 #include "qemu/error-report.h" 12 #include "qapi/error.h" 13 #include "qemu-common.h" 14 #include "cpu.h" 15 #include "hw/hw.h" 16 #include "hw/irq.h" 17 #include "hw/m68k/mcf.h" 18 #include "hw/m68k/mcf_fec.h" 19 #include "qemu/timer.h" 20 #include "hw/ptimer.h" 21 #include "sysemu/sysemu.h" 22 #include "sysemu/qtest.h" 23 #include "net/net.h" 24 #include "hw/boards.h" 25 #include "hw/loader.h" 26 #include "hw/sysbus.h" 27 #include "elf.h" 28 #include "exec/address-spaces.h" 29 30 #define SYS_FREQ 166666666 31 32 #define ROM_SIZE 0x200000 33 34 #define PCSR_EN 0x0001 35 #define PCSR_RLD 0x0002 36 #define PCSR_PIF 0x0004 37 #define PCSR_PIE 0x0008 38 #define PCSR_OVW 0x0010 39 #define PCSR_DBG 0x0020 40 #define PCSR_DOZE 0x0040 41 #define PCSR_PRE_SHIFT 8 42 #define PCSR_PRE_MASK 0x0f00 43 44 typedef struct { 45 MemoryRegion iomem; 46 qemu_irq irq; 47 ptimer_state *timer; 48 uint16_t pcsr; 49 uint16_t pmr; 50 uint16_t pcntr; 51 } m5208_timer_state; 52 53 static void m5208_timer_update(m5208_timer_state *s) 54 { 55 if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF)) 56 qemu_irq_raise(s->irq); 57 else 58 qemu_irq_lower(s->irq); 59 } 60 61 static void m5208_timer_write(void *opaque, hwaddr offset, 62 uint64_t value, unsigned size) 63 { 64 m5208_timer_state *s = (m5208_timer_state *)opaque; 65 int prescale; 66 int limit; 67 switch (offset) { 68 case 0: 69 /* The PIF bit is set-to-clear. */ 70 if (value & PCSR_PIF) { 71 s->pcsr &= ~PCSR_PIF; 72 value &= ~PCSR_PIF; 73 } 74 /* Avoid frobbing the timer if we're just twiddling IRQ bits. */ 75 if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) { 76 s->pcsr = value; 77 m5208_timer_update(s); 78 return; 79 } 80 81 if (s->pcsr & PCSR_EN) 82 ptimer_stop(s->timer); 83 84 s->pcsr = value; 85 86 prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT); 87 ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale); 88 if (s->pcsr & PCSR_RLD) 89 limit = s->pmr; 90 else 91 limit = 0xffff; 92 ptimer_set_limit(s->timer, limit, 0); 93 94 if (s->pcsr & PCSR_EN) 95 ptimer_run(s->timer, 0); 96 break; 97 case 2: 98 s->pmr = value; 99 s->pcsr &= ~PCSR_PIF; 100 if ((s->pcsr & PCSR_RLD) == 0) { 101 if (s->pcsr & PCSR_OVW) 102 ptimer_set_count(s->timer, value); 103 } else { 104 ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW); 105 } 106 break; 107 case 4: 108 break; 109 default: 110 hw_error("m5208_timer_write: Bad offset 0x%x\n", (int)offset); 111 break; 112 } 113 m5208_timer_update(s); 114 } 115 116 static void m5208_timer_trigger(void *opaque) 117 { 118 m5208_timer_state *s = (m5208_timer_state *)opaque; 119 s->pcsr |= PCSR_PIF; 120 m5208_timer_update(s); 121 } 122 123 static uint64_t m5208_timer_read(void *opaque, hwaddr addr, 124 unsigned size) 125 { 126 m5208_timer_state *s = (m5208_timer_state *)opaque; 127 switch (addr) { 128 case 0: 129 return s->pcsr; 130 case 2: 131 return s->pmr; 132 case 4: 133 return ptimer_get_count(s->timer); 134 default: 135 hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr); 136 return 0; 137 } 138 } 139 140 static const MemoryRegionOps m5208_timer_ops = { 141 .read = m5208_timer_read, 142 .write = m5208_timer_write, 143 .endianness = DEVICE_NATIVE_ENDIAN, 144 }; 145 146 static uint64_t m5208_sys_read(void *opaque, hwaddr addr, 147 unsigned size) 148 { 149 switch (addr) { 150 case 0x110: /* SDCS0 */ 151 { 152 int n; 153 for (n = 0; n < 32; n++) { 154 if (ram_size < (2u << n)) 155 break; 156 } 157 return (n - 1) | 0x40000000; 158 } 159 case 0x114: /* SDCS1 */ 160 return 0; 161 162 default: 163 hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr); 164 return 0; 165 } 166 } 167 168 static void m5208_sys_write(void *opaque, hwaddr addr, 169 uint64_t value, unsigned size) 170 { 171 hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr); 172 } 173 174 static const MemoryRegionOps m5208_sys_ops = { 175 .read = m5208_sys_read, 176 .write = m5208_sys_write, 177 .endianness = DEVICE_NATIVE_ENDIAN, 178 }; 179 180 static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic) 181 { 182 MemoryRegion *iomem = g_new(MemoryRegion, 1); 183 m5208_timer_state *s; 184 QEMUBH *bh; 185 int i; 186 187 /* SDRAMC. */ 188 memory_region_init_io(iomem, NULL, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000); 189 memory_region_add_subregion(address_space, 0xfc0a8000, iomem); 190 /* Timers. */ 191 for (i = 0; i < 2; i++) { 192 s = g_new0(m5208_timer_state, 1); 193 bh = qemu_bh_new(m5208_timer_trigger, s); 194 s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); 195 memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s, 196 "m5208-timer", 0x00004000); 197 memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i, 198 &s->iomem); 199 s->irq = pic[4 + i]; 200 } 201 } 202 203 static void mcf_fec_init(MemoryRegion *sysmem, NICInfo *nd, hwaddr base, 204 qemu_irq *irqs) 205 { 206 DeviceState *dev; 207 SysBusDevice *s; 208 int i; 209 210 qemu_check_nic_model(nd, TYPE_MCF_FEC_NET); 211 dev = qdev_create(NULL, TYPE_MCF_FEC_NET); 212 qdev_set_nic_properties(dev, nd); 213 qdev_init_nofail(dev); 214 215 s = SYS_BUS_DEVICE(dev); 216 for (i = 0; i < FEC_NUM_IRQ; i++) { 217 sysbus_connect_irq(s, i, irqs[i]); 218 } 219 220 memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(s, 0)); 221 } 222 223 static void mcf5208evb_init(MachineState *machine) 224 { 225 ram_addr_t ram_size = machine->ram_size; 226 const char *kernel_filename = machine->kernel_filename; 227 M68kCPU *cpu; 228 CPUM68KState *env; 229 int kernel_size; 230 uint64_t elf_entry; 231 hwaddr entry; 232 qemu_irq *pic; 233 MemoryRegion *address_space_mem = get_system_memory(); 234 MemoryRegion *rom = g_new(MemoryRegion, 1); 235 MemoryRegion *ram = g_new(MemoryRegion, 1); 236 MemoryRegion *sram = g_new(MemoryRegion, 1); 237 238 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 239 env = &cpu->env; 240 241 /* Initialize CPU registers. */ 242 env->vbr = 0; 243 /* TODO: Configure BARs. */ 244 245 /* ROM at 0x00000000 */ 246 memory_region_init_rom(rom, NULL, "mcf5208.rom", ROM_SIZE, &error_fatal); 247 memory_region_add_subregion(address_space_mem, 0x00000000, rom); 248 249 /* DRAM at 0x40000000 */ 250 memory_region_allocate_system_memory(ram, NULL, "mcf5208.ram", ram_size); 251 memory_region_add_subregion(address_space_mem, 0x40000000, ram); 252 253 /* Internal SRAM. */ 254 memory_region_init_ram(sram, NULL, "mcf5208.sram", 16 * KiB, &error_fatal); 255 memory_region_add_subregion(address_space_mem, 0x80000000, sram); 256 257 /* Internal peripherals. */ 258 pic = mcf_intc_init(address_space_mem, 0xfc048000, cpu); 259 260 mcf_uart_mm_init(0xfc060000, pic[26], serial_hd(0)); 261 mcf_uart_mm_init(0xfc064000, pic[27], serial_hd(1)); 262 mcf_uart_mm_init(0xfc068000, pic[28], serial_hd(2)); 263 264 mcf5208_sys_init(address_space_mem, pic); 265 266 if (nb_nics > 1) { 267 error_report("Too many NICs"); 268 exit(1); 269 } 270 if (nd_table[0].used) { 271 mcf_fec_init(address_space_mem, &nd_table[0], 272 0xfc030000, pic + 36); 273 } 274 275 /* 0xfc000000 SCM. */ 276 /* 0xfc004000 XBS. */ 277 /* 0xfc008000 FlexBus CS. */ 278 /* 0xfc030000 FEC. */ 279 /* 0xfc040000 SCM + Power management. */ 280 /* 0xfc044000 eDMA. */ 281 /* 0xfc048000 INTC. */ 282 /* 0xfc058000 I2C. */ 283 /* 0xfc05c000 QSPI. */ 284 /* 0xfc060000 UART0. */ 285 /* 0xfc064000 UART0. */ 286 /* 0xfc068000 UART0. */ 287 /* 0xfc070000 DMA timers. */ 288 /* 0xfc080000 PIT0. */ 289 /* 0xfc084000 PIT1. */ 290 /* 0xfc088000 EPORT. */ 291 /* 0xfc08c000 Watchdog. */ 292 /* 0xfc090000 clock module. */ 293 /* 0xfc0a0000 CCM + reset. */ 294 /* 0xfc0a4000 GPIO. */ 295 /* 0xfc0a8000 SDRAM controller. */ 296 297 /* Load firmware */ 298 if (bios_name) { 299 char *fn; 300 uint8_t *ptr; 301 302 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 303 if (!fn) { 304 error_report("Could not find ROM image '%s'", bios_name); 305 exit(1); 306 } 307 if (load_image_targphys(fn, 0x0, ROM_SIZE) < 8) { 308 error_report("Could not load ROM image '%s'", bios_name); 309 exit(1); 310 } 311 g_free(fn); 312 /* Initial PC is always at offset 4 in firmware binaries */ 313 ptr = rom_ptr(0x4, 4); 314 assert(ptr != NULL); 315 env->pc = ldl_p(ptr); 316 } 317 318 /* Load kernel. */ 319 if (!kernel_filename) { 320 if (qtest_enabled() || bios_name) { 321 return; 322 } 323 error_report("Kernel image must be specified"); 324 exit(1); 325 } 326 327 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry, 328 NULL, NULL, 1, EM_68K, 0, 0); 329 entry = elf_entry; 330 if (kernel_size < 0) { 331 kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL, 332 NULL, NULL); 333 } 334 if (kernel_size < 0) { 335 kernel_size = load_image_targphys(kernel_filename, 0x40000000, 336 ram_size); 337 entry = 0x40000000; 338 } 339 if (kernel_size < 0) { 340 error_report("Could not load kernel '%s'", kernel_filename); 341 exit(1); 342 } 343 344 env->pc = entry; 345 } 346 347 static void mcf5208evb_machine_init(MachineClass *mc) 348 { 349 mc->desc = "MCF5208EVB"; 350 mc->init = mcf5208evb_init; 351 mc->is_default = 1; 352 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m5208"); 353 } 354 355 DEFINE_MACHINE("mcf5208evb", mcf5208evb_machine_init) 356