1 /* 2 * Motorola ColdFire MCF5208 SoC emulation. 3 * 4 * Copyright (c) 2007 CodeSourcery. 5 * 6 * This code is licensed under the GPL 7 */ 8 #include "qemu/osdep.h" 9 #include "qapi/error.h" 10 #include "qemu-common.h" 11 #include "cpu.h" 12 #include "hw/hw.h" 13 #include "hw/m68k/mcf.h" 14 #include "qemu/timer.h" 15 #include "hw/ptimer.h" 16 #include "sysemu/sysemu.h" 17 #include "sysemu/qtest.h" 18 #include "net/net.h" 19 #include "hw/boards.h" 20 #include "hw/loader.h" 21 #include "elf.h" 22 #include "exec/address-spaces.h" 23 24 #define SYS_FREQ 166666666 25 26 #define PCSR_EN 0x0001 27 #define PCSR_RLD 0x0002 28 #define PCSR_PIF 0x0004 29 #define PCSR_PIE 0x0008 30 #define PCSR_OVW 0x0010 31 #define PCSR_DBG 0x0020 32 #define PCSR_DOZE 0x0040 33 #define PCSR_PRE_SHIFT 8 34 #define PCSR_PRE_MASK 0x0f00 35 36 typedef struct { 37 MemoryRegion iomem; 38 qemu_irq irq; 39 ptimer_state *timer; 40 uint16_t pcsr; 41 uint16_t pmr; 42 uint16_t pcntr; 43 } m5208_timer_state; 44 45 static void m5208_timer_update(m5208_timer_state *s) 46 { 47 if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF)) 48 qemu_irq_raise(s->irq); 49 else 50 qemu_irq_lower(s->irq); 51 } 52 53 static void m5208_timer_write(void *opaque, hwaddr offset, 54 uint64_t value, unsigned size) 55 { 56 m5208_timer_state *s = (m5208_timer_state *)opaque; 57 int prescale; 58 int limit; 59 switch (offset) { 60 case 0: 61 /* The PIF bit is set-to-clear. */ 62 if (value & PCSR_PIF) { 63 s->pcsr &= ~PCSR_PIF; 64 value &= ~PCSR_PIF; 65 } 66 /* Avoid frobbing the timer if we're just twiddling IRQ bits. */ 67 if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) { 68 s->pcsr = value; 69 m5208_timer_update(s); 70 return; 71 } 72 73 if (s->pcsr & PCSR_EN) 74 ptimer_stop(s->timer); 75 76 s->pcsr = value; 77 78 prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT); 79 ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale); 80 if (s->pcsr & PCSR_RLD) 81 limit = s->pmr; 82 else 83 limit = 0xffff; 84 ptimer_set_limit(s->timer, limit, 0); 85 86 if (s->pcsr & PCSR_EN) 87 ptimer_run(s->timer, 0); 88 break; 89 case 2: 90 s->pmr = value; 91 s->pcsr &= ~PCSR_PIF; 92 if ((s->pcsr & PCSR_RLD) == 0) { 93 if (s->pcsr & PCSR_OVW) 94 ptimer_set_count(s->timer, value); 95 } else { 96 ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW); 97 } 98 break; 99 case 4: 100 break; 101 default: 102 hw_error("m5208_timer_write: Bad offset 0x%x\n", (int)offset); 103 break; 104 } 105 m5208_timer_update(s); 106 } 107 108 static void m5208_timer_trigger(void *opaque) 109 { 110 m5208_timer_state *s = (m5208_timer_state *)opaque; 111 s->pcsr |= PCSR_PIF; 112 m5208_timer_update(s); 113 } 114 115 static uint64_t m5208_timer_read(void *opaque, hwaddr addr, 116 unsigned size) 117 { 118 m5208_timer_state *s = (m5208_timer_state *)opaque; 119 switch (addr) { 120 case 0: 121 return s->pcsr; 122 case 2: 123 return s->pmr; 124 case 4: 125 return ptimer_get_count(s->timer); 126 default: 127 hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr); 128 return 0; 129 } 130 } 131 132 static const MemoryRegionOps m5208_timer_ops = { 133 .read = m5208_timer_read, 134 .write = m5208_timer_write, 135 .endianness = DEVICE_NATIVE_ENDIAN, 136 }; 137 138 static uint64_t m5208_sys_read(void *opaque, hwaddr addr, 139 unsigned size) 140 { 141 switch (addr) { 142 case 0x110: /* SDCS0 */ 143 { 144 int n; 145 for (n = 0; n < 32; n++) { 146 if (ram_size < (2u << n)) 147 break; 148 } 149 return (n - 1) | 0x40000000; 150 } 151 case 0x114: /* SDCS1 */ 152 return 0; 153 154 default: 155 hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr); 156 return 0; 157 } 158 } 159 160 static void m5208_sys_write(void *opaque, hwaddr addr, 161 uint64_t value, unsigned size) 162 { 163 hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr); 164 } 165 166 static const MemoryRegionOps m5208_sys_ops = { 167 .read = m5208_sys_read, 168 .write = m5208_sys_write, 169 .endianness = DEVICE_NATIVE_ENDIAN, 170 }; 171 172 static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic) 173 { 174 MemoryRegion *iomem = g_new(MemoryRegion, 1); 175 m5208_timer_state *s; 176 QEMUBH *bh; 177 int i; 178 179 /* SDRAMC. */ 180 memory_region_init_io(iomem, NULL, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000); 181 memory_region_add_subregion(address_space, 0xfc0a8000, iomem); 182 /* Timers. */ 183 for (i = 0; i < 2; i++) { 184 s = (m5208_timer_state *)g_malloc0(sizeof(m5208_timer_state)); 185 bh = qemu_bh_new(m5208_timer_trigger, s); 186 s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); 187 memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s, 188 "m5208-timer", 0x00004000); 189 memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i, 190 &s->iomem); 191 s->irq = pic[4 + i]; 192 } 193 } 194 195 static void mcf5208evb_init(MachineState *machine) 196 { 197 ram_addr_t ram_size = machine->ram_size; 198 const char *cpu_model = machine->cpu_model; 199 const char *kernel_filename = machine->kernel_filename; 200 M68kCPU *cpu; 201 CPUM68KState *env; 202 int kernel_size; 203 uint64_t elf_entry; 204 hwaddr entry; 205 qemu_irq *pic; 206 MemoryRegion *address_space_mem = get_system_memory(); 207 MemoryRegion *ram = g_new(MemoryRegion, 1); 208 MemoryRegion *sram = g_new(MemoryRegion, 1); 209 210 if (!cpu_model) { 211 cpu_model = "m5208"; 212 } 213 cpu = cpu_m68k_init(cpu_model); 214 if (!cpu) { 215 fprintf(stderr, "Unable to find m68k CPU definition\n"); 216 exit(1); 217 } 218 env = &cpu->env; 219 220 /* Initialize CPU registers. */ 221 env->vbr = 0; 222 /* TODO: Configure BARs. */ 223 224 /* DRAM at 0x40000000 */ 225 memory_region_allocate_system_memory(ram, NULL, "mcf5208.ram", ram_size); 226 memory_region_add_subregion(address_space_mem, 0x40000000, ram); 227 228 /* Internal SRAM. */ 229 memory_region_init_ram(sram, NULL, "mcf5208.sram", 16384, &error_fatal); 230 vmstate_register_ram_global(sram); 231 memory_region_add_subregion(address_space_mem, 0x80000000, sram); 232 233 /* Internal peripherals. */ 234 pic = mcf_intc_init(address_space_mem, 0xfc048000, cpu); 235 236 mcf_uart_mm_init(address_space_mem, 0xfc060000, pic[26], serial_hds[0]); 237 mcf_uart_mm_init(address_space_mem, 0xfc064000, pic[27], serial_hds[1]); 238 mcf_uart_mm_init(address_space_mem, 0xfc068000, pic[28], serial_hds[2]); 239 240 mcf5208_sys_init(address_space_mem, pic); 241 242 if (nb_nics > 1) { 243 fprintf(stderr, "Too many NICs\n"); 244 exit(1); 245 } 246 if (nd_table[0].used) 247 mcf_fec_init(address_space_mem, &nd_table[0], 248 0xfc030000, pic + 36); 249 250 /* 0xfc000000 SCM. */ 251 /* 0xfc004000 XBS. */ 252 /* 0xfc008000 FlexBus CS. */ 253 /* 0xfc030000 FEC. */ 254 /* 0xfc040000 SCM + Power management. */ 255 /* 0xfc044000 eDMA. */ 256 /* 0xfc048000 INTC. */ 257 /* 0xfc058000 I2C. */ 258 /* 0xfc05c000 QSPI. */ 259 /* 0xfc060000 UART0. */ 260 /* 0xfc064000 UART0. */ 261 /* 0xfc068000 UART0. */ 262 /* 0xfc070000 DMA timers. */ 263 /* 0xfc080000 PIT0. */ 264 /* 0xfc084000 PIT1. */ 265 /* 0xfc088000 EPORT. */ 266 /* 0xfc08c000 Watchdog. */ 267 /* 0xfc090000 clock module. */ 268 /* 0xfc0a0000 CCM + reset. */ 269 /* 0xfc0a4000 GPIO. */ 270 /* 0xfc0a8000 SDRAM controller. */ 271 272 /* Load kernel. */ 273 if (!kernel_filename) { 274 if (qtest_enabled()) { 275 return; 276 } 277 fprintf(stderr, "Kernel image must be specified\n"); 278 exit(1); 279 } 280 281 kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry, 282 NULL, NULL, 1, EM_68K, 0, 0); 283 entry = elf_entry; 284 if (kernel_size < 0) { 285 kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL, 286 NULL, NULL); 287 } 288 if (kernel_size < 0) { 289 kernel_size = load_image_targphys(kernel_filename, 0x40000000, 290 ram_size); 291 entry = 0x40000000; 292 } 293 if (kernel_size < 0) { 294 fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename); 295 exit(1); 296 } 297 298 env->pc = entry; 299 } 300 301 static void mcf5208evb_machine_init(MachineClass *mc) 302 { 303 mc->desc = "MCF5206EVB"; 304 mc->init = mcf5208evb_init; 305 mc->is_default = 1; 306 } 307 308 DEFINE_MACHINE("mcf5208evb", mcf5208evb_machine_init) 309