1 /* 2 * Motorola ColdFire MCF5208 SoC emulation. 3 * 4 * Copyright (c) 2007 CodeSourcery. 5 * 6 * This code is licensed under the GPL 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/units.h" 11 #include "qemu/error-report.h" 12 #include "qemu/log.h" 13 #include "qapi/error.h" 14 #include "qemu-common.h" 15 #include "cpu.h" 16 #include "hw/irq.h" 17 #include "hw/m68k/mcf.h" 18 #include "hw/m68k/mcf_fec.h" 19 #include "qemu/timer.h" 20 #include "hw/ptimer.h" 21 #include "sysemu/sysemu.h" 22 #include "sysemu/qtest.h" 23 #include "net/net.h" 24 #include "hw/boards.h" 25 #include "hw/loader.h" 26 #include "hw/sysbus.h" 27 #include "elf.h" 28 #include "exec/address-spaces.h" 29 30 #define SYS_FREQ 166666666 31 32 #define ROM_SIZE 0x200000 33 34 #define PCSR_EN 0x0001 35 #define PCSR_RLD 0x0002 36 #define PCSR_PIF 0x0004 37 #define PCSR_PIE 0x0008 38 #define PCSR_OVW 0x0010 39 #define PCSR_DBG 0x0020 40 #define PCSR_DOZE 0x0040 41 #define PCSR_PRE_SHIFT 8 42 #define PCSR_PRE_MASK 0x0f00 43 44 typedef struct { 45 MemoryRegion iomem; 46 qemu_irq irq; 47 ptimer_state *timer; 48 uint16_t pcsr; 49 uint16_t pmr; 50 uint16_t pcntr; 51 } m5208_timer_state; 52 53 static void m5208_timer_update(m5208_timer_state *s) 54 { 55 if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF)) 56 qemu_irq_raise(s->irq); 57 else 58 qemu_irq_lower(s->irq); 59 } 60 61 static void m5208_timer_write(void *opaque, hwaddr offset, 62 uint64_t value, unsigned size) 63 { 64 m5208_timer_state *s = (m5208_timer_state *)opaque; 65 int prescale; 66 int limit; 67 switch (offset) { 68 case 0: 69 /* The PIF bit is set-to-clear. */ 70 if (value & PCSR_PIF) { 71 s->pcsr &= ~PCSR_PIF; 72 value &= ~PCSR_PIF; 73 } 74 /* Avoid frobbing the timer if we're just twiddling IRQ bits. */ 75 if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) { 76 s->pcsr = value; 77 m5208_timer_update(s); 78 return; 79 } 80 81 ptimer_transaction_begin(s->timer); 82 if (s->pcsr & PCSR_EN) 83 ptimer_stop(s->timer); 84 85 s->pcsr = value; 86 87 prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT); 88 ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale); 89 if (s->pcsr & PCSR_RLD) 90 limit = s->pmr; 91 else 92 limit = 0xffff; 93 ptimer_set_limit(s->timer, limit, 0); 94 95 if (s->pcsr & PCSR_EN) 96 ptimer_run(s->timer, 0); 97 ptimer_transaction_commit(s->timer); 98 break; 99 case 2: 100 ptimer_transaction_begin(s->timer); 101 s->pmr = value; 102 s->pcsr &= ~PCSR_PIF; 103 if ((s->pcsr & PCSR_RLD) == 0) { 104 if (s->pcsr & PCSR_OVW) 105 ptimer_set_count(s->timer, value); 106 } else { 107 ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW); 108 } 109 ptimer_transaction_commit(s->timer); 110 break; 111 case 4: 112 break; 113 default: 114 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 115 __func__, offset); 116 return; 117 } 118 m5208_timer_update(s); 119 } 120 121 static void m5208_timer_trigger(void *opaque) 122 { 123 m5208_timer_state *s = (m5208_timer_state *)opaque; 124 s->pcsr |= PCSR_PIF; 125 m5208_timer_update(s); 126 } 127 128 static uint64_t m5208_timer_read(void *opaque, hwaddr addr, 129 unsigned size) 130 { 131 m5208_timer_state *s = (m5208_timer_state *)opaque; 132 switch (addr) { 133 case 0: 134 return s->pcsr; 135 case 2: 136 return s->pmr; 137 case 4: 138 return ptimer_get_count(s->timer); 139 default: 140 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 141 __func__, addr); 142 return 0; 143 } 144 } 145 146 static const MemoryRegionOps m5208_timer_ops = { 147 .read = m5208_timer_read, 148 .write = m5208_timer_write, 149 .endianness = DEVICE_NATIVE_ENDIAN, 150 }; 151 152 static uint64_t m5208_sys_read(void *opaque, hwaddr addr, 153 unsigned size) 154 { 155 switch (addr) { 156 case 0x110: /* SDCS0 */ 157 { 158 int n; 159 for (n = 0; n < 32; n++) { 160 if (ram_size < (2u << n)) 161 break; 162 } 163 return (n - 1) | 0x40000000; 164 } 165 case 0x114: /* SDCS1 */ 166 return 0; 167 168 default: 169 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 170 __func__, addr); 171 return 0; 172 } 173 } 174 175 static void m5208_sys_write(void *opaque, hwaddr addr, 176 uint64_t value, unsigned size) 177 { 178 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 179 __func__, addr); 180 } 181 182 static const MemoryRegionOps m5208_sys_ops = { 183 .read = m5208_sys_read, 184 .write = m5208_sys_write, 185 .endianness = DEVICE_NATIVE_ENDIAN, 186 }; 187 188 static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic) 189 { 190 MemoryRegion *iomem = g_new(MemoryRegion, 1); 191 m5208_timer_state *s; 192 int i; 193 194 /* SDRAMC. */ 195 memory_region_init_io(iomem, NULL, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000); 196 memory_region_add_subregion(address_space, 0xfc0a8000, iomem); 197 /* Timers. */ 198 for (i = 0; i < 2; i++) { 199 s = g_new0(m5208_timer_state, 1); 200 s->timer = ptimer_init(m5208_timer_trigger, s, PTIMER_POLICY_DEFAULT); 201 memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s, 202 "m5208-timer", 0x00004000); 203 memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i, 204 &s->iomem); 205 s->irq = pic[4 + i]; 206 } 207 } 208 209 static void mcf_fec_init(MemoryRegion *sysmem, NICInfo *nd, hwaddr base, 210 qemu_irq *irqs) 211 { 212 DeviceState *dev; 213 SysBusDevice *s; 214 int i; 215 216 qemu_check_nic_model(nd, TYPE_MCF_FEC_NET); 217 dev = qdev_new(TYPE_MCF_FEC_NET); 218 qdev_set_nic_properties(dev, nd); 219 220 s = SYS_BUS_DEVICE(dev); 221 sysbus_realize_and_unref(s, &error_fatal); 222 for (i = 0; i < FEC_NUM_IRQ; i++) { 223 sysbus_connect_irq(s, i, irqs[i]); 224 } 225 226 memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(s, 0)); 227 } 228 229 static void mcf5208evb_init(MachineState *machine) 230 { 231 ram_addr_t ram_size = machine->ram_size; 232 const char *kernel_filename = machine->kernel_filename; 233 M68kCPU *cpu; 234 CPUM68KState *env; 235 int kernel_size; 236 uint64_t elf_entry; 237 hwaddr entry; 238 qemu_irq *pic; 239 MemoryRegion *address_space_mem = get_system_memory(); 240 MemoryRegion *rom = g_new(MemoryRegion, 1); 241 MemoryRegion *sram = g_new(MemoryRegion, 1); 242 243 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 244 env = &cpu->env; 245 246 /* Initialize CPU registers. */ 247 env->vbr = 0; 248 /* TODO: Configure BARs. */ 249 250 /* ROM at 0x00000000 */ 251 memory_region_init_rom(rom, NULL, "mcf5208.rom", ROM_SIZE, &error_fatal); 252 memory_region_add_subregion(address_space_mem, 0x00000000, rom); 253 254 /* DRAM at 0x40000000 */ 255 memory_region_add_subregion(address_space_mem, 0x40000000, machine->ram); 256 257 /* Internal SRAM. */ 258 memory_region_init_ram(sram, NULL, "mcf5208.sram", 16 * KiB, &error_fatal); 259 memory_region_add_subregion(address_space_mem, 0x80000000, sram); 260 261 /* Internal peripherals. */ 262 pic = mcf_intc_init(address_space_mem, 0xfc048000, cpu); 263 264 mcf_uart_mm_init(0xfc060000, pic[26], serial_hd(0)); 265 mcf_uart_mm_init(0xfc064000, pic[27], serial_hd(1)); 266 mcf_uart_mm_init(0xfc068000, pic[28], serial_hd(2)); 267 268 mcf5208_sys_init(address_space_mem, pic); 269 270 if (nb_nics > 1) { 271 error_report("Too many NICs"); 272 exit(1); 273 } 274 if (nd_table[0].used) { 275 mcf_fec_init(address_space_mem, &nd_table[0], 276 0xfc030000, pic + 36); 277 } 278 279 g_free(pic); 280 281 /* 0xfc000000 SCM. */ 282 /* 0xfc004000 XBS. */ 283 /* 0xfc008000 FlexBus CS. */ 284 /* 0xfc030000 FEC. */ 285 /* 0xfc040000 SCM + Power management. */ 286 /* 0xfc044000 eDMA. */ 287 /* 0xfc048000 INTC. */ 288 /* 0xfc058000 I2C. */ 289 /* 0xfc05c000 QSPI. */ 290 /* 0xfc060000 UART0. */ 291 /* 0xfc064000 UART0. */ 292 /* 0xfc068000 UART0. */ 293 /* 0xfc070000 DMA timers. */ 294 /* 0xfc080000 PIT0. */ 295 /* 0xfc084000 PIT1. */ 296 /* 0xfc088000 EPORT. */ 297 /* 0xfc08c000 Watchdog. */ 298 /* 0xfc090000 clock module. */ 299 /* 0xfc0a0000 CCM + reset. */ 300 /* 0xfc0a4000 GPIO. */ 301 /* 0xfc0a8000 SDRAM controller. */ 302 303 /* Load firmware */ 304 if (bios_name) { 305 char *fn; 306 uint8_t *ptr; 307 308 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); 309 if (!fn) { 310 error_report("Could not find ROM image '%s'", bios_name); 311 exit(1); 312 } 313 if (load_image_targphys(fn, 0x0, ROM_SIZE) < 8) { 314 error_report("Could not load ROM image '%s'", bios_name); 315 exit(1); 316 } 317 g_free(fn); 318 /* Initial PC is always at offset 4 in firmware binaries */ 319 ptr = rom_ptr(0x4, 4); 320 assert(ptr != NULL); 321 env->pc = ldl_p(ptr); 322 } 323 324 /* Load kernel. */ 325 if (!kernel_filename) { 326 if (qtest_enabled() || bios_name) { 327 return; 328 } 329 error_report("Kernel image must be specified"); 330 exit(1); 331 } 332 333 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry, 334 NULL, NULL, NULL, 1, EM_68K, 0, 0); 335 entry = elf_entry; 336 if (kernel_size < 0) { 337 kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL, 338 NULL, NULL); 339 } 340 if (kernel_size < 0) { 341 kernel_size = load_image_targphys(kernel_filename, 0x40000000, 342 ram_size); 343 entry = 0x40000000; 344 } 345 if (kernel_size < 0) { 346 error_report("Could not load kernel '%s'", kernel_filename); 347 exit(1); 348 } 349 350 env->pc = entry; 351 } 352 353 static void mcf5208evb_machine_init(MachineClass *mc) 354 { 355 mc->desc = "MCF5208EVB"; 356 mc->init = mcf5208evb_init; 357 mc->is_default = true; 358 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m5208"); 359 mc->default_ram_id = "mcf5208.ram"; 360 } 361 362 DEFINE_MACHINE("mcf5208evb", mcf5208evb_machine_init) 363