1 /* 2 * Motorola ColdFire MCF5208 SoC emulation. 3 * 4 * Copyright (c) 2007 CodeSourcery. 5 * 6 * This code is licensed under the GPL 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/units.h" 11 #include "qemu/error-report.h" 12 #include "qemu/log.h" 13 #include "qapi/error.h" 14 #include "qemu-common.h" 15 #include "qemu/datadir.h" 16 #include "cpu.h" 17 #include "hw/irq.h" 18 #include "hw/m68k/mcf.h" 19 #include "hw/m68k/mcf_fec.h" 20 #include "qemu/timer.h" 21 #include "hw/ptimer.h" 22 #include "sysemu/sysemu.h" 23 #include "sysemu/qtest.h" 24 #include "net/net.h" 25 #include "hw/boards.h" 26 #include "hw/loader.h" 27 #include "hw/sysbus.h" 28 #include "elf.h" 29 #include "exec/address-spaces.h" 30 31 #define SYS_FREQ 166666666 32 33 #define ROM_SIZE 0x200000 34 35 #define PCSR_EN 0x0001 36 #define PCSR_RLD 0x0002 37 #define PCSR_PIF 0x0004 38 #define PCSR_PIE 0x0008 39 #define PCSR_OVW 0x0010 40 #define PCSR_DBG 0x0020 41 #define PCSR_DOZE 0x0040 42 #define PCSR_PRE_SHIFT 8 43 #define PCSR_PRE_MASK 0x0f00 44 45 typedef struct { 46 MemoryRegion iomem; 47 qemu_irq irq; 48 ptimer_state *timer; 49 uint16_t pcsr; 50 uint16_t pmr; 51 uint16_t pcntr; 52 } m5208_timer_state; 53 54 static void m5208_timer_update(m5208_timer_state *s) 55 { 56 if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF)) 57 qemu_irq_raise(s->irq); 58 else 59 qemu_irq_lower(s->irq); 60 } 61 62 static void m5208_timer_write(void *opaque, hwaddr offset, 63 uint64_t value, unsigned size) 64 { 65 m5208_timer_state *s = (m5208_timer_state *)opaque; 66 int prescale; 67 int limit; 68 switch (offset) { 69 case 0: 70 /* The PIF bit is set-to-clear. */ 71 if (value & PCSR_PIF) { 72 s->pcsr &= ~PCSR_PIF; 73 value &= ~PCSR_PIF; 74 } 75 /* Avoid frobbing the timer if we're just twiddling IRQ bits. */ 76 if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) { 77 s->pcsr = value; 78 m5208_timer_update(s); 79 return; 80 } 81 82 ptimer_transaction_begin(s->timer); 83 if (s->pcsr & PCSR_EN) 84 ptimer_stop(s->timer); 85 86 s->pcsr = value; 87 88 prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT); 89 ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale); 90 if (s->pcsr & PCSR_RLD) 91 limit = s->pmr; 92 else 93 limit = 0xffff; 94 ptimer_set_limit(s->timer, limit, 0); 95 96 if (s->pcsr & PCSR_EN) 97 ptimer_run(s->timer, 0); 98 ptimer_transaction_commit(s->timer); 99 break; 100 case 2: 101 ptimer_transaction_begin(s->timer); 102 s->pmr = value; 103 s->pcsr &= ~PCSR_PIF; 104 if ((s->pcsr & PCSR_RLD) == 0) { 105 if (s->pcsr & PCSR_OVW) 106 ptimer_set_count(s->timer, value); 107 } else { 108 ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW); 109 } 110 ptimer_transaction_commit(s->timer); 111 break; 112 case 4: 113 break; 114 default: 115 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 116 __func__, offset); 117 return; 118 } 119 m5208_timer_update(s); 120 } 121 122 static void m5208_timer_trigger(void *opaque) 123 { 124 m5208_timer_state *s = (m5208_timer_state *)opaque; 125 s->pcsr |= PCSR_PIF; 126 m5208_timer_update(s); 127 } 128 129 static uint64_t m5208_timer_read(void *opaque, hwaddr addr, 130 unsigned size) 131 { 132 m5208_timer_state *s = (m5208_timer_state *)opaque; 133 switch (addr) { 134 case 0: 135 return s->pcsr; 136 case 2: 137 return s->pmr; 138 case 4: 139 return ptimer_get_count(s->timer); 140 default: 141 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 142 __func__, addr); 143 return 0; 144 } 145 } 146 147 static const MemoryRegionOps m5208_timer_ops = { 148 .read = m5208_timer_read, 149 .write = m5208_timer_write, 150 .endianness = DEVICE_NATIVE_ENDIAN, 151 }; 152 153 static uint64_t m5208_sys_read(void *opaque, hwaddr addr, 154 unsigned size) 155 { 156 switch (addr) { 157 case 0x110: /* SDCS0 */ 158 { 159 int n; 160 for (n = 0; n < 32; n++) { 161 if (current_machine->ram_size < (2u << n)) { 162 break; 163 } 164 } 165 return (n - 1) | 0x40000000; 166 } 167 case 0x114: /* SDCS1 */ 168 return 0; 169 170 default: 171 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 172 __func__, addr); 173 return 0; 174 } 175 } 176 177 static void m5208_sys_write(void *opaque, hwaddr addr, 178 uint64_t value, unsigned size) 179 { 180 qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset 0x%" HWADDR_PRIX "\n", 181 __func__, addr); 182 } 183 184 static const MemoryRegionOps m5208_sys_ops = { 185 .read = m5208_sys_read, 186 .write = m5208_sys_write, 187 .endianness = DEVICE_NATIVE_ENDIAN, 188 }; 189 190 static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic) 191 { 192 MemoryRegion *iomem = g_new(MemoryRegion, 1); 193 m5208_timer_state *s; 194 int i; 195 196 /* SDRAMC. */ 197 memory_region_init_io(iomem, NULL, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000); 198 memory_region_add_subregion(address_space, 0xfc0a8000, iomem); 199 /* Timers. */ 200 for (i = 0; i < 2; i++) { 201 s = g_new0(m5208_timer_state, 1); 202 s->timer = ptimer_init(m5208_timer_trigger, s, PTIMER_POLICY_DEFAULT); 203 memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s, 204 "m5208-timer", 0x00004000); 205 memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i, 206 &s->iomem); 207 s->irq = pic[4 + i]; 208 } 209 } 210 211 static void mcf_fec_init(MemoryRegion *sysmem, NICInfo *nd, hwaddr base, 212 qemu_irq *irqs) 213 { 214 DeviceState *dev; 215 SysBusDevice *s; 216 int i; 217 218 qemu_check_nic_model(nd, TYPE_MCF_FEC_NET); 219 dev = qdev_new(TYPE_MCF_FEC_NET); 220 qdev_set_nic_properties(dev, nd); 221 222 s = SYS_BUS_DEVICE(dev); 223 sysbus_realize_and_unref(s, &error_fatal); 224 for (i = 0; i < FEC_NUM_IRQ; i++) { 225 sysbus_connect_irq(s, i, irqs[i]); 226 } 227 228 memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(s, 0)); 229 } 230 231 static void mcf5208evb_init(MachineState *machine) 232 { 233 ram_addr_t ram_size = machine->ram_size; 234 const char *kernel_filename = machine->kernel_filename; 235 M68kCPU *cpu; 236 CPUM68KState *env; 237 int kernel_size; 238 uint64_t elf_entry; 239 hwaddr entry; 240 qemu_irq *pic; 241 MemoryRegion *address_space_mem = get_system_memory(); 242 MemoryRegion *rom = g_new(MemoryRegion, 1); 243 MemoryRegion *sram = g_new(MemoryRegion, 1); 244 245 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 246 env = &cpu->env; 247 248 /* Initialize CPU registers. */ 249 env->vbr = 0; 250 /* TODO: Configure BARs. */ 251 252 /* ROM at 0x00000000 */ 253 memory_region_init_rom(rom, NULL, "mcf5208.rom", ROM_SIZE, &error_fatal); 254 memory_region_add_subregion(address_space_mem, 0x00000000, rom); 255 256 /* DRAM at 0x40000000 */ 257 memory_region_add_subregion(address_space_mem, 0x40000000, machine->ram); 258 259 /* Internal SRAM. */ 260 memory_region_init_ram(sram, NULL, "mcf5208.sram", 16 * KiB, &error_fatal); 261 memory_region_add_subregion(address_space_mem, 0x80000000, sram); 262 263 /* Internal peripherals. */ 264 pic = mcf_intc_init(address_space_mem, 0xfc048000, cpu); 265 266 mcf_uart_mm_init(0xfc060000, pic[26], serial_hd(0)); 267 mcf_uart_mm_init(0xfc064000, pic[27], serial_hd(1)); 268 mcf_uart_mm_init(0xfc068000, pic[28], serial_hd(2)); 269 270 mcf5208_sys_init(address_space_mem, pic); 271 272 if (nb_nics > 1) { 273 error_report("Too many NICs"); 274 exit(1); 275 } 276 if (nd_table[0].used) { 277 mcf_fec_init(address_space_mem, &nd_table[0], 278 0xfc030000, pic + 36); 279 } 280 281 g_free(pic); 282 283 /* 0xfc000000 SCM. */ 284 /* 0xfc004000 XBS. */ 285 /* 0xfc008000 FlexBus CS. */ 286 /* 0xfc030000 FEC. */ 287 /* 0xfc040000 SCM + Power management. */ 288 /* 0xfc044000 eDMA. */ 289 /* 0xfc048000 INTC. */ 290 /* 0xfc058000 I2C. */ 291 /* 0xfc05c000 QSPI. */ 292 /* 0xfc060000 UART0. */ 293 /* 0xfc064000 UART0. */ 294 /* 0xfc068000 UART0. */ 295 /* 0xfc070000 DMA timers. */ 296 /* 0xfc080000 PIT0. */ 297 /* 0xfc084000 PIT1. */ 298 /* 0xfc088000 EPORT. */ 299 /* 0xfc08c000 Watchdog. */ 300 /* 0xfc090000 clock module. */ 301 /* 0xfc0a0000 CCM + reset. */ 302 /* 0xfc0a4000 GPIO. */ 303 /* 0xfc0a8000 SDRAM controller. */ 304 305 /* Load firmware */ 306 if (machine->firmware) { 307 char *fn; 308 uint8_t *ptr; 309 310 fn = qemu_find_file(QEMU_FILE_TYPE_BIOS, machine->firmware); 311 if (!fn) { 312 error_report("Could not find ROM image '%s'", machine->firmware); 313 exit(1); 314 } 315 if (load_image_targphys(fn, 0x0, ROM_SIZE) < 8) { 316 error_report("Could not load ROM image '%s'", machine->firmware); 317 exit(1); 318 } 319 g_free(fn); 320 /* Initial PC is always at offset 4 in firmware binaries */ 321 ptr = rom_ptr(0x4, 4); 322 assert(ptr != NULL); 323 env->pc = ldl_p(ptr); 324 } 325 326 /* Load kernel. */ 327 if (!kernel_filename) { 328 if (qtest_enabled() || machine->firmware) { 329 return; 330 } 331 error_report("Kernel image must be specified"); 332 exit(1); 333 } 334 335 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, &elf_entry, 336 NULL, NULL, NULL, 1, EM_68K, 0, 0); 337 entry = elf_entry; 338 if (kernel_size < 0) { 339 kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL, 340 NULL, NULL); 341 } 342 if (kernel_size < 0) { 343 kernel_size = load_image_targphys(kernel_filename, 0x40000000, 344 ram_size); 345 entry = 0x40000000; 346 } 347 if (kernel_size < 0) { 348 error_report("Could not load kernel '%s'", kernel_filename); 349 exit(1); 350 } 351 352 env->pc = entry; 353 } 354 355 static void mcf5208evb_machine_init(MachineClass *mc) 356 { 357 mc->desc = "MCF5208EVB"; 358 mc->init = mcf5208evb_init; 359 mc->is_default = true; 360 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m5208"); 361 mc->default_ram_id = "mcf5208.ram"; 362 } 363 364 DEFINE_MACHINE("mcf5208evb", mcf5208evb_machine_init) 365