1 /* 2 * Motorola ColdFire MCF5208 SoC emulation. 3 * 4 * Copyright (c) 2007 CodeSourcery. 5 * 6 * This code is licensed under the GPL 7 */ 8 #include "qemu/osdep.h" 9 #include "qemu/units.h" 10 #include "qemu/error-report.h" 11 #include "qapi/error.h" 12 #include "qemu-common.h" 13 #include "cpu.h" 14 #include "hw/hw.h" 15 #include "hw/m68k/mcf.h" 16 #include "hw/m68k/mcf_fec.h" 17 #include "qemu/timer.h" 18 #include "hw/ptimer.h" 19 #include "sysemu/sysemu.h" 20 #include "sysemu/qtest.h" 21 #include "net/net.h" 22 #include "hw/boards.h" 23 #include "hw/loader.h" 24 #include "hw/sysbus.h" 25 #include "elf.h" 26 #include "exec/address-spaces.h" 27 28 #define SYS_FREQ 166666666 29 30 #define PCSR_EN 0x0001 31 #define PCSR_RLD 0x0002 32 #define PCSR_PIF 0x0004 33 #define PCSR_PIE 0x0008 34 #define PCSR_OVW 0x0010 35 #define PCSR_DBG 0x0020 36 #define PCSR_DOZE 0x0040 37 #define PCSR_PRE_SHIFT 8 38 #define PCSR_PRE_MASK 0x0f00 39 40 typedef struct { 41 MemoryRegion iomem; 42 qemu_irq irq; 43 ptimer_state *timer; 44 uint16_t pcsr; 45 uint16_t pmr; 46 uint16_t pcntr; 47 } m5208_timer_state; 48 49 static void m5208_timer_update(m5208_timer_state *s) 50 { 51 if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF)) 52 qemu_irq_raise(s->irq); 53 else 54 qemu_irq_lower(s->irq); 55 } 56 57 static void m5208_timer_write(void *opaque, hwaddr offset, 58 uint64_t value, unsigned size) 59 { 60 m5208_timer_state *s = (m5208_timer_state *)opaque; 61 int prescale; 62 int limit; 63 switch (offset) { 64 case 0: 65 /* The PIF bit is set-to-clear. */ 66 if (value & PCSR_PIF) { 67 s->pcsr &= ~PCSR_PIF; 68 value &= ~PCSR_PIF; 69 } 70 /* Avoid frobbing the timer if we're just twiddling IRQ bits. */ 71 if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) { 72 s->pcsr = value; 73 m5208_timer_update(s); 74 return; 75 } 76 77 if (s->pcsr & PCSR_EN) 78 ptimer_stop(s->timer); 79 80 s->pcsr = value; 81 82 prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT); 83 ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale); 84 if (s->pcsr & PCSR_RLD) 85 limit = s->pmr; 86 else 87 limit = 0xffff; 88 ptimer_set_limit(s->timer, limit, 0); 89 90 if (s->pcsr & PCSR_EN) 91 ptimer_run(s->timer, 0); 92 break; 93 case 2: 94 s->pmr = value; 95 s->pcsr &= ~PCSR_PIF; 96 if ((s->pcsr & PCSR_RLD) == 0) { 97 if (s->pcsr & PCSR_OVW) 98 ptimer_set_count(s->timer, value); 99 } else { 100 ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW); 101 } 102 break; 103 case 4: 104 break; 105 default: 106 hw_error("m5208_timer_write: Bad offset 0x%x\n", (int)offset); 107 break; 108 } 109 m5208_timer_update(s); 110 } 111 112 static void m5208_timer_trigger(void *opaque) 113 { 114 m5208_timer_state *s = (m5208_timer_state *)opaque; 115 s->pcsr |= PCSR_PIF; 116 m5208_timer_update(s); 117 } 118 119 static uint64_t m5208_timer_read(void *opaque, hwaddr addr, 120 unsigned size) 121 { 122 m5208_timer_state *s = (m5208_timer_state *)opaque; 123 switch (addr) { 124 case 0: 125 return s->pcsr; 126 case 2: 127 return s->pmr; 128 case 4: 129 return ptimer_get_count(s->timer); 130 default: 131 hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr); 132 return 0; 133 } 134 } 135 136 static const MemoryRegionOps m5208_timer_ops = { 137 .read = m5208_timer_read, 138 .write = m5208_timer_write, 139 .endianness = DEVICE_NATIVE_ENDIAN, 140 }; 141 142 static uint64_t m5208_sys_read(void *opaque, hwaddr addr, 143 unsigned size) 144 { 145 switch (addr) { 146 case 0x110: /* SDCS0 */ 147 { 148 int n; 149 for (n = 0; n < 32; n++) { 150 if (ram_size < (2u << n)) 151 break; 152 } 153 return (n - 1) | 0x40000000; 154 } 155 case 0x114: /* SDCS1 */ 156 return 0; 157 158 default: 159 hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr); 160 return 0; 161 } 162 } 163 164 static void m5208_sys_write(void *opaque, hwaddr addr, 165 uint64_t value, unsigned size) 166 { 167 hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr); 168 } 169 170 static const MemoryRegionOps m5208_sys_ops = { 171 .read = m5208_sys_read, 172 .write = m5208_sys_write, 173 .endianness = DEVICE_NATIVE_ENDIAN, 174 }; 175 176 static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic) 177 { 178 MemoryRegion *iomem = g_new(MemoryRegion, 1); 179 m5208_timer_state *s; 180 QEMUBH *bh; 181 int i; 182 183 /* SDRAMC. */ 184 memory_region_init_io(iomem, NULL, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000); 185 memory_region_add_subregion(address_space, 0xfc0a8000, iomem); 186 /* Timers. */ 187 for (i = 0; i < 2; i++) { 188 s = g_new0(m5208_timer_state, 1); 189 bh = qemu_bh_new(m5208_timer_trigger, s); 190 s->timer = ptimer_init(bh, PTIMER_POLICY_DEFAULT); 191 memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s, 192 "m5208-timer", 0x00004000); 193 memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i, 194 &s->iomem); 195 s->irq = pic[4 + i]; 196 } 197 } 198 199 static void mcf_fec_init(MemoryRegion *sysmem, NICInfo *nd, hwaddr base, 200 qemu_irq *irqs) 201 { 202 DeviceState *dev; 203 SysBusDevice *s; 204 int i; 205 206 qemu_check_nic_model(nd, TYPE_MCF_FEC_NET); 207 dev = qdev_create(NULL, TYPE_MCF_FEC_NET); 208 qdev_set_nic_properties(dev, nd); 209 qdev_init_nofail(dev); 210 211 s = SYS_BUS_DEVICE(dev); 212 for (i = 0; i < FEC_NUM_IRQ; i++) { 213 sysbus_connect_irq(s, i, irqs[i]); 214 } 215 216 memory_region_add_subregion(sysmem, base, sysbus_mmio_get_region(s, 0)); 217 } 218 219 static void mcf5208evb_init(MachineState *machine) 220 { 221 ram_addr_t ram_size = machine->ram_size; 222 const char *kernel_filename = machine->kernel_filename; 223 M68kCPU *cpu; 224 CPUM68KState *env; 225 int kernel_size; 226 uint64_t elf_entry; 227 hwaddr entry; 228 qemu_irq *pic; 229 MemoryRegion *address_space_mem = get_system_memory(); 230 MemoryRegion *ram = g_new(MemoryRegion, 1); 231 MemoryRegion *sram = g_new(MemoryRegion, 1); 232 233 cpu = M68K_CPU(cpu_create(machine->cpu_type)); 234 env = &cpu->env; 235 236 /* Initialize CPU registers. */ 237 env->vbr = 0; 238 /* TODO: Configure BARs. */ 239 240 /* DRAM at 0x40000000 */ 241 memory_region_allocate_system_memory(ram, NULL, "mcf5208.ram", ram_size); 242 memory_region_add_subregion(address_space_mem, 0x40000000, ram); 243 244 /* Internal SRAM. */ 245 memory_region_init_ram(sram, NULL, "mcf5208.sram", 16 * KiB, &error_fatal); 246 memory_region_add_subregion(address_space_mem, 0x80000000, sram); 247 248 /* Internal peripherals. */ 249 pic = mcf_intc_init(address_space_mem, 0xfc048000, cpu); 250 251 mcf_uart_mm_init(0xfc060000, pic[26], serial_hd(0)); 252 mcf_uart_mm_init(0xfc064000, pic[27], serial_hd(1)); 253 mcf_uart_mm_init(0xfc068000, pic[28], serial_hd(2)); 254 255 mcf5208_sys_init(address_space_mem, pic); 256 257 if (nb_nics > 1) { 258 error_report("Too many NICs"); 259 exit(1); 260 } 261 if (nd_table[0].used) { 262 mcf_fec_init(address_space_mem, &nd_table[0], 263 0xfc030000, pic + 36); 264 } 265 266 /* 0xfc000000 SCM. */ 267 /* 0xfc004000 XBS. */ 268 /* 0xfc008000 FlexBus CS. */ 269 /* 0xfc030000 FEC. */ 270 /* 0xfc040000 SCM + Power management. */ 271 /* 0xfc044000 eDMA. */ 272 /* 0xfc048000 INTC. */ 273 /* 0xfc058000 I2C. */ 274 /* 0xfc05c000 QSPI. */ 275 /* 0xfc060000 UART0. */ 276 /* 0xfc064000 UART0. */ 277 /* 0xfc068000 UART0. */ 278 /* 0xfc070000 DMA timers. */ 279 /* 0xfc080000 PIT0. */ 280 /* 0xfc084000 PIT1. */ 281 /* 0xfc088000 EPORT. */ 282 /* 0xfc08c000 Watchdog. */ 283 /* 0xfc090000 clock module. */ 284 /* 0xfc0a0000 CCM + reset. */ 285 /* 0xfc0a4000 GPIO. */ 286 /* 0xfc0a8000 SDRAM controller. */ 287 288 /* Load kernel. */ 289 if (!kernel_filename) { 290 if (qtest_enabled()) { 291 return; 292 } 293 error_report("Kernel image must be specified"); 294 exit(1); 295 } 296 297 kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry, 298 NULL, NULL, 1, EM_68K, 0, 0); 299 entry = elf_entry; 300 if (kernel_size < 0) { 301 kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL, 302 NULL, NULL); 303 } 304 if (kernel_size < 0) { 305 kernel_size = load_image_targphys(kernel_filename, 0x40000000, 306 ram_size); 307 entry = 0x40000000; 308 } 309 if (kernel_size < 0) { 310 error_report("Could not load kernel '%s'", kernel_filename); 311 exit(1); 312 } 313 314 env->pc = entry; 315 } 316 317 static void mcf5208evb_machine_init(MachineClass *mc) 318 { 319 mc->desc = "MCF5208EVB"; 320 mc->init = mcf5208evb_init; 321 mc->is_default = 1; 322 mc->default_cpu_type = M68K_CPU_TYPE_NAME("m5208"); 323 } 324 325 DEFINE_MACHINE("mcf5208evb", mcf5208evb_machine_init) 326