1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU loongson 3a5000 develop board emulation 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 #include "qemu/osdep.h" 8 #include "qemu/units.h" 9 #include "qemu/datadir.h" 10 #include "qapi/error.h" 11 #include "hw/boards.h" 12 #include "hw/char/serial.h" 13 #include "sysemu/sysemu.h" 14 #include "sysemu/qtest.h" 15 #include "sysemu/runstate.h" 16 #include "sysemu/reset.h" 17 #include "sysemu/rtc.h" 18 #include "hw/loongarch/virt.h" 19 #include "exec/address-spaces.h" 20 #include "hw/irq.h" 21 #include "net/net.h" 22 #include "hw/loader.h" 23 #include "elf.h" 24 #include "hw/intc/loongarch_ipi.h" 25 #include "hw/intc/loongarch_extioi.h" 26 #include "hw/intc/loongarch_pch_pic.h" 27 #include "hw/intc/loongarch_pch_msi.h" 28 #include "hw/pci-host/ls7a.h" 29 #include "hw/pci-host/gpex.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/loongarch/fw_cfg.h" 32 #include "target/loongarch/cpu.h" 33 #include "hw/firmware/smbios.h" 34 #include "hw/acpi/aml-build.h" 35 #include "qapi/qapi-visit-common.h" 36 #include "hw/acpi/generic_event_device.h" 37 #include "hw/mem/nvdimm.h" 38 #include "sysemu/device_tree.h" 39 #include <libfdt.h> 40 #include "hw/core/sysbus-fdt.h" 41 #include "hw/platform-bus.h" 42 #include "hw/display/ramfb.h" 43 #include "hw/mem/pc-dimm.h" 44 #include "sysemu/tpm.h" 45 #include "sysemu/block-backend.h" 46 #include "hw/block/flash.h" 47 #include "qemu/error-report.h" 48 49 50 struct loaderparams { 51 uint64_t ram_size; 52 const char *kernel_filename; 53 const char *kernel_cmdline; 54 const char *initrd_filename; 55 }; 56 57 static void virt_flash_create(LoongArchMachineState *lams) 58 { 59 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 60 61 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 62 qdev_prop_set_uint8(dev, "width", 4); 63 qdev_prop_set_uint8(dev, "device-width", 2); 64 qdev_prop_set_bit(dev, "big-endian", false); 65 qdev_prop_set_uint16(dev, "id0", 0x89); 66 qdev_prop_set_uint16(dev, "id1", 0x18); 67 qdev_prop_set_uint16(dev, "id2", 0x00); 68 qdev_prop_set_uint16(dev, "id3", 0x00); 69 qdev_prop_set_string(dev, "name", "virt.flash"); 70 object_property_add_child(OBJECT(lams), "virt.flash", OBJECT(dev)); 71 object_property_add_alias(OBJECT(lams), "pflash", 72 OBJECT(dev), "drive"); 73 74 lams->flash = PFLASH_CFI01(dev); 75 } 76 77 static void virt_flash_map(LoongArchMachineState *lams, 78 MemoryRegion *sysmem) 79 { 80 PFlashCFI01 *flash = lams->flash; 81 DeviceState *dev = DEVICE(flash); 82 hwaddr base = VIRT_FLASH_BASE; 83 hwaddr size = VIRT_FLASH_SIZE; 84 85 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 86 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 87 88 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 89 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 90 memory_region_add_subregion(sysmem, base, 91 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 92 93 } 94 95 static void fdt_add_flash_node(LoongArchMachineState *lams) 96 { 97 MachineState *ms = MACHINE(lams); 98 char *nodename; 99 100 hwaddr flash_base = VIRT_FLASH_BASE; 101 hwaddr flash_size = VIRT_FLASH_SIZE; 102 103 nodename = g_strdup_printf("/flash@%" PRIx64, flash_base); 104 qemu_fdt_add_subnode(ms->fdt, nodename); 105 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 106 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 107 2, flash_base, 2, flash_size); 108 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 109 g_free(nodename); 110 } 111 112 static void fdt_add_rtc_node(LoongArchMachineState *lams) 113 { 114 char *nodename; 115 hwaddr base = VIRT_RTC_REG_BASE; 116 hwaddr size = VIRT_RTC_LEN; 117 MachineState *ms = MACHINE(lams); 118 119 nodename = g_strdup_printf("/rtc@%" PRIx64, base); 120 qemu_fdt_add_subnode(ms->fdt, nodename); 121 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc"); 122 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 123 g_free(nodename); 124 } 125 126 static void fdt_add_uart_node(LoongArchMachineState *lams) 127 { 128 char *nodename; 129 hwaddr base = VIRT_UART_BASE; 130 hwaddr size = VIRT_UART_SIZE; 131 MachineState *ms = MACHINE(lams); 132 133 nodename = g_strdup_printf("/serial@%" PRIx64, base); 134 qemu_fdt_add_subnode(ms->fdt, nodename); 135 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a"); 136 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size); 137 qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000); 138 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 139 g_free(nodename); 140 } 141 142 static void create_fdt(LoongArchMachineState *lams) 143 { 144 MachineState *ms = MACHINE(lams); 145 146 ms->fdt = create_device_tree(&lams->fdt_size); 147 if (!ms->fdt) { 148 error_report("create_device_tree() failed"); 149 exit(1); 150 } 151 152 /* Header */ 153 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", 154 "linux,dummy-loongson3"); 155 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 156 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 157 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 158 } 159 160 static void fdt_add_cpu_nodes(const LoongArchMachineState *lams) 161 { 162 int num; 163 const MachineState *ms = MACHINE(lams); 164 int smp_cpus = ms->smp.cpus; 165 166 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 167 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 168 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 169 170 /* cpu nodes */ 171 for (num = smp_cpus - 1; num >= 0; num--) { 172 char *nodename = g_strdup_printf("/cpus/cpu@%d", num); 173 LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num)); 174 CPUState *cs = CPU(cpu); 175 176 qemu_fdt_add_subnode(ms->fdt, nodename); 177 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 178 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 179 cpu->dtb_compatible); 180 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 181 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 182 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 183 } 184 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); 185 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 186 qemu_fdt_alloc_phandle(ms->fdt)); 187 g_free(nodename); 188 } 189 190 /*cpu map */ 191 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 192 193 for (num = smp_cpus - 1; num >= 0; num--) { 194 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num); 195 char *map_path; 196 197 if (ms->smp.threads > 1) { 198 map_path = g_strdup_printf( 199 "/cpus/cpu-map/socket%d/core%d/thread%d", 200 num / (ms->smp.cores * ms->smp.threads), 201 (num / ms->smp.threads) % ms->smp.cores, 202 num % ms->smp.threads); 203 } else { 204 map_path = g_strdup_printf( 205 "/cpus/cpu-map/socket%d/core%d", 206 num / ms->smp.cores, 207 num % ms->smp.cores); 208 } 209 qemu_fdt_add_path(ms->fdt, map_path); 210 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 211 212 g_free(map_path); 213 g_free(cpu_path); 214 } 215 } 216 217 static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams) 218 { 219 char *nodename; 220 hwaddr base = VIRT_FWCFG_BASE; 221 const MachineState *ms = MACHINE(lams); 222 223 nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base); 224 qemu_fdt_add_subnode(ms->fdt, nodename); 225 qemu_fdt_setprop_string(ms->fdt, nodename, 226 "compatible", "qemu,fw-cfg-mmio"); 227 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 228 2, base, 2, 0x18); 229 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 230 g_free(nodename); 231 } 232 233 static void fdt_add_pcie_node(const LoongArchMachineState *lams) 234 { 235 char *nodename; 236 hwaddr base_mmio = VIRT_PCI_MEM_BASE; 237 hwaddr size_mmio = VIRT_PCI_MEM_SIZE; 238 hwaddr base_pio = VIRT_PCI_IO_BASE; 239 hwaddr size_pio = VIRT_PCI_IO_SIZE; 240 hwaddr base_pcie = VIRT_PCI_CFG_BASE; 241 hwaddr size_pcie = VIRT_PCI_CFG_SIZE; 242 hwaddr base = base_pcie; 243 244 const MachineState *ms = MACHINE(lams); 245 246 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 247 qemu_fdt_add_subnode(ms->fdt, nodename); 248 qemu_fdt_setprop_string(ms->fdt, nodename, 249 "compatible", "pci-host-ecam-generic"); 250 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 251 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 252 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 253 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 254 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 255 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); 256 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 257 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 258 2, base_pcie, 2, size_pcie); 259 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 260 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, 261 2, base_pio, 2, size_pio, 262 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 263 2, base_mmio, 2, size_mmio); 264 g_free(nodename); 265 } 266 267 static void fdt_add_irqchip_node(LoongArchMachineState *lams) 268 { 269 MachineState *ms = MACHINE(lams); 270 char *nodename; 271 uint32_t irqchip_phandle; 272 273 irqchip_phandle = qemu_fdt_alloc_phandle(ms->fdt); 274 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", irqchip_phandle); 275 276 nodename = g_strdup_printf("/intc@%lx", VIRT_IOAPIC_REG_BASE); 277 qemu_fdt_add_subnode(ms->fdt, nodename); 278 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 279 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 280 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 281 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 282 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 283 284 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 285 "loongarch,ls7a"); 286 287 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 288 2, VIRT_IOAPIC_REG_BASE, 289 2, PCH_PIC_ROUTE_ENTRY_OFFSET); 290 291 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", irqchip_phandle); 292 g_free(nodename); 293 } 294 295 static void fdt_add_memory_node(MachineState *ms, 296 uint64_t base, uint64_t size, int node_id) 297 { 298 char *nodename = g_strdup_printf("/memory@%" PRIx64, base); 299 300 qemu_fdt_add_subnode(ms->fdt, nodename); 301 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 302 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 303 304 if (ms->numa_state && ms->numa_state->num_nodes) { 305 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id); 306 } 307 308 g_free(nodename); 309 } 310 311 static void virt_build_smbios(LoongArchMachineState *lams) 312 { 313 MachineState *ms = MACHINE(lams); 314 MachineClass *mc = MACHINE_GET_CLASS(lams); 315 uint8_t *smbios_tables, *smbios_anchor; 316 size_t smbios_tables_len, smbios_anchor_len; 317 const char *product = "QEMU Virtual Machine"; 318 319 if (!lams->fw_cfg) { 320 return; 321 } 322 323 smbios_set_defaults("QEMU", product, mc->name, false, 324 true, SMBIOS_ENTRY_POINT_TYPE_64); 325 326 smbios_get_tables(ms, NULL, 0, &smbios_tables, &smbios_tables_len, 327 &smbios_anchor, &smbios_anchor_len, &error_fatal); 328 329 if (smbios_anchor) { 330 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables", 331 smbios_tables, smbios_tables_len); 332 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor", 333 smbios_anchor, smbios_anchor_len); 334 } 335 } 336 337 static void virt_machine_done(Notifier *notifier, void *data) 338 { 339 LoongArchMachineState *lams = container_of(notifier, 340 LoongArchMachineState, machine_done); 341 virt_build_smbios(lams); 342 loongarch_acpi_setup(lams); 343 } 344 345 static void virt_powerdown_req(Notifier *notifier, void *opaque) 346 { 347 LoongArchMachineState *s = container_of(notifier, 348 LoongArchMachineState, powerdown_notifier); 349 350 acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS); 351 } 352 353 struct memmap_entry { 354 uint64_t address; 355 uint64_t length; 356 uint32_t type; 357 uint32_t reserved; 358 }; 359 360 static struct memmap_entry *memmap_table; 361 static unsigned memmap_entries; 362 363 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) 364 { 365 /* Ensure there are no duplicate entries. */ 366 for (unsigned i = 0; i < memmap_entries; i++) { 367 assert(memmap_table[i].address != address); 368 } 369 370 memmap_table = g_renew(struct memmap_entry, memmap_table, 371 memmap_entries + 1); 372 memmap_table[memmap_entries].address = cpu_to_le64(address); 373 memmap_table[memmap_entries].length = cpu_to_le64(length); 374 memmap_table[memmap_entries].type = cpu_to_le32(type); 375 memmap_table[memmap_entries].reserved = 0; 376 memmap_entries++; 377 } 378 379 static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr) 380 { 381 return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS); 382 } 383 384 static int64_t load_kernel_info(const struct loaderparams *loaderparams) 385 { 386 uint64_t kernel_entry, kernel_low, kernel_high; 387 ssize_t kernel_size; 388 389 kernel_size = load_elf(loaderparams->kernel_filename, NULL, 390 cpu_loongarch_virt_to_phys, NULL, 391 &kernel_entry, &kernel_low, 392 &kernel_high, NULL, 0, 393 EM_LOONGARCH, 1, 0); 394 395 if (kernel_size < 0) { 396 error_report("could not load kernel '%s': %s", 397 loaderparams->kernel_filename, 398 load_elf_strerror(kernel_size)); 399 exit(1); 400 } 401 return kernel_entry; 402 } 403 404 static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams) 405 { 406 DeviceState *dev; 407 MachineState *ms = MACHINE(lams); 408 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 409 410 if (ms->ram_slots) { 411 event |= ACPI_GED_MEM_HOTPLUG_EVT; 412 } 413 dev = qdev_new(TYPE_ACPI_GED); 414 qdev_prop_set_uint32(dev, "ged-event", event); 415 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 416 417 /* ged event */ 418 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); 419 /* memory hotplug */ 420 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); 421 /* ged regs used for reset and power down */ 422 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); 423 424 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 425 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE)); 426 return dev; 427 } 428 429 static DeviceState *create_platform_bus(DeviceState *pch_pic) 430 { 431 DeviceState *dev; 432 SysBusDevice *sysbus; 433 int i, irq; 434 MemoryRegion *sysmem = get_system_memory(); 435 436 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 437 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 438 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 439 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); 440 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 441 442 sysbus = SYS_BUS_DEVICE(dev); 443 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 444 irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i; 445 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); 446 } 447 448 memory_region_add_subregion(sysmem, 449 VIRT_PLATFORM_BUS_BASEADDRESS, 450 sysbus_mmio_get_region(sysbus, 0)); 451 return dev; 452 } 453 454 static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *lams) 455 { 456 MachineClass *mc = MACHINE_GET_CLASS(lams); 457 DeviceState *gpex_dev; 458 SysBusDevice *d; 459 PCIBus *pci_bus; 460 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; 461 MemoryRegion *mmio_alias, *mmio_reg; 462 int i; 463 464 gpex_dev = qdev_new(TYPE_GPEX_HOST); 465 d = SYS_BUS_DEVICE(gpex_dev); 466 sysbus_realize_and_unref(d, &error_fatal); 467 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; 468 lams->pci_bus = pci_bus; 469 470 /* Map only part size_ecam bytes of ECAM space */ 471 ecam_alias = g_new0(MemoryRegion, 1); 472 ecam_reg = sysbus_mmio_get_region(d, 0); 473 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", 474 ecam_reg, 0, VIRT_PCI_CFG_SIZE); 475 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, 476 ecam_alias); 477 478 /* Map PCI mem space */ 479 mmio_alias = g_new0(MemoryRegion, 1); 480 mmio_reg = sysbus_mmio_get_region(d, 1); 481 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", 482 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); 483 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, 484 mmio_alias); 485 486 /* Map PCI IO port space. */ 487 pio_alias = g_new0(MemoryRegion, 1); 488 pio_reg = sysbus_mmio_get_region(d, 2); 489 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, 490 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); 491 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, 492 pio_alias); 493 494 for (i = 0; i < GPEX_NUM_IRQS; i++) { 495 sysbus_connect_irq(d, i, 496 qdev_get_gpio_in(pch_pic, 16 + i)); 497 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); 498 } 499 500 serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, 501 qdev_get_gpio_in(pch_pic, 502 VIRT_UART_IRQ - VIRT_GSI_BASE), 503 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 504 fdt_add_uart_node(lams); 505 506 /* Network init */ 507 for (i = 0; i < nb_nics; i++) { 508 pci_nic_init_nofail(&nd_table[i], pci_bus, mc->default_nic, NULL); 509 } 510 511 /* 512 * There are some invalid guest memory access. 513 * Create some unimplemented devices to emulate this. 514 */ 515 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); 516 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, 517 qdev_get_gpio_in(pch_pic, 518 VIRT_RTC_IRQ - VIRT_GSI_BASE)); 519 fdt_add_rtc_node(lams); 520 521 /* acpi ged */ 522 lams->acpi_ged = create_acpi_ged(pch_pic, lams); 523 /* platform bus */ 524 lams->platform_bus_dev = create_platform_bus(pch_pic); 525 } 526 527 static void loongarch_irq_init(LoongArchMachineState *lams) 528 { 529 MachineState *ms = MACHINE(lams); 530 DeviceState *pch_pic, *pch_msi, *cpudev; 531 DeviceState *ipi, *extioi; 532 SysBusDevice *d; 533 LoongArchCPU *lacpu; 534 CPULoongArchState *env; 535 CPUState *cpu_state; 536 int cpu, pin, i, start, num; 537 538 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); 539 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); 540 541 /* 542 * The connection of interrupts: 543 * +-----+ +---------+ +-------+ 544 * | IPI |--> | CPUINTC | <-- | Timer | 545 * +-----+ +---------+ +-------+ 546 * ^ 547 * | 548 * +---------+ 549 * | EIOINTC | 550 * +---------+ 551 * ^ ^ 552 * | | 553 * +---------+ +---------+ 554 * | PCH-PIC | | PCH-MSI | 555 * +---------+ +---------+ 556 * ^ ^ ^ 557 * | | | 558 * +--------+ +---------+ +---------+ 559 * | UARTs | | Devices | | Devices | 560 * +--------+ +---------+ +---------+ 561 */ 562 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 563 cpu_state = qemu_get_cpu(cpu); 564 cpudev = DEVICE(cpu_state); 565 lacpu = LOONGARCH_CPU(cpu_state); 566 env = &(lacpu->env); 567 568 ipi = qdev_new(TYPE_LOONGARCH_IPI); 569 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 570 571 /* connect ipi irq to cpu irq */ 572 qdev_connect_gpio_out(ipi, 0, qdev_get_gpio_in(cpudev, IRQ_IPI)); 573 /* IPI iocsr memory region */ 574 memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX, 575 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 576 0)); 577 memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR, 578 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 579 1)); 580 /* 581 * extioi iocsr memory region 582 * only one extioi is added on loongarch virt machine 583 * external device interrupt can only be routed to cpu 0-3 584 */ 585 if (cpu < EXTIOI_CPUS) 586 memory_region_add_subregion(&env->system_iocsr, APIC_BASE, 587 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 588 cpu)); 589 env->ipistate = ipi; 590 } 591 592 /* 593 * connect ext irq to the cpu irq 594 * cpu_pin[9:2] <= intc_pin[7:0] 595 */ 596 for (cpu = 0; cpu < MIN(ms->smp.cpus, EXTIOI_CPUS); cpu++) { 597 cpudev = DEVICE(qemu_get_cpu(cpu)); 598 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 599 qdev_connect_gpio_out(extioi, (cpu * 8 + pin), 600 qdev_get_gpio_in(cpudev, pin + 2)); 601 } 602 } 603 604 pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); 605 num = VIRT_PCH_PIC_IRQ_NUM; 606 qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); 607 d = SYS_BUS_DEVICE(pch_pic); 608 sysbus_realize_and_unref(d, &error_fatal); 609 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, 610 sysbus_mmio_get_region(d, 0)); 611 memory_region_add_subregion(get_system_memory(), 612 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, 613 sysbus_mmio_get_region(d, 1)); 614 memory_region_add_subregion(get_system_memory(), 615 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, 616 sysbus_mmio_get_region(d, 2)); 617 618 /* Connect pch_pic irqs to extioi */ 619 for (i = 0; i < num; i++) { 620 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); 621 } 622 623 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); 624 start = num; 625 num = EXTIOI_IRQS - start; 626 qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); 627 qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); 628 d = SYS_BUS_DEVICE(pch_msi); 629 sysbus_realize_and_unref(d, &error_fatal); 630 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); 631 for (i = 0; i < num; i++) { 632 /* Connect pch_msi irqs to extioi */ 633 qdev_connect_gpio_out(DEVICE(d), i, 634 qdev_get_gpio_in(extioi, i + start)); 635 } 636 637 loongarch_devices_init(pch_pic, lams); 638 } 639 640 static void loongarch_firmware_init(LoongArchMachineState *lams) 641 { 642 char *filename = MACHINE(lams)->firmware; 643 char *bios_name = NULL; 644 int bios_size; 645 646 lams->bios_loaded = false; 647 648 virt_flash_map(lams, get_system_memory()); 649 650 if (filename) { 651 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); 652 if (!bios_name) { 653 error_report("Could not find ROM image '%s'", filename); 654 exit(1); 655 } 656 657 bios_size = load_image_targphys(bios_name, VIRT_BIOS_BASE, VIRT_BIOS_SIZE); 658 if (bios_size < 0) { 659 error_report("Could not load ROM image '%s'", bios_name); 660 exit(1); 661 } 662 663 g_free(bios_name); 664 665 memory_region_init_ram(&lams->bios, NULL, "loongarch.bios", 666 VIRT_BIOS_SIZE, &error_fatal); 667 memory_region_set_readonly(&lams->bios, true); 668 memory_region_add_subregion(get_system_memory(), VIRT_BIOS_BASE, &lams->bios); 669 lams->bios_loaded = true; 670 } 671 672 } 673 674 static void reset_load_elf(void *opaque) 675 { 676 LoongArchCPU *cpu = opaque; 677 CPULoongArchState *env = &cpu->env; 678 679 cpu_reset(CPU(cpu)); 680 if (env->load_elf) { 681 cpu_set_pc(CPU(cpu), env->elf_address); 682 } 683 } 684 685 static void fw_cfg_add_kernel_info(const struct loaderparams *loaderparams, 686 FWCfgState *fw_cfg) 687 { 688 /* 689 * Expose the kernel, the command line, and the initrd in fw_cfg. 690 * We don't process them here at all, it's all left to the 691 * firmware. 692 */ 693 load_image_to_fw_cfg(fw_cfg, 694 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 695 loaderparams->kernel_filename, 696 false); 697 698 if (loaderparams->initrd_filename) { 699 load_image_to_fw_cfg(fw_cfg, 700 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 701 loaderparams->initrd_filename, false); 702 } 703 704 if (loaderparams->kernel_cmdline) { 705 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 706 strlen(loaderparams->kernel_cmdline) + 1); 707 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 708 loaderparams->kernel_cmdline); 709 } 710 } 711 712 static void loongarch_firmware_boot(LoongArchMachineState *lams, 713 const struct loaderparams *loaderparams) 714 { 715 fw_cfg_add_kernel_info(loaderparams, lams->fw_cfg); 716 } 717 718 static void loongarch_direct_kernel_boot(LoongArchMachineState *lams, 719 const struct loaderparams *loaderparams) 720 { 721 MachineState *machine = MACHINE(lams); 722 int64_t kernel_addr = 0; 723 LoongArchCPU *lacpu; 724 int i; 725 726 kernel_addr = load_kernel_info(loaderparams); 727 if (!machine->firmware) { 728 for (i = 0; i < machine->smp.cpus; i++) { 729 lacpu = LOONGARCH_CPU(qemu_get_cpu(i)); 730 lacpu->env.load_elf = true; 731 lacpu->env.elf_address = kernel_addr; 732 } 733 } 734 } 735 736 static void loongarch_init(MachineState *machine) 737 { 738 LoongArchCPU *lacpu; 739 const char *cpu_model = machine->cpu_type; 740 ram_addr_t offset = 0; 741 ram_addr_t ram_size = machine->ram_size; 742 uint64_t highram_size = 0, phyAddr = 0; 743 MemoryRegion *address_space_mem = get_system_memory(); 744 LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); 745 int nb_numa_nodes = machine->numa_state->num_nodes; 746 NodeInfo *numa_info = machine->numa_state->nodes; 747 int i; 748 hwaddr fdt_base; 749 const CPUArchIdList *possible_cpus; 750 MachineClass *mc = MACHINE_GET_CLASS(machine); 751 CPUState *cpu; 752 char *ramName = NULL; 753 struct loaderparams loaderparams = { }; 754 755 if (!cpu_model) { 756 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); 757 } 758 759 if (ram_size < 1 * GiB) { 760 error_report("ram_size must be greater than 1G."); 761 exit(1); 762 } 763 create_fdt(lams); 764 /* Init CPUs */ 765 766 possible_cpus = mc->possible_cpu_arch_ids(machine); 767 for (i = 0; i < possible_cpus->len; i++) { 768 cpu = cpu_create(machine->cpu_type); 769 cpu->cpu_index = i; 770 machine->possible_cpus->cpus[i].cpu = OBJECT(cpu); 771 lacpu = LOONGARCH_CPU(cpu); 772 lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id; 773 } 774 fdt_add_cpu_nodes(lams); 775 776 /* Node0 memory */ 777 memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1); 778 fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0); 779 memory_region_init_alias(&lams->lowmem, NULL, "loongarch.node0.lowram", 780 machine->ram, offset, VIRT_LOWMEM_SIZE); 781 memory_region_add_subregion(address_space_mem, phyAddr, &lams->lowmem); 782 783 offset += VIRT_LOWMEM_SIZE; 784 if (nb_numa_nodes > 0) { 785 assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE); 786 highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE; 787 } else { 788 highram_size = ram_size - VIRT_LOWMEM_SIZE; 789 } 790 phyAddr = VIRT_HIGHMEM_BASE; 791 memmap_add_entry(phyAddr, highram_size, 1); 792 fdt_add_memory_node(machine, phyAddr, highram_size, 0); 793 memory_region_init_alias(&lams->highmem, NULL, "loongarch.node0.highram", 794 machine->ram, offset, highram_size); 795 memory_region_add_subregion(address_space_mem, phyAddr, &lams->highmem); 796 797 /* Node1 - Nodemax memory */ 798 offset += highram_size; 799 phyAddr += highram_size; 800 801 for (i = 1; i < nb_numa_nodes; i++) { 802 MemoryRegion *nodemem = g_new(MemoryRegion, 1); 803 ramName = g_strdup_printf("loongarch.node%d.ram", i); 804 memory_region_init_alias(nodemem, NULL, ramName, machine->ram, 805 offset, numa_info[i].node_mem); 806 memory_region_add_subregion(address_space_mem, phyAddr, nodemem); 807 memmap_add_entry(phyAddr, numa_info[i].node_mem, 1); 808 fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i); 809 offset += numa_info[i].node_mem; 810 phyAddr += numa_info[i].node_mem; 811 } 812 813 /* initialize device memory address space */ 814 if (machine->ram_size < machine->maxram_size) { 815 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 816 hwaddr device_mem_base; 817 818 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 819 error_report("unsupported amount of memory slots: %"PRIu64, 820 machine->ram_slots); 821 exit(EXIT_FAILURE); 822 } 823 824 if (QEMU_ALIGN_UP(machine->maxram_size, 825 TARGET_PAGE_SIZE) != machine->maxram_size) { 826 error_report("maximum memory size must by aligned to multiple of " 827 "%d bytes", TARGET_PAGE_SIZE); 828 exit(EXIT_FAILURE); 829 } 830 /* device memory base is the top of high memory address. */ 831 device_mem_base = ROUND_UP(VIRT_HIGHMEM_BASE + highram_size, 1 * GiB); 832 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 833 } 834 835 /* load the BIOS image. */ 836 loongarch_firmware_init(lams); 837 838 /* fw_cfg init */ 839 lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine); 840 rom_set_fw(lams->fw_cfg); 841 if (lams->fw_cfg != NULL) { 842 fw_cfg_add_file(lams->fw_cfg, "etc/memmap", 843 memmap_table, 844 sizeof(struct memmap_entry) * (memmap_entries)); 845 } 846 fdt_add_fw_cfg_node(lams); 847 loaderparams.ram_size = ram_size; 848 loaderparams.kernel_filename = machine->kernel_filename; 849 loaderparams.kernel_cmdline = machine->kernel_cmdline; 850 loaderparams.initrd_filename = machine->initrd_filename; 851 /* load the kernel. */ 852 if (loaderparams.kernel_filename) { 853 if (lams->bios_loaded) { 854 loongarch_firmware_boot(lams, &loaderparams); 855 } else { 856 loongarch_direct_kernel_boot(lams, &loaderparams); 857 } 858 } 859 fdt_add_flash_node(lams); 860 /* register reset function */ 861 for (i = 0; i < machine->smp.cpus; i++) { 862 lacpu = LOONGARCH_CPU(qemu_get_cpu(i)); 863 qemu_register_reset(reset_load_elf, lacpu); 864 } 865 /* Initialize the IO interrupt subsystem */ 866 loongarch_irq_init(lams); 867 fdt_add_irqchip_node(lams); 868 platform_bus_add_all_fdt_nodes(machine->fdt, "/intc", 869 VIRT_PLATFORM_BUS_BASEADDRESS, 870 VIRT_PLATFORM_BUS_SIZE, 871 VIRT_PLATFORM_BUS_IRQ); 872 lams->machine_done.notify = virt_machine_done; 873 qemu_add_machine_init_done_notifier(&lams->machine_done); 874 /* connect powerdown request */ 875 lams->powerdown_notifier.notify = virt_powerdown_req; 876 qemu_register_powerdown_notifier(&lams->powerdown_notifier); 877 878 fdt_add_pcie_node(lams); 879 /* 880 * Since lowmem region starts from 0 and Linux kernel legacy start address 881 * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer 882 * access. FDT size limit with 1 MiB. 883 * Put the FDT into the memory map as a ROM image: this will ensure 884 * the FDT is copied again upon reset, even if addr points into RAM. 885 */ 886 fdt_base = 1 * MiB; 887 qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size); 888 rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, fdt_base); 889 } 890 891 bool loongarch_is_acpi_enabled(LoongArchMachineState *lams) 892 { 893 if (lams->acpi == ON_OFF_AUTO_OFF) { 894 return false; 895 } 896 return true; 897 } 898 899 static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name, 900 void *opaque, Error **errp) 901 { 902 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 903 OnOffAuto acpi = lams->acpi; 904 905 visit_type_OnOffAuto(v, name, &acpi, errp); 906 } 907 908 static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name, 909 void *opaque, Error **errp) 910 { 911 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 912 913 visit_type_OnOffAuto(v, name, &lams->acpi, errp); 914 } 915 916 static void loongarch_machine_initfn(Object *obj) 917 { 918 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 919 920 lams->acpi = ON_OFF_AUTO_AUTO; 921 lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 922 lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 923 virt_flash_create(lams); 924 } 925 926 static bool memhp_type_supported(DeviceState *dev) 927 { 928 /* we only support pc dimm now */ 929 return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && 930 !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 931 } 932 933 static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 934 Error **errp) 935 { 936 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 937 } 938 939 static void virt_machine_device_pre_plug(HotplugHandler *hotplug_dev, 940 DeviceState *dev, Error **errp) 941 { 942 if (memhp_type_supported(dev)) { 943 virt_mem_pre_plug(hotplug_dev, dev, errp); 944 } 945 } 946 947 static void virt_mem_unplug_request(HotplugHandler *hotplug_dev, 948 DeviceState *dev, Error **errp) 949 { 950 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 951 952 /* the acpi ged is always exist */ 953 hotplug_handler_unplug_request(HOTPLUG_HANDLER(lams->acpi_ged), dev, 954 errp); 955 } 956 957 static void virt_machine_device_unplug_request(HotplugHandler *hotplug_dev, 958 DeviceState *dev, Error **errp) 959 { 960 if (memhp_type_supported(dev)) { 961 virt_mem_unplug_request(hotplug_dev, dev, errp); 962 } 963 } 964 965 static void virt_mem_unplug(HotplugHandler *hotplug_dev, 966 DeviceState *dev, Error **errp) 967 { 968 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 969 970 hotplug_handler_unplug(HOTPLUG_HANDLER(lams->acpi_ged), dev, errp); 971 pc_dimm_unplug(PC_DIMM(dev), MACHINE(lams)); 972 qdev_unrealize(dev); 973 } 974 975 static void virt_machine_device_unplug(HotplugHandler *hotplug_dev, 976 DeviceState *dev, Error **errp) 977 { 978 if (memhp_type_supported(dev)) { 979 virt_mem_unplug(hotplug_dev, dev, errp); 980 } 981 } 982 983 static void virt_mem_plug(HotplugHandler *hotplug_dev, 984 DeviceState *dev, Error **errp) 985 { 986 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 987 988 pc_dimm_plug(PC_DIMM(dev), MACHINE(lams)); 989 hotplug_handler_plug(HOTPLUG_HANDLER(lams->acpi_ged), 990 dev, &error_abort); 991 } 992 993 static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev, 994 DeviceState *dev, Error **errp) 995 { 996 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 997 MachineClass *mc = MACHINE_GET_CLASS(lams); 998 999 if (device_is_dynamic_sysbus(mc, dev)) { 1000 if (lams->platform_bus_dev) { 1001 platform_bus_link_device(PLATFORM_BUS_DEVICE(lams->platform_bus_dev), 1002 SYS_BUS_DEVICE(dev)); 1003 } 1004 } else if (memhp_type_supported(dev)) { 1005 virt_mem_plug(hotplug_dev, dev, errp); 1006 } 1007 } 1008 1009 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1010 DeviceState *dev) 1011 { 1012 MachineClass *mc = MACHINE_GET_CLASS(machine); 1013 1014 if (device_is_dynamic_sysbus(mc, dev) || 1015 memhp_type_supported(dev)) { 1016 return HOTPLUG_HANDLER(machine); 1017 } 1018 return NULL; 1019 } 1020 1021 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1022 { 1023 int n; 1024 unsigned int max_cpus = ms->smp.max_cpus; 1025 1026 if (ms->possible_cpus) { 1027 assert(ms->possible_cpus->len == max_cpus); 1028 return ms->possible_cpus; 1029 } 1030 1031 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1032 sizeof(CPUArchId) * max_cpus); 1033 ms->possible_cpus->len = max_cpus; 1034 for (n = 0; n < ms->possible_cpus->len; n++) { 1035 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1036 ms->possible_cpus->cpus[n].arch_id = n; 1037 1038 ms->possible_cpus->cpus[n].props.has_socket_id = true; 1039 ms->possible_cpus->cpus[n].props.socket_id = 1040 n / (ms->smp.cores * ms->smp.threads); 1041 ms->possible_cpus->cpus[n].props.has_core_id = true; 1042 ms->possible_cpus->cpus[n].props.core_id = 1043 n / ms->smp.threads % ms->smp.cores; 1044 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1045 ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads; 1046 } 1047 return ms->possible_cpus; 1048 } 1049 1050 static CpuInstanceProperties 1051 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1052 { 1053 MachineClass *mc = MACHINE_GET_CLASS(ms); 1054 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1055 1056 assert(cpu_index < possible_cpus->len); 1057 return possible_cpus->cpus[cpu_index].props; 1058 } 1059 1060 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1061 { 1062 int64_t nidx = 0; 1063 1064 if (ms->numa_state->num_nodes) { 1065 nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes); 1066 if (ms->numa_state->num_nodes <= nidx) { 1067 nidx = ms->numa_state->num_nodes - 1; 1068 } 1069 } 1070 return nidx; 1071 } 1072 1073 static void loongarch_class_init(ObjectClass *oc, void *data) 1074 { 1075 MachineClass *mc = MACHINE_CLASS(oc); 1076 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1077 1078 mc->desc = "Loongson-3A5000 LS7A1000 machine"; 1079 mc->init = loongarch_init; 1080 mc->default_ram_size = 1 * GiB; 1081 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); 1082 mc->default_ram_id = "loongarch.ram"; 1083 mc->max_cpus = LOONGARCH_MAX_CPUS; 1084 mc->is_default = 1; 1085 mc->default_kernel_irqchip_split = false; 1086 mc->block_default_type = IF_VIRTIO; 1087 mc->default_boot_order = "c"; 1088 mc->no_cdrom = 1; 1089 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1090 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1091 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1092 mc->numa_mem_supported = true; 1093 mc->auto_enable_numa_with_memhp = true; 1094 mc->auto_enable_numa_with_memdev = true; 1095 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1096 mc->default_nic = "virtio-net-pci"; 1097 hc->plug = loongarch_machine_device_plug_cb; 1098 hc->pre_plug = virt_machine_device_pre_plug; 1099 hc->unplug_request = virt_machine_device_unplug_request; 1100 hc->unplug = virt_machine_device_unplug; 1101 1102 object_class_property_add(oc, "acpi", "OnOffAuto", 1103 loongarch_get_acpi, loongarch_set_acpi, 1104 NULL, NULL); 1105 object_class_property_set_description(oc, "acpi", 1106 "Enable ACPI"); 1107 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1108 #ifdef CONFIG_TPM 1109 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1110 #endif 1111 } 1112 1113 static const TypeInfo loongarch_machine_types[] = { 1114 { 1115 .name = TYPE_LOONGARCH_MACHINE, 1116 .parent = TYPE_MACHINE, 1117 .instance_size = sizeof(LoongArchMachineState), 1118 .class_init = loongarch_class_init, 1119 .instance_init = loongarch_machine_initfn, 1120 .interfaces = (InterfaceInfo[]) { 1121 { TYPE_HOTPLUG_HANDLER }, 1122 { } 1123 }, 1124 } 1125 }; 1126 1127 DEFINE_TYPES(loongarch_machine_types) 1128