1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU loongson 3a5000 develop board emulation 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 #include "qemu/osdep.h" 8 #include "qemu/units.h" 9 #include "qemu/datadir.h" 10 #include "qapi/error.h" 11 #include "hw/boards.h" 12 #include "hw/char/serial.h" 13 #include "sysemu/sysemu.h" 14 #include "sysemu/qtest.h" 15 #include "sysemu/runstate.h" 16 #include "sysemu/reset.h" 17 #include "sysemu/rtc.h" 18 #include "hw/loongarch/virt.h" 19 #include "exec/address-spaces.h" 20 #include "hw/irq.h" 21 #include "net/net.h" 22 #include "hw/loader.h" 23 #include "elf.h" 24 #include "hw/intc/loongarch_ipi.h" 25 #include "hw/intc/loongarch_extioi.h" 26 #include "hw/intc/loongarch_pch_pic.h" 27 #include "hw/intc/loongarch_pch_msi.h" 28 #include "hw/pci-host/ls7a.h" 29 #include "hw/pci-host/gpex.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/loongarch/fw_cfg.h" 32 #include "target/loongarch/cpu.h" 33 #include "hw/firmware/smbios.h" 34 #include "hw/acpi/aml-build.h" 35 #include "qapi/qapi-visit-common.h" 36 #include "hw/acpi/generic_event_device.h" 37 #include "hw/mem/nvdimm.h" 38 #include "sysemu/device_tree.h" 39 #include <libfdt.h> 40 #include "hw/core/sysbus-fdt.h" 41 #include "hw/platform-bus.h" 42 #include "hw/display/ramfb.h" 43 #include "hw/mem/pc-dimm.h" 44 #include "sysemu/tpm.h" 45 #include "sysemu/block-backend.h" 46 #include "hw/block/flash.h" 47 #include "qemu/error-report.h" 48 49 50 static void virt_flash_create(LoongArchMachineState *lams) 51 { 52 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 53 54 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 55 qdev_prop_set_uint8(dev, "width", 4); 56 qdev_prop_set_uint8(dev, "device-width", 2); 57 qdev_prop_set_bit(dev, "big-endian", false); 58 qdev_prop_set_uint16(dev, "id0", 0x89); 59 qdev_prop_set_uint16(dev, "id1", 0x18); 60 qdev_prop_set_uint16(dev, "id2", 0x00); 61 qdev_prop_set_uint16(dev, "id3", 0x00); 62 qdev_prop_set_string(dev, "name", "virt.flash"); 63 object_property_add_child(OBJECT(lams), "virt.flash", OBJECT(dev)); 64 object_property_add_alias(OBJECT(lams), "pflash", 65 OBJECT(dev), "drive"); 66 67 lams->flash = PFLASH_CFI01(dev); 68 } 69 70 static void virt_flash_map(LoongArchMachineState *lams, 71 MemoryRegion *sysmem) 72 { 73 PFlashCFI01 *flash = lams->flash; 74 DeviceState *dev = DEVICE(flash); 75 hwaddr base = VIRT_FLASH_BASE; 76 hwaddr size = VIRT_FLASH_SIZE; 77 78 assert(QEMU_IS_ALIGNED(size, VIRT_FLASH_SECTOR_SIZE)); 79 assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 80 81 qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); 82 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 83 memory_region_add_subregion(sysmem, base, 84 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 85 86 } 87 88 static void fdt_add_flash_node(LoongArchMachineState *lams) 89 { 90 MachineState *ms = MACHINE(lams); 91 char *nodename; 92 93 hwaddr flash_base = VIRT_FLASH_BASE; 94 hwaddr flash_size = VIRT_FLASH_SIZE; 95 96 nodename = g_strdup_printf("/flash@%" PRIx64, flash_base); 97 qemu_fdt_add_subnode(ms->fdt, nodename); 98 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 99 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 100 2, flash_base, 2, flash_size); 101 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 102 g_free(nodename); 103 } 104 105 static void fdt_add_rtc_node(LoongArchMachineState *lams) 106 { 107 char *nodename; 108 hwaddr base = VIRT_RTC_REG_BASE; 109 hwaddr size = VIRT_RTC_LEN; 110 MachineState *ms = MACHINE(lams); 111 112 nodename = g_strdup_printf("/rtc@%" PRIx64, base); 113 qemu_fdt_add_subnode(ms->fdt, nodename); 114 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc"); 115 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 116 g_free(nodename); 117 } 118 119 static void fdt_add_uart_node(LoongArchMachineState *lams) 120 { 121 char *nodename; 122 hwaddr base = VIRT_UART_BASE; 123 hwaddr size = VIRT_UART_SIZE; 124 MachineState *ms = MACHINE(lams); 125 126 nodename = g_strdup_printf("/serial@%" PRIx64, base); 127 qemu_fdt_add_subnode(ms->fdt, nodename); 128 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a"); 129 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size); 130 qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000); 131 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 132 g_free(nodename); 133 } 134 135 static void create_fdt(LoongArchMachineState *lams) 136 { 137 MachineState *ms = MACHINE(lams); 138 139 ms->fdt = create_device_tree(&lams->fdt_size); 140 if (!ms->fdt) { 141 error_report("create_device_tree() failed"); 142 exit(1); 143 } 144 145 /* Header */ 146 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", 147 "linux,dummy-loongson3"); 148 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 149 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 150 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 151 } 152 153 static void fdt_add_cpu_nodes(const LoongArchMachineState *lams) 154 { 155 int num; 156 const MachineState *ms = MACHINE(lams); 157 int smp_cpus = ms->smp.cpus; 158 159 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 160 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 161 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 162 163 /* cpu nodes */ 164 for (num = smp_cpus - 1; num >= 0; num--) { 165 char *nodename = g_strdup_printf("/cpus/cpu@%d", num); 166 LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num)); 167 CPUState *cs = CPU(cpu); 168 169 qemu_fdt_add_subnode(ms->fdt, nodename); 170 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 171 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 172 cpu->dtb_compatible); 173 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 174 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 175 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 176 } 177 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); 178 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 179 qemu_fdt_alloc_phandle(ms->fdt)); 180 g_free(nodename); 181 } 182 183 /*cpu map */ 184 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 185 186 for (num = smp_cpus - 1; num >= 0; num--) { 187 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num); 188 char *map_path; 189 190 if (ms->smp.threads > 1) { 191 map_path = g_strdup_printf( 192 "/cpus/cpu-map/socket%d/core%d/thread%d", 193 num / (ms->smp.cores * ms->smp.threads), 194 (num / ms->smp.threads) % ms->smp.cores, 195 num % ms->smp.threads); 196 } else { 197 map_path = g_strdup_printf( 198 "/cpus/cpu-map/socket%d/core%d", 199 num / ms->smp.cores, 200 num % ms->smp.cores); 201 } 202 qemu_fdt_add_path(ms->fdt, map_path); 203 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 204 205 g_free(map_path); 206 g_free(cpu_path); 207 } 208 } 209 210 static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams) 211 { 212 char *nodename; 213 hwaddr base = VIRT_FWCFG_BASE; 214 const MachineState *ms = MACHINE(lams); 215 216 nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base); 217 qemu_fdt_add_subnode(ms->fdt, nodename); 218 qemu_fdt_setprop_string(ms->fdt, nodename, 219 "compatible", "qemu,fw-cfg-mmio"); 220 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 221 2, base, 2, 0x18); 222 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 223 g_free(nodename); 224 } 225 226 static void fdt_add_pcie_node(const LoongArchMachineState *lams) 227 { 228 char *nodename; 229 hwaddr base_mmio = VIRT_PCI_MEM_BASE; 230 hwaddr size_mmio = VIRT_PCI_MEM_SIZE; 231 hwaddr base_pio = VIRT_PCI_IO_BASE; 232 hwaddr size_pio = VIRT_PCI_IO_SIZE; 233 hwaddr base_pcie = VIRT_PCI_CFG_BASE; 234 hwaddr size_pcie = VIRT_PCI_CFG_SIZE; 235 hwaddr base = base_pcie; 236 237 const MachineState *ms = MACHINE(lams); 238 239 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 240 qemu_fdt_add_subnode(ms->fdt, nodename); 241 qemu_fdt_setprop_string(ms->fdt, nodename, 242 "compatible", "pci-host-ecam-generic"); 243 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 244 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 245 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 246 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 247 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 248 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); 249 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 250 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 251 2, base_pcie, 2, size_pcie); 252 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 253 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, 254 2, base_pio, 2, size_pio, 255 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 256 2, base_mmio, 2, size_mmio); 257 g_free(nodename); 258 } 259 260 static void fdt_add_irqchip_node(LoongArchMachineState *lams) 261 { 262 MachineState *ms = MACHINE(lams); 263 char *nodename; 264 uint32_t irqchip_phandle; 265 266 irqchip_phandle = qemu_fdt_alloc_phandle(ms->fdt); 267 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", irqchip_phandle); 268 269 nodename = g_strdup_printf("/intc@%lx", VIRT_IOAPIC_REG_BASE); 270 qemu_fdt_add_subnode(ms->fdt, nodename); 271 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 272 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 273 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 274 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 275 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 276 277 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 278 "loongarch,ls7a"); 279 280 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 281 2, VIRT_IOAPIC_REG_BASE, 282 2, PCH_PIC_ROUTE_ENTRY_OFFSET); 283 284 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", irqchip_phandle); 285 g_free(nodename); 286 } 287 288 static void fdt_add_memory_node(MachineState *ms, 289 uint64_t base, uint64_t size, int node_id) 290 { 291 char *nodename = g_strdup_printf("/memory@%" PRIx64, base); 292 293 qemu_fdt_add_subnode(ms->fdt, nodename); 294 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 295 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 296 297 if (ms->numa_state && ms->numa_state->num_nodes) { 298 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id); 299 } 300 301 g_free(nodename); 302 } 303 304 #define PM_BASE 0x10080000 305 #define PM_SIZE 0x100 306 #define PM_CTRL 0x10 307 308 static void virt_build_smbios(LoongArchMachineState *lams) 309 { 310 MachineState *ms = MACHINE(lams); 311 MachineClass *mc = MACHINE_GET_CLASS(lams); 312 uint8_t *smbios_tables, *smbios_anchor; 313 size_t smbios_tables_len, smbios_anchor_len; 314 const char *product = "QEMU Virtual Machine"; 315 316 if (!lams->fw_cfg) { 317 return; 318 } 319 320 smbios_set_defaults("QEMU", product, mc->name, false, 321 true, SMBIOS_ENTRY_POINT_TYPE_64); 322 323 smbios_get_tables(ms, NULL, 0, &smbios_tables, &smbios_tables_len, 324 &smbios_anchor, &smbios_anchor_len, &error_fatal); 325 326 if (smbios_anchor) { 327 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables", 328 smbios_tables, smbios_tables_len); 329 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor", 330 smbios_anchor, smbios_anchor_len); 331 } 332 } 333 334 static void virt_machine_done(Notifier *notifier, void *data) 335 { 336 LoongArchMachineState *lams = container_of(notifier, 337 LoongArchMachineState, machine_done); 338 virt_build_smbios(lams); 339 loongarch_acpi_setup(lams); 340 } 341 342 static void virt_powerdown_req(Notifier *notifier, void *opaque) 343 { 344 LoongArchMachineState *s = container_of(notifier, 345 LoongArchMachineState, powerdown_notifier); 346 347 acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS); 348 } 349 350 struct memmap_entry { 351 uint64_t address; 352 uint64_t length; 353 uint32_t type; 354 uint32_t reserved; 355 }; 356 357 static struct memmap_entry *memmap_table; 358 static unsigned memmap_entries; 359 360 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) 361 { 362 /* Ensure there are no duplicate entries. */ 363 for (unsigned i = 0; i < memmap_entries; i++) { 364 assert(memmap_table[i].address != address); 365 } 366 367 memmap_table = g_renew(struct memmap_entry, memmap_table, 368 memmap_entries + 1); 369 memmap_table[memmap_entries].address = cpu_to_le64(address); 370 memmap_table[memmap_entries].length = cpu_to_le64(length); 371 memmap_table[memmap_entries].type = cpu_to_le32(type); 372 memmap_table[memmap_entries].reserved = 0; 373 memmap_entries++; 374 } 375 376 /* 377 * This is a placeholder for missing ACPI, 378 * and will eventually be replaced. 379 */ 380 static uint64_t loongarch_virt_pm_read(void *opaque, hwaddr addr, unsigned size) 381 { 382 return 0; 383 } 384 385 static void loongarch_virt_pm_write(void *opaque, hwaddr addr, 386 uint64_t val, unsigned size) 387 { 388 if (addr != PM_CTRL) { 389 return; 390 } 391 392 switch (val) { 393 case 0x00: 394 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 395 return; 396 case 0xff: 397 qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); 398 return; 399 default: 400 return; 401 } 402 } 403 404 static const MemoryRegionOps loongarch_virt_pm_ops = { 405 .read = loongarch_virt_pm_read, 406 .write = loongarch_virt_pm_write, 407 .endianness = DEVICE_NATIVE_ENDIAN, 408 .valid = { 409 .min_access_size = 1, 410 .max_access_size = 1 411 } 412 }; 413 414 static struct _loaderparams { 415 uint64_t ram_size; 416 const char *kernel_filename; 417 const char *kernel_cmdline; 418 const char *initrd_filename; 419 } loaderparams; 420 421 static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr) 422 { 423 return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS); 424 } 425 426 static int64_t load_kernel_info(void) 427 { 428 uint64_t kernel_entry, kernel_low, kernel_high; 429 ssize_t kernel_size; 430 431 kernel_size = load_elf(loaderparams.kernel_filename, NULL, 432 cpu_loongarch_virt_to_phys, NULL, 433 &kernel_entry, &kernel_low, 434 &kernel_high, NULL, 0, 435 EM_LOONGARCH, 1, 0); 436 437 if (kernel_size < 0) { 438 error_report("could not load kernel '%s': %s", 439 loaderparams.kernel_filename, 440 load_elf_strerror(kernel_size)); 441 exit(1); 442 } 443 return kernel_entry; 444 } 445 446 static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams) 447 { 448 DeviceState *dev; 449 MachineState *ms = MACHINE(lams); 450 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 451 452 if (ms->ram_slots) { 453 event |= ACPI_GED_MEM_HOTPLUG_EVT; 454 } 455 dev = qdev_new(TYPE_ACPI_GED); 456 qdev_prop_set_uint32(dev, "ged-event", event); 457 458 /* ged event */ 459 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); 460 /* memory hotplug */ 461 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); 462 /* ged regs used for reset and power down */ 463 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); 464 465 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 466 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE)); 467 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 468 return dev; 469 } 470 471 static DeviceState *create_platform_bus(DeviceState *pch_pic) 472 { 473 DeviceState *dev; 474 SysBusDevice *sysbus; 475 int i, irq; 476 MemoryRegion *sysmem = get_system_memory(); 477 478 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 479 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 480 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 481 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); 482 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 483 484 sysbus = SYS_BUS_DEVICE(dev); 485 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 486 irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i; 487 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); 488 } 489 490 memory_region_add_subregion(sysmem, 491 VIRT_PLATFORM_BUS_BASEADDRESS, 492 sysbus_mmio_get_region(sysbus, 0)); 493 return dev; 494 } 495 496 static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *lams) 497 { 498 MachineClass *mc = MACHINE_GET_CLASS(lams); 499 DeviceState *gpex_dev; 500 SysBusDevice *d; 501 PCIBus *pci_bus; 502 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; 503 MemoryRegion *mmio_alias, *mmio_reg, *pm_mem; 504 int i; 505 506 gpex_dev = qdev_new(TYPE_GPEX_HOST); 507 d = SYS_BUS_DEVICE(gpex_dev); 508 sysbus_realize_and_unref(d, &error_fatal); 509 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; 510 lams->pci_bus = pci_bus; 511 512 /* Map only part size_ecam bytes of ECAM space */ 513 ecam_alias = g_new0(MemoryRegion, 1); 514 ecam_reg = sysbus_mmio_get_region(d, 0); 515 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", 516 ecam_reg, 0, VIRT_PCI_CFG_SIZE); 517 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, 518 ecam_alias); 519 520 /* Map PCI mem space */ 521 mmio_alias = g_new0(MemoryRegion, 1); 522 mmio_reg = sysbus_mmio_get_region(d, 1); 523 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", 524 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); 525 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, 526 mmio_alias); 527 528 /* Map PCI IO port space. */ 529 pio_alias = g_new0(MemoryRegion, 1); 530 pio_reg = sysbus_mmio_get_region(d, 2); 531 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, 532 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); 533 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, 534 pio_alias); 535 536 for (i = 0; i < GPEX_NUM_IRQS; i++) { 537 sysbus_connect_irq(d, i, 538 qdev_get_gpio_in(pch_pic, 16 + i)); 539 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); 540 } 541 542 serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, 543 qdev_get_gpio_in(pch_pic, 544 VIRT_UART_IRQ - VIRT_GSI_BASE), 545 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 546 fdt_add_uart_node(lams); 547 548 /* Network init */ 549 for (i = 0; i < nb_nics; i++) { 550 NICInfo *nd = &nd_table[i]; 551 552 if (!nd->model) { 553 nd->model = g_strdup(mc->default_nic); 554 } 555 556 pci_nic_init_nofail(nd, pci_bus, nd->model, NULL); 557 } 558 559 /* 560 * There are some invalid guest memory access. 561 * Create some unimplemented devices to emulate this. 562 */ 563 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); 564 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, 565 qdev_get_gpio_in(pch_pic, 566 VIRT_RTC_IRQ - VIRT_GSI_BASE)); 567 fdt_add_rtc_node(lams); 568 569 pm_mem = g_new(MemoryRegion, 1); 570 memory_region_init_io(pm_mem, NULL, &loongarch_virt_pm_ops, 571 NULL, "loongarch_virt_pm", PM_SIZE); 572 memory_region_add_subregion(get_system_memory(), PM_BASE, pm_mem); 573 /* acpi ged */ 574 lams->acpi_ged = create_acpi_ged(pch_pic, lams); 575 /* platform bus */ 576 lams->platform_bus_dev = create_platform_bus(pch_pic); 577 } 578 579 static void loongarch_irq_init(LoongArchMachineState *lams) 580 { 581 MachineState *ms = MACHINE(lams); 582 DeviceState *pch_pic, *pch_msi, *cpudev; 583 DeviceState *ipi, *extioi; 584 SysBusDevice *d; 585 LoongArchCPU *lacpu; 586 CPULoongArchState *env; 587 CPUState *cpu_state; 588 int cpu, pin, i, start, num; 589 590 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); 591 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); 592 593 /* 594 * The connection of interrupts: 595 * +-----+ +---------+ +-------+ 596 * | IPI |--> | CPUINTC | <-- | Timer | 597 * +-----+ +---------+ +-------+ 598 * ^ 599 * | 600 * +---------+ 601 * | EIOINTC | 602 * +---------+ 603 * ^ ^ 604 * | | 605 * +---------+ +---------+ 606 * | PCH-PIC | | PCH-MSI | 607 * +---------+ +---------+ 608 * ^ ^ ^ 609 * | | | 610 * +--------+ +---------+ +---------+ 611 * | UARTs | | Devices | | Devices | 612 * +--------+ +---------+ +---------+ 613 */ 614 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 615 cpu_state = qemu_get_cpu(cpu); 616 cpudev = DEVICE(cpu_state); 617 lacpu = LOONGARCH_CPU(cpu_state); 618 env = &(lacpu->env); 619 620 ipi = qdev_new(TYPE_LOONGARCH_IPI); 621 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 622 623 /* connect ipi irq to cpu irq */ 624 qdev_connect_gpio_out(ipi, 0, qdev_get_gpio_in(cpudev, IRQ_IPI)); 625 /* IPI iocsr memory region */ 626 memory_region_add_subregion(&env->system_iocsr, SMP_IPI_MAILBOX, 627 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 628 0)); 629 memory_region_add_subregion(&env->system_iocsr, MAIL_SEND_ADDR, 630 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 631 1)); 632 /* 633 * extioi iocsr memory region 634 * only one extioi is added on loongarch virt machine 635 * external device interrupt can only be routed to cpu 0-3 636 */ 637 if (cpu < EXTIOI_CPUS) 638 memory_region_add_subregion(&env->system_iocsr, APIC_BASE, 639 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 640 cpu)); 641 env->ipistate = ipi; 642 } 643 644 /* 645 * connect ext irq to the cpu irq 646 * cpu_pin[9:2] <= intc_pin[7:0] 647 */ 648 for (cpu = 0; cpu < MIN(ms->smp.cpus, EXTIOI_CPUS); cpu++) { 649 cpudev = DEVICE(qemu_get_cpu(cpu)); 650 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 651 qdev_connect_gpio_out(extioi, (cpu * 8 + pin), 652 qdev_get_gpio_in(cpudev, pin + 2)); 653 } 654 } 655 656 pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); 657 num = VIRT_PCH_PIC_IRQ_NUM; 658 qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); 659 d = SYS_BUS_DEVICE(pch_pic); 660 sysbus_realize_and_unref(d, &error_fatal); 661 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, 662 sysbus_mmio_get_region(d, 0)); 663 memory_region_add_subregion(get_system_memory(), 664 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, 665 sysbus_mmio_get_region(d, 1)); 666 memory_region_add_subregion(get_system_memory(), 667 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, 668 sysbus_mmio_get_region(d, 2)); 669 670 /* Connect pch_pic irqs to extioi */ 671 for (int i = 0; i < num; i++) { 672 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); 673 } 674 675 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); 676 start = num; 677 num = EXTIOI_IRQS - start; 678 qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); 679 qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); 680 d = SYS_BUS_DEVICE(pch_msi); 681 sysbus_realize_and_unref(d, &error_fatal); 682 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); 683 for (i = 0; i < num; i++) { 684 /* Connect pch_msi irqs to extioi */ 685 qdev_connect_gpio_out(DEVICE(d), i, 686 qdev_get_gpio_in(extioi, i + start)); 687 } 688 689 loongarch_devices_init(pch_pic, lams); 690 } 691 692 static void loongarch_firmware_init(LoongArchMachineState *lams) 693 { 694 char *filename = MACHINE(lams)->firmware; 695 char *bios_name = NULL; 696 int bios_size; 697 698 lams->bios_loaded = false; 699 700 virt_flash_map(lams, get_system_memory()); 701 702 if (filename) { 703 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); 704 if (!bios_name) { 705 error_report("Could not find ROM image '%s'", filename); 706 exit(1); 707 } 708 709 bios_size = load_image_targphys(bios_name, VIRT_BIOS_BASE, VIRT_BIOS_SIZE); 710 if (bios_size < 0) { 711 error_report("Could not load ROM image '%s'", bios_name); 712 exit(1); 713 } 714 715 g_free(bios_name); 716 717 memory_region_init_ram(&lams->bios, NULL, "loongarch.bios", 718 VIRT_BIOS_SIZE, &error_fatal); 719 memory_region_set_readonly(&lams->bios, true); 720 memory_region_add_subregion(get_system_memory(), VIRT_BIOS_BASE, &lams->bios); 721 lams->bios_loaded = true; 722 } 723 724 } 725 726 static void reset_load_elf(void *opaque) 727 { 728 LoongArchCPU *cpu = opaque; 729 CPULoongArchState *env = &cpu->env; 730 731 cpu_reset(CPU(cpu)); 732 if (env->load_elf) { 733 cpu_set_pc(CPU(cpu), env->elf_address); 734 } 735 } 736 737 static void fw_cfg_add_kernel_info(FWCfgState *fw_cfg) 738 { 739 /* 740 * Expose the kernel, the command line, and the initrd in fw_cfg. 741 * We don't process them here at all, it's all left to the 742 * firmware. 743 */ 744 load_image_to_fw_cfg(fw_cfg, 745 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 746 loaderparams.kernel_filename, 747 false); 748 749 if (loaderparams.initrd_filename) { 750 load_image_to_fw_cfg(fw_cfg, 751 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 752 loaderparams.initrd_filename, false); 753 } 754 755 if (loaderparams.kernel_cmdline) { 756 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 757 strlen(loaderparams.kernel_cmdline) + 1); 758 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 759 loaderparams.kernel_cmdline); 760 } 761 } 762 763 static void loongarch_firmware_boot(LoongArchMachineState *lams) 764 { 765 fw_cfg_add_kernel_info(lams->fw_cfg); 766 } 767 768 static void loongarch_direct_kernel_boot(LoongArchMachineState *lams) 769 { 770 MachineState *machine = MACHINE(lams); 771 int64_t kernel_addr = 0; 772 LoongArchCPU *lacpu; 773 int i; 774 775 kernel_addr = load_kernel_info(); 776 if (!machine->firmware) { 777 for (i = 0; i < machine->smp.cpus; i++) { 778 lacpu = LOONGARCH_CPU(qemu_get_cpu(i)); 779 lacpu->env.load_elf = true; 780 lacpu->env.elf_address = kernel_addr; 781 } 782 } 783 } 784 785 static void loongarch_init(MachineState *machine) 786 { 787 LoongArchCPU *lacpu; 788 const char *cpu_model = machine->cpu_type; 789 ram_addr_t offset = 0; 790 ram_addr_t ram_size = machine->ram_size; 791 uint64_t highram_size = 0, phyAddr = 0; 792 MemoryRegion *address_space_mem = get_system_memory(); 793 LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); 794 int nb_numa_nodes = machine->numa_state->num_nodes; 795 NodeInfo *numa_info = machine->numa_state->nodes; 796 int i; 797 hwaddr fdt_base; 798 const CPUArchIdList *possible_cpus; 799 MachineClass *mc = MACHINE_GET_CLASS(machine); 800 CPUState *cpu; 801 char *ramName = NULL; 802 803 if (!cpu_model) { 804 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); 805 } 806 807 if (!strstr(cpu_model, "la464")) { 808 error_report("LoongArch/TCG needs cpu type la464"); 809 exit(1); 810 } 811 812 if (ram_size < 1 * GiB) { 813 error_report("ram_size must be greater than 1G."); 814 exit(1); 815 } 816 create_fdt(lams); 817 /* Init CPUs */ 818 819 possible_cpus = mc->possible_cpu_arch_ids(machine); 820 for (i = 0; i < possible_cpus->len; i++) { 821 cpu = cpu_create(machine->cpu_type); 822 cpu->cpu_index = i; 823 machine->possible_cpus->cpus[i].cpu = OBJECT(cpu); 824 } 825 fdt_add_cpu_nodes(lams); 826 827 /* Node0 memory */ 828 memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1); 829 fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0); 830 memory_region_init_alias(&lams->lowmem, NULL, "loongarch.node0.lowram", 831 machine->ram, offset, VIRT_LOWMEM_SIZE); 832 memory_region_add_subregion(address_space_mem, phyAddr, &lams->lowmem); 833 834 offset += VIRT_LOWMEM_SIZE; 835 if (nb_numa_nodes > 0) { 836 assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE); 837 highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE; 838 } else { 839 highram_size = ram_size - VIRT_LOWMEM_SIZE; 840 } 841 phyAddr = VIRT_HIGHMEM_BASE; 842 memmap_add_entry(phyAddr, highram_size, 1); 843 fdt_add_memory_node(machine, phyAddr, highram_size, 0); 844 memory_region_init_alias(&lams->highmem, NULL, "loongarch.node0.highram", 845 machine->ram, offset, highram_size); 846 memory_region_add_subregion(address_space_mem, phyAddr, &lams->highmem); 847 848 /* Node1 - Nodemax memory */ 849 offset += highram_size; 850 phyAddr += highram_size; 851 852 for (i = 1; i < nb_numa_nodes; i++) { 853 MemoryRegion *nodemem = g_new(MemoryRegion, 1); 854 ramName = g_strdup_printf("loongarch.node%d.ram", i); 855 memory_region_init_alias(nodemem, NULL, ramName, machine->ram, 856 offset, numa_info[i].node_mem); 857 memory_region_add_subregion(address_space_mem, phyAddr, nodemem); 858 memmap_add_entry(phyAddr, numa_info[i].node_mem, 1); 859 fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i); 860 offset += numa_info[i].node_mem; 861 phyAddr += numa_info[i].node_mem; 862 } 863 864 /* initialize device memory address space */ 865 if (machine->ram_size < machine->maxram_size) { 866 machine->device_memory = g_malloc0(sizeof(*machine->device_memory)); 867 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 868 869 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 870 error_report("unsupported amount of memory slots: %"PRIu64, 871 machine->ram_slots); 872 exit(EXIT_FAILURE); 873 } 874 875 if (QEMU_ALIGN_UP(machine->maxram_size, 876 TARGET_PAGE_SIZE) != machine->maxram_size) { 877 error_report("maximum memory size must by aligned to multiple of " 878 "%d bytes", TARGET_PAGE_SIZE); 879 exit(EXIT_FAILURE); 880 } 881 /* device memory base is the top of high memory address. */ 882 machine->device_memory->base = 0x90000000 + highram_size; 883 machine->device_memory->base = 884 ROUND_UP(machine->device_memory->base, 1 * GiB); 885 886 memory_region_init(&machine->device_memory->mr, OBJECT(lams), 887 "device-memory", device_mem_size); 888 memory_region_add_subregion(address_space_mem, machine->device_memory->base, 889 &machine->device_memory->mr); 890 } 891 892 /* Add isa io region */ 893 memory_region_init_alias(&lams->isa_io, NULL, "isa-io", 894 get_system_io(), 0, VIRT_ISA_IO_SIZE); 895 memory_region_add_subregion(address_space_mem, VIRT_ISA_IO_BASE, 896 &lams->isa_io); 897 /* load the BIOS image. */ 898 loongarch_firmware_init(lams); 899 900 /* fw_cfg init */ 901 lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine); 902 rom_set_fw(lams->fw_cfg); 903 if (lams->fw_cfg != NULL) { 904 fw_cfg_add_file(lams->fw_cfg, "etc/memmap", 905 memmap_table, 906 sizeof(struct memmap_entry) * (memmap_entries)); 907 } 908 fdt_add_fw_cfg_node(lams); 909 loaderparams.ram_size = ram_size; 910 loaderparams.kernel_filename = machine->kernel_filename; 911 loaderparams.kernel_cmdline = machine->kernel_cmdline; 912 loaderparams.initrd_filename = machine->initrd_filename; 913 /* load the kernel. */ 914 if (loaderparams.kernel_filename) { 915 if (lams->bios_loaded) { 916 loongarch_firmware_boot(lams); 917 } else { 918 loongarch_direct_kernel_boot(lams); 919 } 920 } 921 fdt_add_flash_node(lams); 922 /* register reset function */ 923 for (i = 0; i < machine->smp.cpus; i++) { 924 lacpu = LOONGARCH_CPU(qemu_get_cpu(i)); 925 qemu_register_reset(reset_load_elf, lacpu); 926 } 927 /* Initialize the IO interrupt subsystem */ 928 loongarch_irq_init(lams); 929 fdt_add_irqchip_node(lams); 930 platform_bus_add_all_fdt_nodes(machine->fdt, "/intc", 931 VIRT_PLATFORM_BUS_BASEADDRESS, 932 VIRT_PLATFORM_BUS_SIZE, 933 VIRT_PLATFORM_BUS_IRQ); 934 lams->machine_done.notify = virt_machine_done; 935 qemu_add_machine_init_done_notifier(&lams->machine_done); 936 /* connect powerdown request */ 937 lams->powerdown_notifier.notify = virt_powerdown_req; 938 qemu_register_powerdown_notifier(&lams->powerdown_notifier); 939 940 fdt_add_pcie_node(lams); 941 /* 942 * Since lowmem region starts from 0 and Linux kernel legacy start address 943 * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer 944 * access. FDT size limit with 1 MiB. 945 * Put the FDT into the memory map as a ROM image: this will ensure 946 * the FDT is copied again upon reset, even if addr points into RAM. 947 */ 948 fdt_base = 1 * MiB; 949 qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size); 950 rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, fdt_base); 951 } 952 953 bool loongarch_is_acpi_enabled(LoongArchMachineState *lams) 954 { 955 if (lams->acpi == ON_OFF_AUTO_OFF) { 956 return false; 957 } 958 return true; 959 } 960 961 static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name, 962 void *opaque, Error **errp) 963 { 964 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 965 OnOffAuto acpi = lams->acpi; 966 967 visit_type_OnOffAuto(v, name, &acpi, errp); 968 } 969 970 static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name, 971 void *opaque, Error **errp) 972 { 973 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 974 975 visit_type_OnOffAuto(v, name, &lams->acpi, errp); 976 } 977 978 static void loongarch_machine_initfn(Object *obj) 979 { 980 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 981 982 lams->acpi = ON_OFF_AUTO_AUTO; 983 lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 984 lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 985 virt_flash_create(lams); 986 } 987 988 static bool memhp_type_supported(DeviceState *dev) 989 { 990 /* we only support pc dimm now */ 991 return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && 992 !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 993 } 994 995 static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 996 Error **errp) 997 { 998 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 999 } 1000 1001 static void virt_machine_device_pre_plug(HotplugHandler *hotplug_dev, 1002 DeviceState *dev, Error **errp) 1003 { 1004 if (memhp_type_supported(dev)) { 1005 virt_mem_pre_plug(hotplug_dev, dev, errp); 1006 } 1007 } 1008 1009 static void virt_mem_unplug_request(HotplugHandler *hotplug_dev, 1010 DeviceState *dev, Error **errp) 1011 { 1012 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1013 1014 /* the acpi ged is always exist */ 1015 hotplug_handler_unplug_request(HOTPLUG_HANDLER(lams->acpi_ged), dev, 1016 errp); 1017 } 1018 1019 static void virt_machine_device_unplug_request(HotplugHandler *hotplug_dev, 1020 DeviceState *dev, Error **errp) 1021 { 1022 if (memhp_type_supported(dev)) { 1023 virt_mem_unplug_request(hotplug_dev, dev, errp); 1024 } 1025 } 1026 1027 static void virt_mem_unplug(HotplugHandler *hotplug_dev, 1028 DeviceState *dev, Error **errp) 1029 { 1030 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1031 1032 hotplug_handler_unplug(HOTPLUG_HANDLER(lams->acpi_ged), dev, errp); 1033 pc_dimm_unplug(PC_DIMM(dev), MACHINE(lams)); 1034 qdev_unrealize(dev); 1035 } 1036 1037 static void virt_machine_device_unplug(HotplugHandler *hotplug_dev, 1038 DeviceState *dev, Error **errp) 1039 { 1040 if (memhp_type_supported(dev)) { 1041 virt_mem_unplug(hotplug_dev, dev, errp); 1042 } 1043 } 1044 1045 static void virt_mem_plug(HotplugHandler *hotplug_dev, 1046 DeviceState *dev, Error **errp) 1047 { 1048 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1049 1050 pc_dimm_plug(PC_DIMM(dev), MACHINE(lams)); 1051 hotplug_handler_plug(HOTPLUG_HANDLER(lams->acpi_ged), 1052 dev, &error_abort); 1053 } 1054 1055 static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1056 DeviceState *dev, Error **errp) 1057 { 1058 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1059 MachineClass *mc = MACHINE_GET_CLASS(lams); 1060 1061 if (device_is_dynamic_sysbus(mc, dev)) { 1062 if (lams->platform_bus_dev) { 1063 platform_bus_link_device(PLATFORM_BUS_DEVICE(lams->platform_bus_dev), 1064 SYS_BUS_DEVICE(dev)); 1065 } 1066 } else if (memhp_type_supported(dev)) { 1067 virt_mem_plug(hotplug_dev, dev, errp); 1068 } 1069 } 1070 1071 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1072 DeviceState *dev) 1073 { 1074 MachineClass *mc = MACHINE_GET_CLASS(machine); 1075 1076 if (device_is_dynamic_sysbus(mc, dev) || 1077 memhp_type_supported(dev)) { 1078 return HOTPLUG_HANDLER(machine); 1079 } 1080 return NULL; 1081 } 1082 1083 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1084 { 1085 int n; 1086 unsigned int max_cpus = ms->smp.max_cpus; 1087 1088 if (ms->possible_cpus) { 1089 assert(ms->possible_cpus->len == max_cpus); 1090 return ms->possible_cpus; 1091 } 1092 1093 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1094 sizeof(CPUArchId) * max_cpus); 1095 ms->possible_cpus->len = max_cpus; 1096 for (n = 0; n < ms->possible_cpus->len; n++) { 1097 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1098 ms->possible_cpus->cpus[n].arch_id = n; 1099 1100 ms->possible_cpus->cpus[n].props.has_socket_id = true; 1101 ms->possible_cpus->cpus[n].props.socket_id = 1102 n / (ms->smp.cores * ms->smp.threads); 1103 ms->possible_cpus->cpus[n].props.has_core_id = true; 1104 ms->possible_cpus->cpus[n].props.core_id = 1105 n / ms->smp.threads % ms->smp.cores; 1106 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1107 ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads; 1108 } 1109 return ms->possible_cpus; 1110 } 1111 1112 static CpuInstanceProperties 1113 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1114 { 1115 MachineClass *mc = MACHINE_GET_CLASS(ms); 1116 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1117 1118 assert(cpu_index < possible_cpus->len); 1119 return possible_cpus->cpus[cpu_index].props; 1120 } 1121 1122 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1123 { 1124 int64_t nidx = 0; 1125 1126 if (ms->numa_state->num_nodes) { 1127 nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes); 1128 if (ms->numa_state->num_nodes <= nidx) { 1129 nidx = ms->numa_state->num_nodes - 1; 1130 } 1131 } 1132 return nidx; 1133 } 1134 1135 static void loongarch_class_init(ObjectClass *oc, void *data) 1136 { 1137 MachineClass *mc = MACHINE_CLASS(oc); 1138 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1139 1140 mc->desc = "Loongson-3A5000 LS7A1000 machine"; 1141 mc->init = loongarch_init; 1142 mc->default_ram_size = 1 * GiB; 1143 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); 1144 mc->default_ram_id = "loongarch.ram"; 1145 mc->max_cpus = LOONGARCH_MAX_CPUS; 1146 mc->is_default = 1; 1147 mc->default_kernel_irqchip_split = false; 1148 mc->block_default_type = IF_VIRTIO; 1149 mc->default_boot_order = "c"; 1150 mc->no_cdrom = 1; 1151 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1152 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1153 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1154 mc->numa_mem_supported = true; 1155 mc->auto_enable_numa_with_memhp = true; 1156 mc->auto_enable_numa_with_memdev = true; 1157 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1158 mc->default_nic = "virtio-net-pci"; 1159 hc->plug = loongarch_machine_device_plug_cb; 1160 hc->pre_plug = virt_machine_device_pre_plug; 1161 hc->unplug_request = virt_machine_device_unplug_request; 1162 hc->unplug = virt_machine_device_unplug; 1163 1164 object_class_property_add(oc, "acpi", "OnOffAuto", 1165 loongarch_get_acpi, loongarch_set_acpi, 1166 NULL, NULL); 1167 object_class_property_set_description(oc, "acpi", 1168 "Enable ACPI"); 1169 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1170 #ifdef CONFIG_TPM 1171 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1172 #endif 1173 } 1174 1175 static const TypeInfo loongarch_machine_types[] = { 1176 { 1177 .name = TYPE_LOONGARCH_MACHINE, 1178 .parent = TYPE_MACHINE, 1179 .instance_size = sizeof(LoongArchMachineState), 1180 .class_init = loongarch_class_init, 1181 .instance_init = loongarch_machine_initfn, 1182 .interfaces = (InterfaceInfo[]) { 1183 { TYPE_HOTPLUG_HANDLER }, 1184 { } 1185 }, 1186 } 1187 }; 1188 1189 DEFINE_TYPES(loongarch_machine_types) 1190