1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU loongson 3a5000 develop board emulation 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 #include "qemu/osdep.h" 8 #include "qemu/units.h" 9 #include "qemu/datadir.h" 10 #include "qapi/error.h" 11 #include "hw/boards.h" 12 #include "hw/char/serial.h" 13 #include "sysemu/kvm.h" 14 #include "sysemu/sysemu.h" 15 #include "sysemu/qtest.h" 16 #include "sysemu/runstate.h" 17 #include "sysemu/reset.h" 18 #include "sysemu/rtc.h" 19 #include "hw/loongarch/virt.h" 20 #include "exec/address-spaces.h" 21 #include "hw/irq.h" 22 #include "net/net.h" 23 #include "hw/loader.h" 24 #include "elf.h" 25 #include "hw/intc/loongson_ipi.h" 26 #include "hw/intc/loongarch_extioi.h" 27 #include "hw/intc/loongarch_pch_pic.h" 28 #include "hw/intc/loongarch_pch_msi.h" 29 #include "hw/pci-host/ls7a.h" 30 #include "hw/pci-host/gpex.h" 31 #include "hw/misc/unimp.h" 32 #include "hw/loongarch/fw_cfg.h" 33 #include "target/loongarch/cpu.h" 34 #include "hw/firmware/smbios.h" 35 #include "hw/acpi/aml-build.h" 36 #include "qapi/qapi-visit-common.h" 37 #include "hw/acpi/generic_event_device.h" 38 #include "hw/mem/nvdimm.h" 39 #include "sysemu/device_tree.h" 40 #include <libfdt.h> 41 #include "hw/core/sysbus-fdt.h" 42 #include "hw/platform-bus.h" 43 #include "hw/display/ramfb.h" 44 #include "hw/mem/pc-dimm.h" 45 #include "sysemu/tpm.h" 46 #include "sysemu/block-backend.h" 47 #include "hw/block/flash.h" 48 #include "qemu/error-report.h" 49 50 static PFlashCFI01 *virt_flash_create1(LoongArchVirtMachineState *lvms, 51 const char *name, 52 const char *alias_prop_name) 53 { 54 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 55 56 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 57 qdev_prop_set_uint8(dev, "width", 4); 58 qdev_prop_set_uint8(dev, "device-width", 2); 59 qdev_prop_set_bit(dev, "big-endian", false); 60 qdev_prop_set_uint16(dev, "id0", 0x89); 61 qdev_prop_set_uint16(dev, "id1", 0x18); 62 qdev_prop_set_uint16(dev, "id2", 0x00); 63 qdev_prop_set_uint16(dev, "id3", 0x00); 64 qdev_prop_set_string(dev, "name", name); 65 object_property_add_child(OBJECT(lvms), name, OBJECT(dev)); 66 object_property_add_alias(OBJECT(lvms), alias_prop_name, 67 OBJECT(dev), "drive"); 68 return PFLASH_CFI01(dev); 69 } 70 71 static void virt_flash_create(LoongArchVirtMachineState *lvms) 72 { 73 lvms->flash[0] = virt_flash_create1(lvms, "virt.flash0", "pflash0"); 74 lvms->flash[1] = virt_flash_create1(lvms, "virt.flash1", "pflash1"); 75 } 76 77 static void virt_flash_map1(PFlashCFI01 *flash, 78 hwaddr base, hwaddr size, 79 MemoryRegion *sysmem) 80 { 81 DeviceState *dev = DEVICE(flash); 82 BlockBackend *blk; 83 hwaddr real_size = size; 84 85 blk = pflash_cfi01_get_blk(flash); 86 if (blk) { 87 real_size = blk_getlength(blk); 88 assert(real_size && real_size <= size); 89 } 90 91 assert(QEMU_IS_ALIGNED(real_size, VIRT_FLASH_SECTOR_SIZE)); 92 assert(real_size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 93 94 qdev_prop_set_uint32(dev, "num-blocks", real_size / VIRT_FLASH_SECTOR_SIZE); 95 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 96 memory_region_add_subregion(sysmem, base, 97 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 98 } 99 100 static void virt_flash_map(LoongArchVirtMachineState *lvms, 101 MemoryRegion *sysmem) 102 { 103 PFlashCFI01 *flash0 = lvms->flash[0]; 104 PFlashCFI01 *flash1 = lvms->flash[1]; 105 106 virt_flash_map1(flash0, VIRT_FLASH0_BASE, VIRT_FLASH0_SIZE, sysmem); 107 virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem); 108 } 109 110 static void fdt_add_cpuic_node(LoongArchVirtMachineState *lvms, 111 uint32_t *cpuintc_phandle) 112 { 113 MachineState *ms = MACHINE(lvms); 114 char *nodename; 115 116 *cpuintc_phandle = qemu_fdt_alloc_phandle(ms->fdt); 117 nodename = g_strdup_printf("/cpuic"); 118 qemu_fdt_add_subnode(ms->fdt, nodename); 119 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *cpuintc_phandle); 120 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 121 "loongson,cpu-interrupt-controller"); 122 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 123 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 124 g_free(nodename); 125 } 126 127 static void fdt_add_eiointc_node(LoongArchVirtMachineState *lvms, 128 uint32_t *cpuintc_phandle, 129 uint32_t *eiointc_phandle) 130 { 131 MachineState *ms = MACHINE(lvms); 132 char *nodename; 133 hwaddr extioi_base = APIC_BASE; 134 hwaddr extioi_size = EXTIOI_SIZE; 135 136 *eiointc_phandle = qemu_fdt_alloc_phandle(ms->fdt); 137 nodename = g_strdup_printf("/eiointc@%" PRIx64, extioi_base); 138 qemu_fdt_add_subnode(ms->fdt, nodename); 139 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *eiointc_phandle); 140 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 141 "loongson,ls2k2000-eiointc"); 142 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 143 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 1); 144 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 145 *cpuintc_phandle); 146 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupts", 3); 147 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, 148 extioi_base, 0x0, extioi_size); 149 g_free(nodename); 150 } 151 152 static void fdt_add_pch_pic_node(LoongArchVirtMachineState *lvms, 153 uint32_t *eiointc_phandle, 154 uint32_t *pch_pic_phandle) 155 { 156 MachineState *ms = MACHINE(lvms); 157 char *nodename; 158 hwaddr pch_pic_base = VIRT_PCH_REG_BASE; 159 hwaddr pch_pic_size = VIRT_PCH_REG_SIZE; 160 161 *pch_pic_phandle = qemu_fdt_alloc_phandle(ms->fdt); 162 nodename = g_strdup_printf("/platic@%" PRIx64, pch_pic_base); 163 qemu_fdt_add_subnode(ms->fdt, nodename); 164 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_pic_phandle); 165 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 166 "loongson,pch-pic-1.0"); 167 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, 168 pch_pic_base, 0, pch_pic_size); 169 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 170 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 2); 171 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 172 *eiointc_phandle); 173 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,pic-base-vec", 0); 174 g_free(nodename); 175 } 176 177 static void fdt_add_pch_msi_node(LoongArchVirtMachineState *lvms, 178 uint32_t *eiointc_phandle, 179 uint32_t *pch_msi_phandle) 180 { 181 MachineState *ms = MACHINE(lvms); 182 char *nodename; 183 hwaddr pch_msi_base = VIRT_PCH_MSI_ADDR_LOW; 184 hwaddr pch_msi_size = VIRT_PCH_MSI_SIZE; 185 186 *pch_msi_phandle = qemu_fdt_alloc_phandle(ms->fdt); 187 nodename = g_strdup_printf("/msi@%" PRIx64, pch_msi_base); 188 qemu_fdt_add_subnode(ms->fdt, nodename); 189 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", *pch_msi_phandle); 190 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 191 "loongson,pch-msi-1.0"); 192 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 193 0, pch_msi_base, 194 0, pch_msi_size); 195 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 196 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 197 *eiointc_phandle); 198 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-base-vec", 199 VIRT_PCH_PIC_IRQ_NUM); 200 qemu_fdt_setprop_cell(ms->fdt, nodename, "loongson,msi-num-vecs", 201 EXTIOI_IRQS - VIRT_PCH_PIC_IRQ_NUM); 202 g_free(nodename); 203 } 204 205 static void fdt_add_flash_node(LoongArchVirtMachineState *lvms) 206 { 207 MachineState *ms = MACHINE(lvms); 208 char *nodename; 209 MemoryRegion *flash_mem; 210 211 hwaddr flash0_base; 212 hwaddr flash0_size; 213 214 hwaddr flash1_base; 215 hwaddr flash1_size; 216 217 flash_mem = pflash_cfi01_get_memory(lvms->flash[0]); 218 flash0_base = flash_mem->addr; 219 flash0_size = memory_region_size(flash_mem); 220 221 flash_mem = pflash_cfi01_get_memory(lvms->flash[1]); 222 flash1_base = flash_mem->addr; 223 flash1_size = memory_region_size(flash_mem); 224 225 nodename = g_strdup_printf("/flash@%" PRIx64, flash0_base); 226 qemu_fdt_add_subnode(ms->fdt, nodename); 227 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 228 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 229 2, flash0_base, 2, flash0_size, 230 2, flash1_base, 2, flash1_size); 231 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 232 g_free(nodename); 233 } 234 235 static void fdt_add_rtc_node(LoongArchVirtMachineState *lvms, 236 uint32_t *pch_pic_phandle) 237 { 238 char *nodename; 239 hwaddr base = VIRT_RTC_REG_BASE; 240 hwaddr size = VIRT_RTC_LEN; 241 MachineState *ms = MACHINE(lvms); 242 243 nodename = g_strdup_printf("/rtc@%" PRIx64, base); 244 qemu_fdt_add_subnode(ms->fdt, nodename); 245 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 246 "loongson,ls7a-rtc"); 247 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 248 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 249 VIRT_RTC_IRQ - VIRT_GSI_BASE , 0x4); 250 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 251 *pch_pic_phandle); 252 g_free(nodename); 253 } 254 255 static void fdt_add_uart_node(LoongArchVirtMachineState *lvms, 256 uint32_t *pch_pic_phandle) 257 { 258 char *nodename; 259 hwaddr base = VIRT_UART_BASE; 260 hwaddr size = VIRT_UART_SIZE; 261 MachineState *ms = MACHINE(lvms); 262 263 nodename = g_strdup_printf("/serial@%" PRIx64, base); 264 qemu_fdt_add_subnode(ms->fdt, nodename); 265 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a"); 266 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size); 267 qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000); 268 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 269 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts", 270 VIRT_UART_IRQ - VIRT_GSI_BASE, 0x4); 271 qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent", 272 *pch_pic_phandle); 273 g_free(nodename); 274 } 275 276 static void create_fdt(LoongArchVirtMachineState *lvms) 277 { 278 MachineState *ms = MACHINE(lvms); 279 280 ms->fdt = create_device_tree(&lvms->fdt_size); 281 if (!ms->fdt) { 282 error_report("create_device_tree() failed"); 283 exit(1); 284 } 285 286 /* Header */ 287 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", 288 "linux,dummy-loongson3"); 289 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 290 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 291 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 292 } 293 294 static void fdt_add_cpu_nodes(const LoongArchVirtMachineState *lvms) 295 { 296 int num; 297 const MachineState *ms = MACHINE(lvms); 298 int smp_cpus = ms->smp.cpus; 299 300 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 301 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 302 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 303 304 /* cpu nodes */ 305 for (num = smp_cpus - 1; num >= 0; num--) { 306 char *nodename = g_strdup_printf("/cpus/cpu@%d", num); 307 LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num)); 308 CPUState *cs = CPU(cpu); 309 310 qemu_fdt_add_subnode(ms->fdt, nodename); 311 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 312 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 313 cpu->dtb_compatible); 314 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 315 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 316 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 317 } 318 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); 319 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 320 qemu_fdt_alloc_phandle(ms->fdt)); 321 g_free(nodename); 322 } 323 324 /*cpu map */ 325 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 326 327 for (num = smp_cpus - 1; num >= 0; num--) { 328 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num); 329 char *map_path; 330 331 if (ms->smp.threads > 1) { 332 map_path = g_strdup_printf( 333 "/cpus/cpu-map/socket%d/core%d/thread%d", 334 num / (ms->smp.cores * ms->smp.threads), 335 (num / ms->smp.threads) % ms->smp.cores, 336 num % ms->smp.threads); 337 } else { 338 map_path = g_strdup_printf( 339 "/cpus/cpu-map/socket%d/core%d", 340 num / ms->smp.cores, 341 num % ms->smp.cores); 342 } 343 qemu_fdt_add_path(ms->fdt, map_path); 344 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 345 346 g_free(map_path); 347 g_free(cpu_path); 348 } 349 } 350 351 static void fdt_add_fw_cfg_node(const LoongArchVirtMachineState *lvms) 352 { 353 char *nodename; 354 hwaddr base = VIRT_FWCFG_BASE; 355 const MachineState *ms = MACHINE(lvms); 356 357 nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base); 358 qemu_fdt_add_subnode(ms->fdt, nodename); 359 qemu_fdt_setprop_string(ms->fdt, nodename, 360 "compatible", "qemu,fw-cfg-mmio"); 361 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 362 2, base, 2, 0x18); 363 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 364 g_free(nodename); 365 } 366 367 static void fdt_add_pcie_irq_map_node(const LoongArchVirtMachineState *lvms, 368 char *nodename, 369 uint32_t *pch_pic_phandle) 370 { 371 int pin, dev; 372 uint32_t irq_map_stride = 0; 373 uint32_t full_irq_map[GPEX_NUM_IRQS *GPEX_NUM_IRQS * 10] = {}; 374 uint32_t *irq_map = full_irq_map; 375 const MachineState *ms = MACHINE(lvms); 376 377 /* This code creates a standard swizzle of interrupts such that 378 * each device's first interrupt is based on it's PCI_SLOT number. 379 * (See pci_swizzle_map_irq_fn()) 380 * 381 * We only need one entry per interrupt in the table (not one per 382 * possible slot) seeing the interrupt-map-mask will allow the table 383 * to wrap to any number of devices. 384 */ 385 386 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 387 int devfn = dev * 0x8; 388 389 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 390 int irq_nr = 16 + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 391 int i = 0; 392 393 /* Fill PCI address cells */ 394 irq_map[i] = cpu_to_be32(devfn << 8); 395 i += 3; 396 397 /* Fill PCI Interrupt cells */ 398 irq_map[i] = cpu_to_be32(pin + 1); 399 i += 1; 400 401 /* Fill interrupt controller phandle and cells */ 402 irq_map[i++] = cpu_to_be32(*pch_pic_phandle); 403 irq_map[i++] = cpu_to_be32(irq_nr); 404 405 if (!irq_map_stride) { 406 irq_map_stride = i; 407 } 408 irq_map += irq_map_stride; 409 } 410 } 411 412 413 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-map", full_irq_map, 414 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 415 irq_map_stride * sizeof(uint32_t)); 416 qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupt-map-mask", 417 0x1800, 0, 0, 0x7); 418 } 419 420 static void fdt_add_pcie_node(const LoongArchVirtMachineState *lvms, 421 uint32_t *pch_pic_phandle, 422 uint32_t *pch_msi_phandle) 423 { 424 char *nodename; 425 hwaddr base_mmio = VIRT_PCI_MEM_BASE; 426 hwaddr size_mmio = VIRT_PCI_MEM_SIZE; 427 hwaddr base_pio = VIRT_PCI_IO_BASE; 428 hwaddr size_pio = VIRT_PCI_IO_SIZE; 429 hwaddr base_pcie = VIRT_PCI_CFG_BASE; 430 hwaddr size_pcie = VIRT_PCI_CFG_SIZE; 431 hwaddr base = base_pcie; 432 433 const MachineState *ms = MACHINE(lvms); 434 435 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 436 qemu_fdt_add_subnode(ms->fdt, nodename); 437 qemu_fdt_setprop_string(ms->fdt, nodename, 438 "compatible", "pci-host-ecam-generic"); 439 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 440 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 441 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 442 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 443 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 444 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); 445 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 446 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 447 2, base_pcie, 2, size_pcie); 448 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 449 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, 450 2, base_pio, 2, size_pio, 451 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 452 2, base_mmio, 2, size_mmio); 453 qemu_fdt_setprop_cells(ms->fdt, nodename, "msi-map", 454 0, *pch_msi_phandle, 0, 0x10000); 455 456 fdt_add_pcie_irq_map_node(lvms, nodename, pch_pic_phandle); 457 458 g_free(nodename); 459 } 460 461 static void fdt_add_memory_node(MachineState *ms, 462 uint64_t base, uint64_t size, int node_id) 463 { 464 char *nodename = g_strdup_printf("/memory@%" PRIx64, base); 465 466 qemu_fdt_add_subnode(ms->fdt, nodename); 467 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", base >> 32, base, 468 size >> 32, size); 469 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 470 471 if (ms->numa_state && ms->numa_state->num_nodes) { 472 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id); 473 } 474 475 g_free(nodename); 476 } 477 478 static void fdt_add_memory_nodes(MachineState *ms) 479 { 480 hwaddr base, size, ram_size, gap; 481 int i, nb_numa_nodes, nodes; 482 NodeInfo *numa_info; 483 484 ram_size = ms->ram_size; 485 base = VIRT_LOWMEM_BASE; 486 gap = VIRT_LOWMEM_SIZE; 487 nodes = nb_numa_nodes = ms->numa_state->num_nodes; 488 numa_info = ms->numa_state->nodes; 489 if (!nodes) { 490 nodes = 1; 491 } 492 493 for (i = 0; i < nodes; i++) { 494 if (nb_numa_nodes) { 495 size = numa_info[i].node_mem; 496 } else { 497 size = ram_size; 498 } 499 500 /* 501 * memory for the node splited into two part 502 * lowram: [base, +gap) 503 * highram: [VIRT_HIGHMEM_BASE, +(len - gap)) 504 */ 505 if (size >= gap) { 506 fdt_add_memory_node(ms, base, gap, i); 507 size -= gap; 508 base = VIRT_HIGHMEM_BASE; 509 gap = ram_size - VIRT_LOWMEM_SIZE; 510 } 511 512 if (size) { 513 fdt_add_memory_node(ms, base, size, i); 514 base += size; 515 gap -= size; 516 } 517 } 518 } 519 520 static void virt_build_smbios(LoongArchVirtMachineState *lvms) 521 { 522 MachineState *ms = MACHINE(lvms); 523 MachineClass *mc = MACHINE_GET_CLASS(lvms); 524 uint8_t *smbios_tables, *smbios_anchor; 525 size_t smbios_tables_len, smbios_anchor_len; 526 const char *product = "QEMU Virtual Machine"; 527 528 if (!lvms->fw_cfg) { 529 return; 530 } 531 532 smbios_set_defaults("QEMU", product, mc->name, true); 533 534 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 535 NULL, 0, 536 &smbios_tables, &smbios_tables_len, 537 &smbios_anchor, &smbios_anchor_len, &error_fatal); 538 539 if (smbios_anchor) { 540 fw_cfg_add_file(lvms->fw_cfg, "etc/smbios/smbios-tables", 541 smbios_tables, smbios_tables_len); 542 fw_cfg_add_file(lvms->fw_cfg, "etc/smbios/smbios-anchor", 543 smbios_anchor, smbios_anchor_len); 544 } 545 } 546 547 static void virt_done(Notifier *notifier, void *data) 548 { 549 LoongArchVirtMachineState *lvms = container_of(notifier, 550 LoongArchVirtMachineState, machine_done); 551 virt_build_smbios(lvms); 552 loongarch_acpi_setup(lvms); 553 } 554 555 static void virt_powerdown_req(Notifier *notifier, void *opaque) 556 { 557 LoongArchVirtMachineState *s; 558 559 s = container_of(notifier, LoongArchVirtMachineState, powerdown_notifier); 560 acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS); 561 } 562 563 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) 564 { 565 /* Ensure there are no duplicate entries. */ 566 for (unsigned i = 0; i < memmap_entries; i++) { 567 assert(memmap_table[i].address != address); 568 } 569 570 memmap_table = g_renew(struct memmap_entry, memmap_table, 571 memmap_entries + 1); 572 memmap_table[memmap_entries].address = cpu_to_le64(address); 573 memmap_table[memmap_entries].length = cpu_to_le64(length); 574 memmap_table[memmap_entries].type = cpu_to_le32(type); 575 memmap_table[memmap_entries].reserved = 0; 576 memmap_entries++; 577 } 578 579 static DeviceState *create_acpi_ged(DeviceState *pch_pic, 580 LoongArchVirtMachineState *lvms) 581 { 582 DeviceState *dev; 583 MachineState *ms = MACHINE(lvms); 584 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 585 586 if (ms->ram_slots) { 587 event |= ACPI_GED_MEM_HOTPLUG_EVT; 588 } 589 dev = qdev_new(TYPE_ACPI_GED); 590 qdev_prop_set_uint32(dev, "ged-event", event); 591 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 592 593 /* ged event */ 594 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); 595 /* memory hotplug */ 596 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); 597 /* ged regs used for reset and power down */ 598 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); 599 600 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 601 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE)); 602 return dev; 603 } 604 605 static DeviceState *create_platform_bus(DeviceState *pch_pic) 606 { 607 DeviceState *dev; 608 SysBusDevice *sysbus; 609 int i, irq; 610 MemoryRegion *sysmem = get_system_memory(); 611 612 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 613 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 614 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 615 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); 616 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 617 618 sysbus = SYS_BUS_DEVICE(dev); 619 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 620 irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i; 621 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); 622 } 623 624 memory_region_add_subregion(sysmem, 625 VIRT_PLATFORM_BUS_BASEADDRESS, 626 sysbus_mmio_get_region(sysbus, 0)); 627 return dev; 628 } 629 630 static void virt_devices_init(DeviceState *pch_pic, 631 LoongArchVirtMachineState *lvms, 632 uint32_t *pch_pic_phandle, 633 uint32_t *pch_msi_phandle) 634 { 635 MachineClass *mc = MACHINE_GET_CLASS(lvms); 636 DeviceState *gpex_dev; 637 SysBusDevice *d; 638 PCIBus *pci_bus; 639 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; 640 MemoryRegion *mmio_alias, *mmio_reg; 641 int i; 642 643 gpex_dev = qdev_new(TYPE_GPEX_HOST); 644 d = SYS_BUS_DEVICE(gpex_dev); 645 sysbus_realize_and_unref(d, &error_fatal); 646 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; 647 lvms->pci_bus = pci_bus; 648 649 /* Map only part size_ecam bytes of ECAM space */ 650 ecam_alias = g_new0(MemoryRegion, 1); 651 ecam_reg = sysbus_mmio_get_region(d, 0); 652 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", 653 ecam_reg, 0, VIRT_PCI_CFG_SIZE); 654 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, 655 ecam_alias); 656 657 /* Map PCI mem space */ 658 mmio_alias = g_new0(MemoryRegion, 1); 659 mmio_reg = sysbus_mmio_get_region(d, 1); 660 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", 661 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); 662 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, 663 mmio_alias); 664 665 /* Map PCI IO port space. */ 666 pio_alias = g_new0(MemoryRegion, 1); 667 pio_reg = sysbus_mmio_get_region(d, 2); 668 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, 669 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); 670 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, 671 pio_alias); 672 673 for (i = 0; i < GPEX_NUM_IRQS; i++) { 674 sysbus_connect_irq(d, i, 675 qdev_get_gpio_in(pch_pic, 16 + i)); 676 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); 677 } 678 679 /* Add pcie node */ 680 fdt_add_pcie_node(lvms, pch_pic_phandle, pch_msi_phandle); 681 682 serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, 683 qdev_get_gpio_in(pch_pic, 684 VIRT_UART_IRQ - VIRT_GSI_BASE), 685 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 686 fdt_add_uart_node(lvms, pch_pic_phandle); 687 688 /* Network init */ 689 pci_init_nic_devices(pci_bus, mc->default_nic); 690 691 /* 692 * There are some invalid guest memory access. 693 * Create some unimplemented devices to emulate this. 694 */ 695 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); 696 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, 697 qdev_get_gpio_in(pch_pic, 698 VIRT_RTC_IRQ - VIRT_GSI_BASE)); 699 fdt_add_rtc_node(lvms, pch_pic_phandle); 700 701 /* acpi ged */ 702 lvms->acpi_ged = create_acpi_ged(pch_pic, lvms); 703 /* platform bus */ 704 lvms->platform_bus_dev = create_platform_bus(pch_pic); 705 } 706 707 static void virt_irq_init(LoongArchVirtMachineState *lvms) 708 { 709 MachineState *ms = MACHINE(lvms); 710 DeviceState *pch_pic, *pch_msi, *cpudev; 711 DeviceState *ipi, *extioi; 712 SysBusDevice *d; 713 LoongArchCPU *lacpu; 714 CPULoongArchState *env; 715 CPUState *cpu_state; 716 int cpu, pin, i, start, num; 717 uint32_t cpuintc_phandle, eiointc_phandle, pch_pic_phandle, pch_msi_phandle; 718 719 /* 720 * The connection of interrupts: 721 * +-----+ +---------+ +-------+ 722 * | IPI |--> | CPUINTC | <-- | Timer | 723 * +-----+ +---------+ +-------+ 724 * ^ 725 * | 726 * +---------+ 727 * | EIOINTC | 728 * +---------+ 729 * ^ ^ 730 * | | 731 * +---------+ +---------+ 732 * | PCH-PIC | | PCH-MSI | 733 * +---------+ +---------+ 734 * ^ ^ ^ 735 * | | | 736 * +--------+ +---------+ +---------+ 737 * | UARTs | | Devices | | Devices | 738 * +--------+ +---------+ +---------+ 739 */ 740 741 /* Create IPI device */ 742 ipi = qdev_new(TYPE_LOONGSON_IPI); 743 qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); 744 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 745 746 /* IPI iocsr memory region */ 747 memory_region_add_subregion(&lvms->system_iocsr, SMP_IPI_MAILBOX, 748 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); 749 memory_region_add_subregion(&lvms->system_iocsr, MAIL_SEND_ADDR, 750 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); 751 752 /* Add cpu interrupt-controller */ 753 fdt_add_cpuic_node(lvms, &cpuintc_phandle); 754 755 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 756 cpu_state = qemu_get_cpu(cpu); 757 cpudev = DEVICE(cpu_state); 758 lacpu = LOONGARCH_CPU(cpu_state); 759 env = &(lacpu->env); 760 env->address_space_iocsr = &lvms->as_iocsr; 761 762 /* connect ipi irq to cpu irq */ 763 qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI)); 764 env->ipistate = ipi; 765 } 766 767 /* Create EXTIOI device */ 768 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); 769 qdev_prop_set_uint32(extioi, "num-cpu", ms->smp.cpus); 770 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); 771 memory_region_add_subregion(&lvms->system_iocsr, APIC_BASE, 772 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0)); 773 774 /* 775 * connect ext irq to the cpu irq 776 * cpu_pin[9:2] <= intc_pin[7:0] 777 */ 778 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 779 cpudev = DEVICE(qemu_get_cpu(cpu)); 780 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 781 qdev_connect_gpio_out(extioi, (cpu * 8 + pin), 782 qdev_get_gpio_in(cpudev, pin + 2)); 783 } 784 } 785 786 /* Add Extend I/O Interrupt Controller node */ 787 fdt_add_eiointc_node(lvms, &cpuintc_phandle, &eiointc_phandle); 788 789 pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); 790 num = VIRT_PCH_PIC_IRQ_NUM; 791 qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); 792 d = SYS_BUS_DEVICE(pch_pic); 793 sysbus_realize_and_unref(d, &error_fatal); 794 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, 795 sysbus_mmio_get_region(d, 0)); 796 memory_region_add_subregion(get_system_memory(), 797 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, 798 sysbus_mmio_get_region(d, 1)); 799 memory_region_add_subregion(get_system_memory(), 800 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, 801 sysbus_mmio_get_region(d, 2)); 802 803 /* Connect pch_pic irqs to extioi */ 804 for (i = 0; i < num; i++) { 805 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); 806 } 807 808 /* Add PCH PIC node */ 809 fdt_add_pch_pic_node(lvms, &eiointc_phandle, &pch_pic_phandle); 810 811 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); 812 start = num; 813 num = EXTIOI_IRQS - start; 814 qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); 815 qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); 816 d = SYS_BUS_DEVICE(pch_msi); 817 sysbus_realize_and_unref(d, &error_fatal); 818 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); 819 for (i = 0; i < num; i++) { 820 /* Connect pch_msi irqs to extioi */ 821 qdev_connect_gpio_out(DEVICE(d), i, 822 qdev_get_gpio_in(extioi, i + start)); 823 } 824 825 /* Add PCH MSI node */ 826 fdt_add_pch_msi_node(lvms, &eiointc_phandle, &pch_msi_phandle); 827 828 virt_devices_init(pch_pic, lvms, &pch_pic_phandle, &pch_msi_phandle); 829 } 830 831 static void virt_firmware_init(LoongArchVirtMachineState *lvms) 832 { 833 char *filename = MACHINE(lvms)->firmware; 834 char *bios_name = NULL; 835 int bios_size, i; 836 BlockBackend *pflash_blk0; 837 MemoryRegion *mr; 838 839 lvms->bios_loaded = false; 840 841 /* Map legacy -drive if=pflash to machine properties */ 842 for (i = 0; i < ARRAY_SIZE(lvms->flash); i++) { 843 pflash_cfi01_legacy_drive(lvms->flash[i], 844 drive_get(IF_PFLASH, 0, i)); 845 } 846 847 virt_flash_map(lvms, get_system_memory()); 848 849 pflash_blk0 = pflash_cfi01_get_blk(lvms->flash[0]); 850 851 if (pflash_blk0) { 852 if (filename) { 853 error_report("cannot use both '-bios' and '-drive if=pflash'" 854 "options at once"); 855 exit(1); 856 } 857 lvms->bios_loaded = true; 858 return; 859 } 860 861 if (filename) { 862 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); 863 if (!bios_name) { 864 error_report("Could not find ROM image '%s'", filename); 865 exit(1); 866 } 867 868 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(lvms->flash[0]), 0); 869 bios_size = load_image_mr(bios_name, mr); 870 if (bios_size < 0) { 871 error_report("Could not load ROM image '%s'", bios_name); 872 exit(1); 873 } 874 g_free(bios_name); 875 lvms->bios_loaded = true; 876 } 877 } 878 879 880 static void virt_iocsr_misc_write(void *opaque, hwaddr addr, 881 uint64_t val, unsigned size) 882 { 883 } 884 885 static uint64_t virt_iocsr_misc_read(void *opaque, hwaddr addr, unsigned size) 886 { 887 uint64_t ret; 888 889 switch (addr) { 890 case VERSION_REG: 891 return 0x11ULL; 892 case FEATURE_REG: 893 ret = BIT(IOCSRF_MSI) | BIT(IOCSRF_EXTIOI) | BIT(IOCSRF_CSRIPI); 894 if (kvm_enabled()) { 895 ret |= BIT(IOCSRF_VM); 896 } 897 return ret; 898 case VENDOR_REG: 899 return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 900 case CPUNAME_REG: 901 return 0x303030354133ULL; /* "3A5000" */ 902 case MISC_FUNC_REG: 903 return BIT_ULL(IOCSRM_EXTIOI_EN); 904 } 905 return 0ULL; 906 } 907 908 static const MemoryRegionOps virt_iocsr_misc_ops = { 909 .read = virt_iocsr_misc_read, 910 .write = virt_iocsr_misc_write, 911 .endianness = DEVICE_LITTLE_ENDIAN, 912 .valid = { 913 .min_access_size = 4, 914 .max_access_size = 8, 915 }, 916 .impl = { 917 .min_access_size = 8, 918 .max_access_size = 8, 919 }, 920 }; 921 922 static void fw_cfg_add_memory(MachineState *ms) 923 { 924 hwaddr base, size, ram_size, gap; 925 int nb_numa_nodes, nodes; 926 NodeInfo *numa_info; 927 928 ram_size = ms->ram_size; 929 base = VIRT_LOWMEM_BASE; 930 gap = VIRT_LOWMEM_SIZE; 931 nodes = nb_numa_nodes = ms->numa_state->num_nodes; 932 numa_info = ms->numa_state->nodes; 933 if (!nodes) { 934 nodes = 1; 935 } 936 937 /* add fw_cfg memory map of node0 */ 938 if (nb_numa_nodes) { 939 size = numa_info[0].node_mem; 940 } else { 941 size = ram_size; 942 } 943 944 if (size >= gap) { 945 memmap_add_entry(base, gap, 1); 946 size -= gap; 947 base = VIRT_HIGHMEM_BASE; 948 gap = ram_size - VIRT_LOWMEM_SIZE; 949 } 950 951 if (size) { 952 memmap_add_entry(base, size, 1); 953 base += size; 954 } 955 956 if (nodes < 2) { 957 return; 958 } 959 960 /* add fw_cfg memory map of other nodes */ 961 size = ram_size - numa_info[0].node_mem; 962 gap = VIRT_LOWMEM_BASE + VIRT_LOWMEM_SIZE; 963 if (base < gap && (base + size) > gap) { 964 /* 965 * memory map for the maining nodes splited into two part 966 * lowram: [base, +(gap - base)) 967 * highram: [VIRT_HIGHMEM_BASE, +(size - (gap - base))) 968 */ 969 memmap_add_entry(base, gap - base, 1); 970 size -= gap - base; 971 base = VIRT_HIGHMEM_BASE; 972 } 973 974 if (size) 975 memmap_add_entry(base, size, 1); 976 } 977 978 static void virt_init(MachineState *machine) 979 { 980 LoongArchCPU *lacpu; 981 const char *cpu_model = machine->cpu_type; 982 MemoryRegion *address_space_mem = get_system_memory(); 983 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(machine); 984 int i; 985 hwaddr base, size, ram_size = machine->ram_size; 986 const CPUArchIdList *possible_cpus; 987 MachineClass *mc = MACHINE_GET_CLASS(machine); 988 CPUState *cpu; 989 990 if (!cpu_model) { 991 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); 992 } 993 994 create_fdt(lvms); 995 996 /* Create IOCSR space */ 997 memory_region_init_io(&lvms->system_iocsr, OBJECT(machine), NULL, 998 machine, "iocsr", UINT64_MAX); 999 address_space_init(&lvms->as_iocsr, &lvms->system_iocsr, "IOCSR"); 1000 memory_region_init_io(&lvms->iocsr_mem, OBJECT(machine), 1001 &virt_iocsr_misc_ops, 1002 machine, "iocsr_misc", 0x428); 1003 memory_region_add_subregion(&lvms->system_iocsr, 0, &lvms->iocsr_mem); 1004 1005 /* Init CPUs */ 1006 possible_cpus = mc->possible_cpu_arch_ids(machine); 1007 for (i = 0; i < possible_cpus->len; i++) { 1008 cpu = cpu_create(machine->cpu_type); 1009 cpu->cpu_index = i; 1010 machine->possible_cpus->cpus[i].cpu = cpu; 1011 lacpu = LOONGARCH_CPU(cpu); 1012 lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id; 1013 } 1014 fdt_add_cpu_nodes(lvms); 1015 fdt_add_memory_nodes(machine); 1016 fw_cfg_add_memory(machine); 1017 1018 /* Node0 memory */ 1019 size = ram_size; 1020 base = VIRT_LOWMEM_BASE; 1021 if (size > VIRT_LOWMEM_SIZE) { 1022 size = VIRT_LOWMEM_SIZE; 1023 } 1024 1025 memory_region_init_alias(&lvms->lowmem, NULL, "loongarch.lowram", 1026 machine->ram, base, size); 1027 memory_region_add_subregion(address_space_mem, base, &lvms->lowmem); 1028 base += size; 1029 if (ram_size - size) { 1030 base = VIRT_HIGHMEM_BASE; 1031 memory_region_init_alias(&lvms->highmem, NULL, "loongarch.highram", 1032 machine->ram, VIRT_LOWMEM_BASE + size, ram_size - size); 1033 memory_region_add_subregion(address_space_mem, base, &lvms->highmem); 1034 base += ram_size - size; 1035 } 1036 1037 /* initialize device memory address space */ 1038 if (machine->ram_size < machine->maxram_size) { 1039 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 1040 1041 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 1042 error_report("unsupported amount of memory slots: %"PRIu64, 1043 machine->ram_slots); 1044 exit(EXIT_FAILURE); 1045 } 1046 1047 if (QEMU_ALIGN_UP(machine->maxram_size, 1048 TARGET_PAGE_SIZE) != machine->maxram_size) { 1049 error_report("maximum memory size must by aligned to multiple of " 1050 "%d bytes", TARGET_PAGE_SIZE); 1051 exit(EXIT_FAILURE); 1052 } 1053 machine_memory_devices_init(machine, base, device_mem_size); 1054 } 1055 1056 /* load the BIOS image. */ 1057 virt_firmware_init(lvms); 1058 1059 /* fw_cfg init */ 1060 lvms->fw_cfg = virt_fw_cfg_init(ram_size, machine); 1061 rom_set_fw(lvms->fw_cfg); 1062 if (lvms->fw_cfg != NULL) { 1063 fw_cfg_add_file(lvms->fw_cfg, "etc/memmap", 1064 memmap_table, 1065 sizeof(struct memmap_entry) * (memmap_entries)); 1066 } 1067 fdt_add_fw_cfg_node(lvms); 1068 fdt_add_flash_node(lvms); 1069 1070 /* Initialize the IO interrupt subsystem */ 1071 virt_irq_init(lvms); 1072 platform_bus_add_all_fdt_nodes(machine->fdt, "/platic", 1073 VIRT_PLATFORM_BUS_BASEADDRESS, 1074 VIRT_PLATFORM_BUS_SIZE, 1075 VIRT_PLATFORM_BUS_IRQ); 1076 lvms->machine_done.notify = virt_done; 1077 qemu_add_machine_init_done_notifier(&lvms->machine_done); 1078 /* connect powerdown request */ 1079 lvms->powerdown_notifier.notify = virt_powerdown_req; 1080 qemu_register_powerdown_notifier(&lvms->powerdown_notifier); 1081 1082 /* 1083 * Since lowmem region starts from 0 and Linux kernel legacy start address 1084 * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer 1085 * access. FDT size limit with 1 MiB. 1086 * Put the FDT into the memory map as a ROM image: this will ensure 1087 * the FDT is copied again upon reset, even if addr points into RAM. 1088 */ 1089 qemu_fdt_dumpdtb(machine->fdt, lvms->fdt_size); 1090 rom_add_blob_fixed_as("fdt", machine->fdt, lvms->fdt_size, FDT_BASE, 1091 &address_space_memory); 1092 qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, 1093 rom_ptr_for_as(&address_space_memory, FDT_BASE, lvms->fdt_size)); 1094 1095 lvms->bootinfo.ram_size = ram_size; 1096 loongarch_load_kernel(machine, &lvms->bootinfo); 1097 } 1098 1099 static void virt_get_acpi(Object *obj, Visitor *v, const char *name, 1100 void *opaque, Error **errp) 1101 { 1102 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 1103 OnOffAuto acpi = lvms->acpi; 1104 1105 visit_type_OnOffAuto(v, name, &acpi, errp); 1106 } 1107 1108 static void virt_set_acpi(Object *obj, Visitor *v, const char *name, 1109 void *opaque, Error **errp) 1110 { 1111 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 1112 1113 visit_type_OnOffAuto(v, name, &lvms->acpi, errp); 1114 } 1115 1116 static void virt_initfn(Object *obj) 1117 { 1118 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(obj); 1119 1120 lvms->acpi = ON_OFF_AUTO_AUTO; 1121 lvms->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1122 lvms->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1123 virt_flash_create(lvms); 1124 } 1125 1126 static bool memhp_type_supported(DeviceState *dev) 1127 { 1128 /* we only support pc dimm now */ 1129 return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && 1130 !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1131 } 1132 1133 static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1134 Error **errp) 1135 { 1136 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 1137 } 1138 1139 static void virt_device_pre_plug(HotplugHandler *hotplug_dev, 1140 DeviceState *dev, Error **errp) 1141 { 1142 if (memhp_type_supported(dev)) { 1143 virt_mem_pre_plug(hotplug_dev, dev, errp); 1144 } 1145 } 1146 1147 static void virt_mem_unplug_request(HotplugHandler *hotplug_dev, 1148 DeviceState *dev, Error **errp) 1149 { 1150 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 1151 1152 /* the acpi ged is always exist */ 1153 hotplug_handler_unplug_request(HOTPLUG_HANDLER(lvms->acpi_ged), dev, 1154 errp); 1155 } 1156 1157 static void virt_device_unplug_request(HotplugHandler *hotplug_dev, 1158 DeviceState *dev, Error **errp) 1159 { 1160 if (memhp_type_supported(dev)) { 1161 virt_mem_unplug_request(hotplug_dev, dev, errp); 1162 } 1163 } 1164 1165 static void virt_mem_unplug(HotplugHandler *hotplug_dev, 1166 DeviceState *dev, Error **errp) 1167 { 1168 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 1169 1170 hotplug_handler_unplug(HOTPLUG_HANDLER(lvms->acpi_ged), dev, errp); 1171 pc_dimm_unplug(PC_DIMM(dev), MACHINE(lvms)); 1172 qdev_unrealize(dev); 1173 } 1174 1175 static void virt_device_unplug(HotplugHandler *hotplug_dev, 1176 DeviceState *dev, Error **errp) 1177 { 1178 if (memhp_type_supported(dev)) { 1179 virt_mem_unplug(hotplug_dev, dev, errp); 1180 } 1181 } 1182 1183 static void virt_mem_plug(HotplugHandler *hotplug_dev, 1184 DeviceState *dev, Error **errp) 1185 { 1186 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 1187 1188 pc_dimm_plug(PC_DIMM(dev), MACHINE(lvms)); 1189 hotplug_handler_plug(HOTPLUG_HANDLER(lvms->acpi_ged), 1190 dev, &error_abort); 1191 } 1192 1193 static void virt_device_plug_cb(HotplugHandler *hotplug_dev, 1194 DeviceState *dev, Error **errp) 1195 { 1196 LoongArchVirtMachineState *lvms = LOONGARCH_VIRT_MACHINE(hotplug_dev); 1197 MachineClass *mc = MACHINE_GET_CLASS(lvms); 1198 PlatformBusDevice *pbus; 1199 1200 if (device_is_dynamic_sysbus(mc, dev)) { 1201 if (lvms->platform_bus_dev) { 1202 pbus = PLATFORM_BUS_DEVICE(lvms->platform_bus_dev); 1203 platform_bus_link_device(pbus, SYS_BUS_DEVICE(dev)); 1204 } 1205 } else if (memhp_type_supported(dev)) { 1206 virt_mem_plug(hotplug_dev, dev, errp); 1207 } 1208 } 1209 1210 static HotplugHandler *virt_get_hotplug_handler(MachineState *machine, 1211 DeviceState *dev) 1212 { 1213 MachineClass *mc = MACHINE_GET_CLASS(machine); 1214 1215 if (device_is_dynamic_sysbus(mc, dev) || 1216 memhp_type_supported(dev)) { 1217 return HOTPLUG_HANDLER(machine); 1218 } 1219 return NULL; 1220 } 1221 1222 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1223 { 1224 int n; 1225 unsigned int max_cpus = ms->smp.max_cpus; 1226 1227 if (ms->possible_cpus) { 1228 assert(ms->possible_cpus->len == max_cpus); 1229 return ms->possible_cpus; 1230 } 1231 1232 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1233 sizeof(CPUArchId) * max_cpus); 1234 ms->possible_cpus->len = max_cpus; 1235 for (n = 0; n < ms->possible_cpus->len; n++) { 1236 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1237 ms->possible_cpus->cpus[n].arch_id = n; 1238 1239 ms->possible_cpus->cpus[n].props.has_socket_id = true; 1240 ms->possible_cpus->cpus[n].props.socket_id = 1241 n / (ms->smp.cores * ms->smp.threads); 1242 ms->possible_cpus->cpus[n].props.has_core_id = true; 1243 ms->possible_cpus->cpus[n].props.core_id = 1244 n / ms->smp.threads % ms->smp.cores; 1245 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1246 ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads; 1247 } 1248 return ms->possible_cpus; 1249 } 1250 1251 static CpuInstanceProperties virt_cpu_index_to_props(MachineState *ms, 1252 unsigned cpu_index) 1253 { 1254 MachineClass *mc = MACHINE_GET_CLASS(ms); 1255 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1256 1257 assert(cpu_index < possible_cpus->len); 1258 return possible_cpus->cpus[cpu_index].props; 1259 } 1260 1261 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1262 { 1263 int64_t socket_id; 1264 1265 if (ms->numa_state->num_nodes) { 1266 socket_id = ms->possible_cpus->cpus[idx].props.socket_id; 1267 return socket_id % ms->numa_state->num_nodes; 1268 } else { 1269 return 0; 1270 } 1271 } 1272 1273 static void virt_class_init(ObjectClass *oc, void *data) 1274 { 1275 MachineClass *mc = MACHINE_CLASS(oc); 1276 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1277 1278 mc->init = virt_init; 1279 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); 1280 mc->default_ram_id = "loongarch.ram"; 1281 mc->max_cpus = LOONGARCH_MAX_CPUS; 1282 mc->is_default = 1; 1283 mc->default_kernel_irqchip_split = false; 1284 mc->block_default_type = IF_VIRTIO; 1285 mc->default_boot_order = "c"; 1286 mc->no_cdrom = 1; 1287 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1288 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1289 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1290 mc->numa_mem_supported = true; 1291 mc->auto_enable_numa_with_memhp = true; 1292 mc->auto_enable_numa_with_memdev = true; 1293 mc->get_hotplug_handler = virt_get_hotplug_handler; 1294 mc->default_nic = "virtio-net-pci"; 1295 hc->plug = virt_device_plug_cb; 1296 hc->pre_plug = virt_device_pre_plug; 1297 hc->unplug_request = virt_device_unplug_request; 1298 hc->unplug = virt_device_unplug; 1299 1300 object_class_property_add(oc, "acpi", "OnOffAuto", 1301 virt_get_acpi, virt_set_acpi, 1302 NULL, NULL); 1303 object_class_property_set_description(oc, "acpi", 1304 "Enable ACPI"); 1305 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1306 #ifdef CONFIG_TPM 1307 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1308 #endif 1309 } 1310 1311 static const TypeInfo virt_machine_types[] = { 1312 { 1313 .name = TYPE_LOONGARCH_VIRT_MACHINE, 1314 .parent = TYPE_MACHINE, 1315 .instance_size = sizeof(LoongArchVirtMachineState), 1316 .class_init = virt_class_init, 1317 .instance_init = virt_initfn, 1318 .interfaces = (InterfaceInfo[]) { 1319 { TYPE_HOTPLUG_HANDLER }, 1320 { } 1321 }, 1322 } 1323 }; 1324 1325 DEFINE_TYPES(virt_machine_types) 1326