1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * QEMU loongson 3a5000 develop board emulation 4 * 5 * Copyright (c) 2021 Loongson Technology Corporation Limited 6 */ 7 #include "qemu/osdep.h" 8 #include "qemu/units.h" 9 #include "qemu/datadir.h" 10 #include "qapi/error.h" 11 #include "hw/boards.h" 12 #include "hw/char/serial.h" 13 #include "sysemu/sysemu.h" 14 #include "sysemu/qtest.h" 15 #include "sysemu/runstate.h" 16 #include "sysemu/reset.h" 17 #include "sysemu/rtc.h" 18 #include "hw/loongarch/virt.h" 19 #include "exec/address-spaces.h" 20 #include "hw/irq.h" 21 #include "net/net.h" 22 #include "hw/loader.h" 23 #include "elf.h" 24 #include "hw/intc/loongarch_ipi.h" 25 #include "hw/intc/loongarch_extioi.h" 26 #include "hw/intc/loongarch_pch_pic.h" 27 #include "hw/intc/loongarch_pch_msi.h" 28 #include "hw/pci-host/ls7a.h" 29 #include "hw/pci-host/gpex.h" 30 #include "hw/misc/unimp.h" 31 #include "hw/loongarch/fw_cfg.h" 32 #include "target/loongarch/cpu.h" 33 #include "hw/firmware/smbios.h" 34 #include "hw/acpi/aml-build.h" 35 #include "qapi/qapi-visit-common.h" 36 #include "hw/acpi/generic_event_device.h" 37 #include "hw/mem/nvdimm.h" 38 #include "sysemu/device_tree.h" 39 #include <libfdt.h> 40 #include "hw/core/sysbus-fdt.h" 41 #include "hw/platform-bus.h" 42 #include "hw/display/ramfb.h" 43 #include "hw/mem/pc-dimm.h" 44 #include "sysemu/tpm.h" 45 #include "sysemu/block-backend.h" 46 #include "hw/block/flash.h" 47 #include "qemu/error-report.h" 48 49 50 struct loaderparams { 51 uint64_t ram_size; 52 const char *kernel_filename; 53 const char *kernel_cmdline; 54 const char *initrd_filename; 55 }; 56 57 static PFlashCFI01 *virt_flash_create1(LoongArchMachineState *lams, 58 const char *name, 59 const char *alias_prop_name) 60 { 61 DeviceState *dev = qdev_new(TYPE_PFLASH_CFI01); 62 63 qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); 64 qdev_prop_set_uint8(dev, "width", 4); 65 qdev_prop_set_uint8(dev, "device-width", 2); 66 qdev_prop_set_bit(dev, "big-endian", false); 67 qdev_prop_set_uint16(dev, "id0", 0x89); 68 qdev_prop_set_uint16(dev, "id1", 0x18); 69 qdev_prop_set_uint16(dev, "id2", 0x00); 70 qdev_prop_set_uint16(dev, "id3", 0x00); 71 qdev_prop_set_string(dev, "name", name); 72 object_property_add_child(OBJECT(lams), name, OBJECT(dev)); 73 object_property_add_alias(OBJECT(lams), alias_prop_name, 74 OBJECT(dev), "drive"); 75 return PFLASH_CFI01(dev); 76 } 77 78 static void virt_flash_create(LoongArchMachineState *lams) 79 { 80 lams->flash[0] = virt_flash_create1(lams, "virt.flash0", "pflash0"); 81 lams->flash[1] = virt_flash_create1(lams, "virt.flash1", "pflash1"); 82 } 83 84 static void virt_flash_map1(PFlashCFI01 *flash, 85 hwaddr base, hwaddr size, 86 MemoryRegion *sysmem) 87 { 88 DeviceState *dev = DEVICE(flash); 89 BlockBackend *blk; 90 hwaddr real_size = size; 91 92 blk = pflash_cfi01_get_blk(flash); 93 if (blk) { 94 real_size = blk_getlength(blk); 95 assert(real_size && real_size <= size); 96 } 97 98 assert(QEMU_IS_ALIGNED(real_size, VIRT_FLASH_SECTOR_SIZE)); 99 assert(real_size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); 100 101 qdev_prop_set_uint32(dev, "num-blocks", real_size / VIRT_FLASH_SECTOR_SIZE); 102 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 103 memory_region_add_subregion(sysmem, base, 104 sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0)); 105 } 106 107 static void virt_flash_map(LoongArchMachineState *lams, 108 MemoryRegion *sysmem) 109 { 110 PFlashCFI01 *flash0 = lams->flash[0]; 111 PFlashCFI01 *flash1 = lams->flash[1]; 112 113 virt_flash_map1(flash0, VIRT_FLASH0_BASE, VIRT_FLASH0_SIZE, sysmem); 114 virt_flash_map1(flash1, VIRT_FLASH1_BASE, VIRT_FLASH1_SIZE, sysmem); 115 } 116 117 static void fdt_add_flash_node(LoongArchMachineState *lams) 118 { 119 MachineState *ms = MACHINE(lams); 120 char *nodename; 121 MemoryRegion *flash_mem; 122 123 hwaddr flash0_base; 124 hwaddr flash0_size; 125 126 hwaddr flash1_base; 127 hwaddr flash1_size; 128 129 flash_mem = pflash_cfi01_get_memory(lams->flash[0]); 130 flash0_base = flash_mem->addr; 131 flash0_size = memory_region_size(flash_mem); 132 133 flash_mem = pflash_cfi01_get_memory(lams->flash[1]); 134 flash1_base = flash_mem->addr; 135 flash1_size = memory_region_size(flash_mem); 136 137 nodename = g_strdup_printf("/flash@%" PRIx64, flash0_base); 138 qemu_fdt_add_subnode(ms->fdt, nodename); 139 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "cfi-flash"); 140 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 141 2, flash0_base, 2, flash0_size, 142 2, flash1_base, 2, flash1_size); 143 qemu_fdt_setprop_cell(ms->fdt, nodename, "bank-width", 4); 144 g_free(nodename); 145 } 146 147 static void fdt_add_rtc_node(LoongArchMachineState *lams) 148 { 149 char *nodename; 150 hwaddr base = VIRT_RTC_REG_BASE; 151 hwaddr size = VIRT_RTC_LEN; 152 MachineState *ms = MACHINE(lams); 153 154 nodename = g_strdup_printf("/rtc@%" PRIx64, base); 155 qemu_fdt_add_subnode(ms->fdt, nodename); 156 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "loongson,ls7a-rtc"); 157 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 158 g_free(nodename); 159 } 160 161 static void fdt_add_uart_node(LoongArchMachineState *lams) 162 { 163 char *nodename; 164 hwaddr base = VIRT_UART_BASE; 165 hwaddr size = VIRT_UART_SIZE; 166 MachineState *ms = MACHINE(lams); 167 168 nodename = g_strdup_printf("/serial@%" PRIx64, base); 169 qemu_fdt_add_subnode(ms->fdt, nodename); 170 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", "ns16550a"); 171 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0x0, base, 0x0, size); 172 qemu_fdt_setprop_cell(ms->fdt, nodename, "clock-frequency", 100000000); 173 qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename); 174 g_free(nodename); 175 } 176 177 static void create_fdt(LoongArchMachineState *lams) 178 { 179 MachineState *ms = MACHINE(lams); 180 181 ms->fdt = create_device_tree(&lams->fdt_size); 182 if (!ms->fdt) { 183 error_report("create_device_tree() failed"); 184 exit(1); 185 } 186 187 /* Header */ 188 qemu_fdt_setprop_string(ms->fdt, "/", "compatible", 189 "linux,dummy-loongson3"); 190 qemu_fdt_setprop_cell(ms->fdt, "/", "#address-cells", 0x2); 191 qemu_fdt_setprop_cell(ms->fdt, "/", "#size-cells", 0x2); 192 qemu_fdt_add_subnode(ms->fdt, "/chosen"); 193 } 194 195 static void fdt_add_cpu_nodes(const LoongArchMachineState *lams) 196 { 197 int num; 198 const MachineState *ms = MACHINE(lams); 199 int smp_cpus = ms->smp.cpus; 200 201 qemu_fdt_add_subnode(ms->fdt, "/cpus"); 202 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1); 203 qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0); 204 205 /* cpu nodes */ 206 for (num = smp_cpus - 1; num >= 0; num--) { 207 char *nodename = g_strdup_printf("/cpus/cpu@%d", num); 208 LoongArchCPU *cpu = LOONGARCH_CPU(qemu_get_cpu(num)); 209 CPUState *cs = CPU(cpu); 210 211 qemu_fdt_add_subnode(ms->fdt, nodename); 212 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu"); 213 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 214 cpu->dtb_compatible); 215 if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) { 216 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", 217 ms->possible_cpus->cpus[cs->cpu_index].props.node_id); 218 } 219 qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num); 220 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", 221 qemu_fdt_alloc_phandle(ms->fdt)); 222 g_free(nodename); 223 } 224 225 /*cpu map */ 226 qemu_fdt_add_subnode(ms->fdt, "/cpus/cpu-map"); 227 228 for (num = smp_cpus - 1; num >= 0; num--) { 229 char *cpu_path = g_strdup_printf("/cpus/cpu@%d", num); 230 char *map_path; 231 232 if (ms->smp.threads > 1) { 233 map_path = g_strdup_printf( 234 "/cpus/cpu-map/socket%d/core%d/thread%d", 235 num / (ms->smp.cores * ms->smp.threads), 236 (num / ms->smp.threads) % ms->smp.cores, 237 num % ms->smp.threads); 238 } else { 239 map_path = g_strdup_printf( 240 "/cpus/cpu-map/socket%d/core%d", 241 num / ms->smp.cores, 242 num % ms->smp.cores); 243 } 244 qemu_fdt_add_path(ms->fdt, map_path); 245 qemu_fdt_setprop_phandle(ms->fdt, map_path, "cpu", cpu_path); 246 247 g_free(map_path); 248 g_free(cpu_path); 249 } 250 } 251 252 static void fdt_add_fw_cfg_node(const LoongArchMachineState *lams) 253 { 254 char *nodename; 255 hwaddr base = VIRT_FWCFG_BASE; 256 const MachineState *ms = MACHINE(lams); 257 258 nodename = g_strdup_printf("/fw_cfg@%" PRIx64, base); 259 qemu_fdt_add_subnode(ms->fdt, nodename); 260 qemu_fdt_setprop_string(ms->fdt, nodename, 261 "compatible", "qemu,fw-cfg-mmio"); 262 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 263 2, base, 2, 0x18); 264 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 265 g_free(nodename); 266 } 267 268 static void fdt_add_pcie_node(const LoongArchMachineState *lams) 269 { 270 char *nodename; 271 hwaddr base_mmio = VIRT_PCI_MEM_BASE; 272 hwaddr size_mmio = VIRT_PCI_MEM_SIZE; 273 hwaddr base_pio = VIRT_PCI_IO_BASE; 274 hwaddr size_pio = VIRT_PCI_IO_SIZE; 275 hwaddr base_pcie = VIRT_PCI_CFG_BASE; 276 hwaddr size_pcie = VIRT_PCI_CFG_SIZE; 277 hwaddr base = base_pcie; 278 279 const MachineState *ms = MACHINE(lams); 280 281 nodename = g_strdup_printf("/pcie@%" PRIx64, base); 282 qemu_fdt_add_subnode(ms->fdt, nodename); 283 qemu_fdt_setprop_string(ms->fdt, nodename, 284 "compatible", "pci-host-ecam-generic"); 285 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "pci"); 286 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 3); 287 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 2); 288 qemu_fdt_setprop_cell(ms->fdt, nodename, "linux,pci-domain", 0); 289 qemu_fdt_setprop_cells(ms->fdt, nodename, "bus-range", 0, 290 PCIE_MMCFG_BUS(VIRT_PCI_CFG_SIZE - 1)); 291 qemu_fdt_setprop(ms->fdt, nodename, "dma-coherent", NULL, 0); 292 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 293 2, base_pcie, 2, size_pcie); 294 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "ranges", 295 1, FDT_PCI_RANGE_IOPORT, 2, VIRT_PCI_IO_OFFSET, 296 2, base_pio, 2, size_pio, 297 1, FDT_PCI_RANGE_MMIO, 2, base_mmio, 298 2, base_mmio, 2, size_mmio); 299 g_free(nodename); 300 } 301 302 static void fdt_add_irqchip_node(LoongArchMachineState *lams) 303 { 304 MachineState *ms = MACHINE(lams); 305 char *nodename; 306 uint32_t irqchip_phandle; 307 308 irqchip_phandle = qemu_fdt_alloc_phandle(ms->fdt); 309 qemu_fdt_setprop_cell(ms->fdt, "/", "interrupt-parent", irqchip_phandle); 310 311 nodename = g_strdup_printf("/intc@%lx", VIRT_IOAPIC_REG_BASE); 312 qemu_fdt_add_subnode(ms->fdt, nodename); 313 qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 3); 314 qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0); 315 qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); 316 qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); 317 qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); 318 319 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", 320 "loongarch,ls7a"); 321 322 qemu_fdt_setprop_sized_cells(ms->fdt, nodename, "reg", 323 2, VIRT_IOAPIC_REG_BASE, 324 2, PCH_PIC_ROUTE_ENTRY_OFFSET); 325 326 qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", irqchip_phandle); 327 g_free(nodename); 328 } 329 330 static void fdt_add_memory_node(MachineState *ms, 331 uint64_t base, uint64_t size, int node_id) 332 { 333 char *nodename = g_strdup_printf("/memory@%" PRIx64, base); 334 335 qemu_fdt_add_subnode(ms->fdt, nodename); 336 qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 2, base, 2, size); 337 qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "memory"); 338 339 if (ms->numa_state && ms->numa_state->num_nodes) { 340 qemu_fdt_setprop_cell(ms->fdt, nodename, "numa-node-id", node_id); 341 } 342 343 g_free(nodename); 344 } 345 346 static void virt_build_smbios(LoongArchMachineState *lams) 347 { 348 MachineState *ms = MACHINE(lams); 349 MachineClass *mc = MACHINE_GET_CLASS(lams); 350 uint8_t *smbios_tables, *smbios_anchor; 351 size_t smbios_tables_len, smbios_anchor_len; 352 const char *product = "QEMU Virtual Machine"; 353 354 if (!lams->fw_cfg) { 355 return; 356 } 357 358 smbios_set_defaults("QEMU", product, mc->name, true); 359 360 smbios_get_tables(ms, SMBIOS_ENTRY_POINT_TYPE_64, 361 NULL, 0, 362 &smbios_tables, &smbios_tables_len, 363 &smbios_anchor, &smbios_anchor_len, &error_fatal); 364 365 if (smbios_anchor) { 366 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-tables", 367 smbios_tables, smbios_tables_len); 368 fw_cfg_add_file(lams->fw_cfg, "etc/smbios/smbios-anchor", 369 smbios_anchor, smbios_anchor_len); 370 } 371 } 372 373 static void virt_machine_done(Notifier *notifier, void *data) 374 { 375 LoongArchMachineState *lams = container_of(notifier, 376 LoongArchMachineState, machine_done); 377 virt_build_smbios(lams); 378 loongarch_acpi_setup(lams); 379 } 380 381 static void virt_powerdown_req(Notifier *notifier, void *opaque) 382 { 383 LoongArchMachineState *s = container_of(notifier, 384 LoongArchMachineState, powerdown_notifier); 385 386 acpi_send_event(s->acpi_ged, ACPI_POWER_DOWN_STATUS); 387 } 388 389 struct memmap_entry { 390 uint64_t address; 391 uint64_t length; 392 uint32_t type; 393 uint32_t reserved; 394 }; 395 396 static struct memmap_entry *memmap_table; 397 static unsigned memmap_entries; 398 399 static void memmap_add_entry(uint64_t address, uint64_t length, uint32_t type) 400 { 401 /* Ensure there are no duplicate entries. */ 402 for (unsigned i = 0; i < memmap_entries; i++) { 403 assert(memmap_table[i].address != address); 404 } 405 406 memmap_table = g_renew(struct memmap_entry, memmap_table, 407 memmap_entries + 1); 408 memmap_table[memmap_entries].address = cpu_to_le64(address); 409 memmap_table[memmap_entries].length = cpu_to_le64(length); 410 memmap_table[memmap_entries].type = cpu_to_le32(type); 411 memmap_table[memmap_entries].reserved = 0; 412 memmap_entries++; 413 } 414 415 static uint64_t cpu_loongarch_virt_to_phys(void *opaque, uint64_t addr) 416 { 417 return addr & MAKE_64BIT_MASK(0, TARGET_PHYS_ADDR_SPACE_BITS); 418 } 419 420 static int64_t load_kernel_info(const struct loaderparams *loaderparams) 421 { 422 uint64_t kernel_entry, kernel_low, kernel_high; 423 ssize_t kernel_size; 424 425 kernel_size = load_elf(loaderparams->kernel_filename, NULL, 426 cpu_loongarch_virt_to_phys, NULL, 427 &kernel_entry, &kernel_low, 428 &kernel_high, NULL, 0, 429 EM_LOONGARCH, 1, 0); 430 431 if (kernel_size < 0) { 432 error_report("could not load kernel '%s': %s", 433 loaderparams->kernel_filename, 434 load_elf_strerror(kernel_size)); 435 exit(1); 436 } 437 return kernel_entry; 438 } 439 440 static DeviceState *create_acpi_ged(DeviceState *pch_pic, LoongArchMachineState *lams) 441 { 442 DeviceState *dev; 443 MachineState *ms = MACHINE(lams); 444 uint32_t event = ACPI_GED_PWR_DOWN_EVT; 445 446 if (ms->ram_slots) { 447 event |= ACPI_GED_MEM_HOTPLUG_EVT; 448 } 449 dev = qdev_new(TYPE_ACPI_GED); 450 qdev_prop_set_uint32(dev, "ged-event", event); 451 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 452 453 /* ged event */ 454 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, VIRT_GED_EVT_ADDR); 455 /* memory hotplug */ 456 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 1, VIRT_GED_MEM_ADDR); 457 /* ged regs used for reset and power down */ 458 sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, VIRT_GED_REG_ADDR); 459 460 sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, 461 qdev_get_gpio_in(pch_pic, VIRT_SCI_IRQ - VIRT_GSI_BASE)); 462 return dev; 463 } 464 465 static DeviceState *create_platform_bus(DeviceState *pch_pic) 466 { 467 DeviceState *dev; 468 SysBusDevice *sysbus; 469 int i, irq; 470 MemoryRegion *sysmem = get_system_memory(); 471 472 dev = qdev_new(TYPE_PLATFORM_BUS_DEVICE); 473 dev->id = g_strdup(TYPE_PLATFORM_BUS_DEVICE); 474 qdev_prop_set_uint32(dev, "num_irqs", VIRT_PLATFORM_BUS_NUM_IRQS); 475 qdev_prop_set_uint32(dev, "mmio_size", VIRT_PLATFORM_BUS_SIZE); 476 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 477 478 sysbus = SYS_BUS_DEVICE(dev); 479 for (i = 0; i < VIRT_PLATFORM_BUS_NUM_IRQS; i++) { 480 irq = VIRT_PLATFORM_BUS_IRQ - VIRT_GSI_BASE + i; 481 sysbus_connect_irq(sysbus, i, qdev_get_gpio_in(pch_pic, irq)); 482 } 483 484 memory_region_add_subregion(sysmem, 485 VIRT_PLATFORM_BUS_BASEADDRESS, 486 sysbus_mmio_get_region(sysbus, 0)); 487 return dev; 488 } 489 490 static void loongarch_devices_init(DeviceState *pch_pic, LoongArchMachineState *lams) 491 { 492 MachineClass *mc = MACHINE_GET_CLASS(lams); 493 DeviceState *gpex_dev; 494 SysBusDevice *d; 495 PCIBus *pci_bus; 496 MemoryRegion *ecam_alias, *ecam_reg, *pio_alias, *pio_reg; 497 MemoryRegion *mmio_alias, *mmio_reg; 498 int i; 499 500 gpex_dev = qdev_new(TYPE_GPEX_HOST); 501 d = SYS_BUS_DEVICE(gpex_dev); 502 sysbus_realize_and_unref(d, &error_fatal); 503 pci_bus = PCI_HOST_BRIDGE(gpex_dev)->bus; 504 lams->pci_bus = pci_bus; 505 506 /* Map only part size_ecam bytes of ECAM space */ 507 ecam_alias = g_new0(MemoryRegion, 1); 508 ecam_reg = sysbus_mmio_get_region(d, 0); 509 memory_region_init_alias(ecam_alias, OBJECT(gpex_dev), "pcie-ecam", 510 ecam_reg, 0, VIRT_PCI_CFG_SIZE); 511 memory_region_add_subregion(get_system_memory(), VIRT_PCI_CFG_BASE, 512 ecam_alias); 513 514 /* Map PCI mem space */ 515 mmio_alias = g_new0(MemoryRegion, 1); 516 mmio_reg = sysbus_mmio_get_region(d, 1); 517 memory_region_init_alias(mmio_alias, OBJECT(gpex_dev), "pcie-mmio", 518 mmio_reg, VIRT_PCI_MEM_BASE, VIRT_PCI_MEM_SIZE); 519 memory_region_add_subregion(get_system_memory(), VIRT_PCI_MEM_BASE, 520 mmio_alias); 521 522 /* Map PCI IO port space. */ 523 pio_alias = g_new0(MemoryRegion, 1); 524 pio_reg = sysbus_mmio_get_region(d, 2); 525 memory_region_init_alias(pio_alias, OBJECT(gpex_dev), "pcie-io", pio_reg, 526 VIRT_PCI_IO_OFFSET, VIRT_PCI_IO_SIZE); 527 memory_region_add_subregion(get_system_memory(), VIRT_PCI_IO_BASE, 528 pio_alias); 529 530 for (i = 0; i < GPEX_NUM_IRQS; i++) { 531 sysbus_connect_irq(d, i, 532 qdev_get_gpio_in(pch_pic, 16 + i)); 533 gpex_set_irq_num(GPEX_HOST(gpex_dev), i, 16 + i); 534 } 535 536 serial_mm_init(get_system_memory(), VIRT_UART_BASE, 0, 537 qdev_get_gpio_in(pch_pic, 538 VIRT_UART_IRQ - VIRT_GSI_BASE), 539 115200, serial_hd(0), DEVICE_LITTLE_ENDIAN); 540 fdt_add_uart_node(lams); 541 542 /* Network init */ 543 pci_init_nic_devices(pci_bus, mc->default_nic); 544 545 /* 546 * There are some invalid guest memory access. 547 * Create some unimplemented devices to emulate this. 548 */ 549 create_unimplemented_device("pci-dma-cfg", 0x1001041c, 0x4); 550 sysbus_create_simple("ls7a_rtc", VIRT_RTC_REG_BASE, 551 qdev_get_gpio_in(pch_pic, 552 VIRT_RTC_IRQ - VIRT_GSI_BASE)); 553 fdt_add_rtc_node(lams); 554 555 /* acpi ged */ 556 lams->acpi_ged = create_acpi_ged(pch_pic, lams); 557 /* platform bus */ 558 lams->platform_bus_dev = create_platform_bus(pch_pic); 559 } 560 561 static void loongarch_irq_init(LoongArchMachineState *lams) 562 { 563 MachineState *ms = MACHINE(lams); 564 DeviceState *pch_pic, *pch_msi, *cpudev; 565 DeviceState *ipi, *extioi; 566 SysBusDevice *d; 567 LoongArchCPU *lacpu; 568 CPULoongArchState *env; 569 CPUState *cpu_state; 570 int cpu, pin, i, start, num; 571 572 /* 573 * The connection of interrupts: 574 * +-----+ +---------+ +-------+ 575 * | IPI |--> | CPUINTC | <-- | Timer | 576 * +-----+ +---------+ +-------+ 577 * ^ 578 * | 579 * +---------+ 580 * | EIOINTC | 581 * +---------+ 582 * ^ ^ 583 * | | 584 * +---------+ +---------+ 585 * | PCH-PIC | | PCH-MSI | 586 * +---------+ +---------+ 587 * ^ ^ ^ 588 * | | | 589 * +--------+ +---------+ +---------+ 590 * | UARTs | | Devices | | Devices | 591 * +--------+ +---------+ +---------+ 592 */ 593 594 /* Create IPI device */ 595 ipi = qdev_new(TYPE_LOONGARCH_IPI); 596 qdev_prop_set_uint32(ipi, "num-cpu", ms->smp.cpus); 597 sysbus_realize_and_unref(SYS_BUS_DEVICE(ipi), &error_fatal); 598 599 /* IPI iocsr memory region */ 600 memory_region_add_subregion(&lams->system_iocsr, SMP_IPI_MAILBOX, 601 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 0)); 602 memory_region_add_subregion(&lams->system_iocsr, MAIL_SEND_ADDR, 603 sysbus_mmio_get_region(SYS_BUS_DEVICE(ipi), 1)); 604 605 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 606 cpu_state = qemu_get_cpu(cpu); 607 cpudev = DEVICE(cpu_state); 608 lacpu = LOONGARCH_CPU(cpu_state); 609 env = &(lacpu->env); 610 env->address_space_iocsr = &lams->as_iocsr; 611 612 /* connect ipi irq to cpu irq */ 613 qdev_connect_gpio_out(ipi, cpu, qdev_get_gpio_in(cpudev, IRQ_IPI)); 614 env->ipistate = ipi; 615 } 616 617 /* Create EXTIOI device */ 618 extioi = qdev_new(TYPE_LOONGARCH_EXTIOI); 619 qdev_prop_set_uint32(extioi, "num-cpu", ms->smp.cpus); 620 sysbus_realize_and_unref(SYS_BUS_DEVICE(extioi), &error_fatal); 621 memory_region_add_subregion(&lams->system_iocsr, APIC_BASE, 622 sysbus_mmio_get_region(SYS_BUS_DEVICE(extioi), 0)); 623 624 /* 625 * connect ext irq to the cpu irq 626 * cpu_pin[9:2] <= intc_pin[7:0] 627 */ 628 for (cpu = 0; cpu < ms->smp.cpus; cpu++) { 629 cpudev = DEVICE(qemu_get_cpu(cpu)); 630 for (pin = 0; pin < LS3A_INTC_IP; pin++) { 631 qdev_connect_gpio_out(extioi, (cpu * 8 + pin), 632 qdev_get_gpio_in(cpudev, pin + 2)); 633 } 634 } 635 636 pch_pic = qdev_new(TYPE_LOONGARCH_PCH_PIC); 637 num = VIRT_PCH_PIC_IRQ_NUM; 638 qdev_prop_set_uint32(pch_pic, "pch_pic_irq_num", num); 639 d = SYS_BUS_DEVICE(pch_pic); 640 sysbus_realize_and_unref(d, &error_fatal); 641 memory_region_add_subregion(get_system_memory(), VIRT_IOAPIC_REG_BASE, 642 sysbus_mmio_get_region(d, 0)); 643 memory_region_add_subregion(get_system_memory(), 644 VIRT_IOAPIC_REG_BASE + PCH_PIC_ROUTE_ENTRY_OFFSET, 645 sysbus_mmio_get_region(d, 1)); 646 memory_region_add_subregion(get_system_memory(), 647 VIRT_IOAPIC_REG_BASE + PCH_PIC_INT_STATUS_LO, 648 sysbus_mmio_get_region(d, 2)); 649 650 /* Connect pch_pic irqs to extioi */ 651 for (i = 0; i < num; i++) { 652 qdev_connect_gpio_out(DEVICE(d), i, qdev_get_gpio_in(extioi, i)); 653 } 654 655 pch_msi = qdev_new(TYPE_LOONGARCH_PCH_MSI); 656 start = num; 657 num = EXTIOI_IRQS - start; 658 qdev_prop_set_uint32(pch_msi, "msi_irq_base", start); 659 qdev_prop_set_uint32(pch_msi, "msi_irq_num", num); 660 d = SYS_BUS_DEVICE(pch_msi); 661 sysbus_realize_and_unref(d, &error_fatal); 662 sysbus_mmio_map(d, 0, VIRT_PCH_MSI_ADDR_LOW); 663 for (i = 0; i < num; i++) { 664 /* Connect pch_msi irqs to extioi */ 665 qdev_connect_gpio_out(DEVICE(d), i, 666 qdev_get_gpio_in(extioi, i + start)); 667 } 668 669 loongarch_devices_init(pch_pic, lams); 670 } 671 672 static void loongarch_firmware_init(LoongArchMachineState *lams) 673 { 674 char *filename = MACHINE(lams)->firmware; 675 char *bios_name = NULL; 676 int bios_size, i; 677 BlockBackend *pflash_blk0; 678 MemoryRegion *mr; 679 680 lams->bios_loaded = false; 681 682 /* Map legacy -drive if=pflash to machine properties */ 683 for (i = 0; i < ARRAY_SIZE(lams->flash); i++) { 684 pflash_cfi01_legacy_drive(lams->flash[i], 685 drive_get(IF_PFLASH, 0, i)); 686 } 687 688 virt_flash_map(lams, get_system_memory()); 689 690 pflash_blk0 = pflash_cfi01_get_blk(lams->flash[0]); 691 692 if (pflash_blk0) { 693 if (filename) { 694 error_report("cannot use both '-bios' and '-drive if=pflash'" 695 "options at once"); 696 exit(1); 697 } 698 lams->bios_loaded = true; 699 return; 700 } 701 702 if (filename) { 703 bios_name = qemu_find_file(QEMU_FILE_TYPE_BIOS, filename); 704 if (!bios_name) { 705 error_report("Could not find ROM image '%s'", filename); 706 exit(1); 707 } 708 709 mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(lams->flash[0]), 0); 710 bios_size = load_image_mr(bios_name, mr); 711 if (bios_size < 0) { 712 error_report("Could not load ROM image '%s'", bios_name); 713 exit(1); 714 } 715 g_free(bios_name); 716 lams->bios_loaded = true; 717 } 718 } 719 720 static void reset_load_elf(void *opaque) 721 { 722 LoongArchCPU *cpu = opaque; 723 CPULoongArchState *env = &cpu->env; 724 725 cpu_reset(CPU(cpu)); 726 if (env->load_elf) { 727 cpu_set_pc(CPU(cpu), env->elf_address); 728 } 729 } 730 731 static void fw_cfg_add_kernel_info(const struct loaderparams *loaderparams, 732 FWCfgState *fw_cfg) 733 { 734 /* 735 * Expose the kernel, the command line, and the initrd in fw_cfg. 736 * We don't process them here at all, it's all left to the 737 * firmware. 738 */ 739 load_image_to_fw_cfg(fw_cfg, 740 FW_CFG_KERNEL_SIZE, FW_CFG_KERNEL_DATA, 741 loaderparams->kernel_filename, 742 false); 743 744 if (loaderparams->initrd_filename) { 745 load_image_to_fw_cfg(fw_cfg, 746 FW_CFG_INITRD_SIZE, FW_CFG_INITRD_DATA, 747 loaderparams->initrd_filename, false); 748 } 749 750 if (loaderparams->kernel_cmdline) { 751 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 752 strlen(loaderparams->kernel_cmdline) + 1); 753 fw_cfg_add_string(fw_cfg, FW_CFG_CMDLINE_DATA, 754 loaderparams->kernel_cmdline); 755 } 756 } 757 758 static void loongarch_firmware_boot(LoongArchMachineState *lams, 759 const struct loaderparams *loaderparams) 760 { 761 fw_cfg_add_kernel_info(loaderparams, lams->fw_cfg); 762 } 763 764 static void loongarch_direct_kernel_boot(LoongArchMachineState *lams, 765 const struct loaderparams *loaderparams) 766 { 767 MachineState *machine = MACHINE(lams); 768 int64_t kernel_addr = 0; 769 LoongArchCPU *lacpu; 770 int i; 771 772 kernel_addr = load_kernel_info(loaderparams); 773 if (!machine->firmware) { 774 for (i = 0; i < machine->smp.cpus; i++) { 775 lacpu = LOONGARCH_CPU(qemu_get_cpu(i)); 776 lacpu->env.load_elf = true; 777 lacpu->env.elf_address = kernel_addr; 778 } 779 } 780 } 781 782 static void loongarch_qemu_write(void *opaque, hwaddr addr, 783 uint64_t val, unsigned size) 784 { 785 } 786 787 static uint64_t loongarch_qemu_read(void *opaque, hwaddr addr, unsigned size) 788 { 789 switch (addr) { 790 case VERSION_REG: 791 return 0x11ULL; 792 case FEATURE_REG: 793 return 1ULL << IOCSRF_MSI | 1ULL << IOCSRF_EXTIOI | 794 1ULL << IOCSRF_CSRIPI; 795 case VENDOR_REG: 796 return 0x6e6f73676e6f6f4cULL; /* "Loongson" */ 797 case CPUNAME_REG: 798 return 0x303030354133ULL; /* "3A5000" */ 799 case MISC_FUNC_REG: 800 return 1ULL << IOCSRM_EXTIOI_EN; 801 } 802 return 0ULL; 803 } 804 805 static const MemoryRegionOps loongarch_qemu_ops = { 806 .read = loongarch_qemu_read, 807 .write = loongarch_qemu_write, 808 .endianness = DEVICE_LITTLE_ENDIAN, 809 .valid = { 810 .min_access_size = 4, 811 .max_access_size = 8, 812 }, 813 .impl = { 814 .min_access_size = 8, 815 .max_access_size = 8, 816 }, 817 }; 818 819 static void loongarch_init(MachineState *machine) 820 { 821 LoongArchCPU *lacpu; 822 const char *cpu_model = machine->cpu_type; 823 ram_addr_t offset = 0; 824 ram_addr_t ram_size = machine->ram_size; 825 uint64_t highram_size = 0, phyAddr = 0; 826 MemoryRegion *address_space_mem = get_system_memory(); 827 LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); 828 int nb_numa_nodes = machine->numa_state->num_nodes; 829 NodeInfo *numa_info = machine->numa_state->nodes; 830 int i; 831 hwaddr fdt_base; 832 const CPUArchIdList *possible_cpus; 833 MachineClass *mc = MACHINE_GET_CLASS(machine); 834 CPUState *cpu; 835 char *ramName = NULL; 836 struct loaderparams loaderparams = { }; 837 838 if (!cpu_model) { 839 cpu_model = LOONGARCH_CPU_TYPE_NAME("la464"); 840 } 841 842 if (ram_size < 1 * GiB) { 843 error_report("ram_size must be greater than 1G."); 844 exit(1); 845 } 846 create_fdt(lams); 847 848 /* Create IOCSR space */ 849 memory_region_init_io(&lams->system_iocsr, OBJECT(machine), NULL, 850 machine, "iocsr", UINT64_MAX); 851 address_space_init(&lams->as_iocsr, &lams->system_iocsr, "IOCSR"); 852 memory_region_init_io(&lams->iocsr_mem, OBJECT(machine), 853 &loongarch_qemu_ops, 854 machine, "iocsr_misc", 0x428); 855 memory_region_add_subregion(&lams->system_iocsr, 0, &lams->iocsr_mem); 856 857 /* Init CPUs */ 858 possible_cpus = mc->possible_cpu_arch_ids(machine); 859 for (i = 0; i < possible_cpus->len; i++) { 860 cpu = cpu_create(machine->cpu_type); 861 cpu->cpu_index = i; 862 machine->possible_cpus->cpus[i].cpu = cpu; 863 lacpu = LOONGARCH_CPU(cpu); 864 lacpu->phy_id = machine->possible_cpus->cpus[i].arch_id; 865 } 866 fdt_add_cpu_nodes(lams); 867 868 /* Node0 memory */ 869 memmap_add_entry(VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 1); 870 fdt_add_memory_node(machine, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 0); 871 memory_region_init_alias(&lams->lowmem, NULL, "loongarch.node0.lowram", 872 machine->ram, offset, VIRT_LOWMEM_SIZE); 873 memory_region_add_subregion(address_space_mem, phyAddr, &lams->lowmem); 874 875 offset += VIRT_LOWMEM_SIZE; 876 if (nb_numa_nodes > 0) { 877 assert(numa_info[0].node_mem > VIRT_LOWMEM_SIZE); 878 highram_size = numa_info[0].node_mem - VIRT_LOWMEM_SIZE; 879 } else { 880 highram_size = ram_size - VIRT_LOWMEM_SIZE; 881 } 882 phyAddr = VIRT_HIGHMEM_BASE; 883 memmap_add_entry(phyAddr, highram_size, 1); 884 fdt_add_memory_node(machine, phyAddr, highram_size, 0); 885 memory_region_init_alias(&lams->highmem, NULL, "loongarch.node0.highram", 886 machine->ram, offset, highram_size); 887 memory_region_add_subregion(address_space_mem, phyAddr, &lams->highmem); 888 889 /* Node1 - Nodemax memory */ 890 offset += highram_size; 891 phyAddr += highram_size; 892 893 for (i = 1; i < nb_numa_nodes; i++) { 894 MemoryRegion *nodemem = g_new(MemoryRegion, 1); 895 ramName = g_strdup_printf("loongarch.node%d.ram", i); 896 memory_region_init_alias(nodemem, NULL, ramName, machine->ram, 897 offset, numa_info[i].node_mem); 898 memory_region_add_subregion(address_space_mem, phyAddr, nodemem); 899 memmap_add_entry(phyAddr, numa_info[i].node_mem, 1); 900 fdt_add_memory_node(machine, phyAddr, numa_info[i].node_mem, i); 901 offset += numa_info[i].node_mem; 902 phyAddr += numa_info[i].node_mem; 903 } 904 905 /* initialize device memory address space */ 906 if (machine->ram_size < machine->maxram_size) { 907 ram_addr_t device_mem_size = machine->maxram_size - machine->ram_size; 908 hwaddr device_mem_base; 909 910 if (machine->ram_slots > ACPI_MAX_RAM_SLOTS) { 911 error_report("unsupported amount of memory slots: %"PRIu64, 912 machine->ram_slots); 913 exit(EXIT_FAILURE); 914 } 915 916 if (QEMU_ALIGN_UP(machine->maxram_size, 917 TARGET_PAGE_SIZE) != machine->maxram_size) { 918 error_report("maximum memory size must by aligned to multiple of " 919 "%d bytes", TARGET_PAGE_SIZE); 920 exit(EXIT_FAILURE); 921 } 922 /* device memory base is the top of high memory address. */ 923 device_mem_base = ROUND_UP(VIRT_HIGHMEM_BASE + highram_size, 1 * GiB); 924 machine_memory_devices_init(machine, device_mem_base, device_mem_size); 925 } 926 927 /* load the BIOS image. */ 928 loongarch_firmware_init(lams); 929 930 /* fw_cfg init */ 931 lams->fw_cfg = loongarch_fw_cfg_init(ram_size, machine); 932 rom_set_fw(lams->fw_cfg); 933 if (lams->fw_cfg != NULL) { 934 fw_cfg_add_file(lams->fw_cfg, "etc/memmap", 935 memmap_table, 936 sizeof(struct memmap_entry) * (memmap_entries)); 937 } 938 fdt_add_fw_cfg_node(lams); 939 loaderparams.ram_size = ram_size; 940 loaderparams.kernel_filename = machine->kernel_filename; 941 loaderparams.kernel_cmdline = machine->kernel_cmdline; 942 loaderparams.initrd_filename = machine->initrd_filename; 943 /* load the kernel. */ 944 if (loaderparams.kernel_filename) { 945 if (lams->bios_loaded) { 946 loongarch_firmware_boot(lams, &loaderparams); 947 } else { 948 loongarch_direct_kernel_boot(lams, &loaderparams); 949 } 950 } 951 fdt_add_flash_node(lams); 952 /* register reset function */ 953 for (i = 0; i < machine->smp.cpus; i++) { 954 lacpu = LOONGARCH_CPU(qemu_get_cpu(i)); 955 qemu_register_reset(reset_load_elf, lacpu); 956 } 957 /* Initialize the IO interrupt subsystem */ 958 loongarch_irq_init(lams); 959 fdt_add_irqchip_node(lams); 960 platform_bus_add_all_fdt_nodes(machine->fdt, "/intc", 961 VIRT_PLATFORM_BUS_BASEADDRESS, 962 VIRT_PLATFORM_BUS_SIZE, 963 VIRT_PLATFORM_BUS_IRQ); 964 lams->machine_done.notify = virt_machine_done; 965 qemu_add_machine_init_done_notifier(&lams->machine_done); 966 /* connect powerdown request */ 967 lams->powerdown_notifier.notify = virt_powerdown_req; 968 qemu_register_powerdown_notifier(&lams->powerdown_notifier); 969 970 fdt_add_pcie_node(lams); 971 /* 972 * Since lowmem region starts from 0 and Linux kernel legacy start address 973 * at 2 MiB, FDT base address is located at 1 MiB to avoid NULL pointer 974 * access. FDT size limit with 1 MiB. 975 * Put the FDT into the memory map as a ROM image: this will ensure 976 * the FDT is copied again upon reset, even if addr points into RAM. 977 */ 978 fdt_base = 1 * MiB; 979 qemu_fdt_dumpdtb(machine->fdt, lams->fdt_size); 980 rom_add_blob_fixed("fdt", machine->fdt, lams->fdt_size, fdt_base); 981 } 982 983 bool loongarch_is_acpi_enabled(LoongArchMachineState *lams) 984 { 985 if (lams->acpi == ON_OFF_AUTO_OFF) { 986 return false; 987 } 988 return true; 989 } 990 991 static void loongarch_get_acpi(Object *obj, Visitor *v, const char *name, 992 void *opaque, Error **errp) 993 { 994 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 995 OnOffAuto acpi = lams->acpi; 996 997 visit_type_OnOffAuto(v, name, &acpi, errp); 998 } 999 1000 static void loongarch_set_acpi(Object *obj, Visitor *v, const char *name, 1001 void *opaque, Error **errp) 1002 { 1003 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 1004 1005 visit_type_OnOffAuto(v, name, &lams->acpi, errp); 1006 } 1007 1008 static void loongarch_machine_initfn(Object *obj) 1009 { 1010 LoongArchMachineState *lams = LOONGARCH_MACHINE(obj); 1011 1012 lams->acpi = ON_OFF_AUTO_AUTO; 1013 lams->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); 1014 lams->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); 1015 virt_flash_create(lams); 1016 } 1017 1018 static bool memhp_type_supported(DeviceState *dev) 1019 { 1020 /* we only support pc dimm now */ 1021 return object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && 1022 !object_dynamic_cast(OBJECT(dev), TYPE_NVDIMM); 1023 } 1024 1025 static void virt_mem_pre_plug(HotplugHandler *hotplug_dev, DeviceState *dev, 1026 Error **errp) 1027 { 1028 pc_dimm_pre_plug(PC_DIMM(dev), MACHINE(hotplug_dev), NULL, errp); 1029 } 1030 1031 static void virt_machine_device_pre_plug(HotplugHandler *hotplug_dev, 1032 DeviceState *dev, Error **errp) 1033 { 1034 if (memhp_type_supported(dev)) { 1035 virt_mem_pre_plug(hotplug_dev, dev, errp); 1036 } 1037 } 1038 1039 static void virt_mem_unplug_request(HotplugHandler *hotplug_dev, 1040 DeviceState *dev, Error **errp) 1041 { 1042 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1043 1044 /* the acpi ged is always exist */ 1045 hotplug_handler_unplug_request(HOTPLUG_HANDLER(lams->acpi_ged), dev, 1046 errp); 1047 } 1048 1049 static void virt_machine_device_unplug_request(HotplugHandler *hotplug_dev, 1050 DeviceState *dev, Error **errp) 1051 { 1052 if (memhp_type_supported(dev)) { 1053 virt_mem_unplug_request(hotplug_dev, dev, errp); 1054 } 1055 } 1056 1057 static void virt_mem_unplug(HotplugHandler *hotplug_dev, 1058 DeviceState *dev, Error **errp) 1059 { 1060 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1061 1062 hotplug_handler_unplug(HOTPLUG_HANDLER(lams->acpi_ged), dev, errp); 1063 pc_dimm_unplug(PC_DIMM(dev), MACHINE(lams)); 1064 qdev_unrealize(dev); 1065 } 1066 1067 static void virt_machine_device_unplug(HotplugHandler *hotplug_dev, 1068 DeviceState *dev, Error **errp) 1069 { 1070 if (memhp_type_supported(dev)) { 1071 virt_mem_unplug(hotplug_dev, dev, errp); 1072 } 1073 } 1074 1075 static void virt_mem_plug(HotplugHandler *hotplug_dev, 1076 DeviceState *dev, Error **errp) 1077 { 1078 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1079 1080 pc_dimm_plug(PC_DIMM(dev), MACHINE(lams)); 1081 hotplug_handler_plug(HOTPLUG_HANDLER(lams->acpi_ged), 1082 dev, &error_abort); 1083 } 1084 1085 static void loongarch_machine_device_plug_cb(HotplugHandler *hotplug_dev, 1086 DeviceState *dev, Error **errp) 1087 { 1088 LoongArchMachineState *lams = LOONGARCH_MACHINE(hotplug_dev); 1089 MachineClass *mc = MACHINE_GET_CLASS(lams); 1090 1091 if (device_is_dynamic_sysbus(mc, dev)) { 1092 if (lams->platform_bus_dev) { 1093 platform_bus_link_device(PLATFORM_BUS_DEVICE(lams->platform_bus_dev), 1094 SYS_BUS_DEVICE(dev)); 1095 } 1096 } else if (memhp_type_supported(dev)) { 1097 virt_mem_plug(hotplug_dev, dev, errp); 1098 } 1099 } 1100 1101 static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, 1102 DeviceState *dev) 1103 { 1104 MachineClass *mc = MACHINE_GET_CLASS(machine); 1105 1106 if (device_is_dynamic_sysbus(mc, dev) || 1107 memhp_type_supported(dev)) { 1108 return HOTPLUG_HANDLER(machine); 1109 } 1110 return NULL; 1111 } 1112 1113 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) 1114 { 1115 int n; 1116 unsigned int max_cpus = ms->smp.max_cpus; 1117 1118 if (ms->possible_cpus) { 1119 assert(ms->possible_cpus->len == max_cpus); 1120 return ms->possible_cpus; 1121 } 1122 1123 ms->possible_cpus = g_malloc0(sizeof(CPUArchIdList) + 1124 sizeof(CPUArchId) * max_cpus); 1125 ms->possible_cpus->len = max_cpus; 1126 for (n = 0; n < ms->possible_cpus->len; n++) { 1127 ms->possible_cpus->cpus[n].type = ms->cpu_type; 1128 ms->possible_cpus->cpus[n].arch_id = n; 1129 1130 ms->possible_cpus->cpus[n].props.has_socket_id = true; 1131 ms->possible_cpus->cpus[n].props.socket_id = 1132 n / (ms->smp.cores * ms->smp.threads); 1133 ms->possible_cpus->cpus[n].props.has_core_id = true; 1134 ms->possible_cpus->cpus[n].props.core_id = 1135 n / ms->smp.threads % ms->smp.cores; 1136 ms->possible_cpus->cpus[n].props.has_thread_id = true; 1137 ms->possible_cpus->cpus[n].props.thread_id = n % ms->smp.threads; 1138 } 1139 return ms->possible_cpus; 1140 } 1141 1142 static CpuInstanceProperties 1143 virt_cpu_index_to_props(MachineState *ms, unsigned cpu_index) 1144 { 1145 MachineClass *mc = MACHINE_GET_CLASS(ms); 1146 const CPUArchIdList *possible_cpus = mc->possible_cpu_arch_ids(ms); 1147 1148 assert(cpu_index < possible_cpus->len); 1149 return possible_cpus->cpus[cpu_index].props; 1150 } 1151 1152 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int idx) 1153 { 1154 int64_t nidx = 0; 1155 1156 if (ms->numa_state->num_nodes) { 1157 nidx = idx / (ms->smp.cpus / ms->numa_state->num_nodes); 1158 if (ms->numa_state->num_nodes <= nidx) { 1159 nidx = ms->numa_state->num_nodes - 1; 1160 } 1161 } 1162 return nidx; 1163 } 1164 1165 static void loongarch_class_init(ObjectClass *oc, void *data) 1166 { 1167 MachineClass *mc = MACHINE_CLASS(oc); 1168 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc); 1169 1170 mc->desc = "Loongson-3A5000 LS7A1000 machine"; 1171 mc->init = loongarch_init; 1172 mc->default_ram_size = 1 * GiB; 1173 mc->default_cpu_type = LOONGARCH_CPU_TYPE_NAME("la464"); 1174 mc->default_ram_id = "loongarch.ram"; 1175 mc->max_cpus = LOONGARCH_MAX_CPUS; 1176 mc->is_default = 1; 1177 mc->default_kernel_irqchip_split = false; 1178 mc->block_default_type = IF_VIRTIO; 1179 mc->default_boot_order = "c"; 1180 mc->no_cdrom = 1; 1181 mc->possible_cpu_arch_ids = virt_possible_cpu_arch_ids; 1182 mc->cpu_index_to_instance_props = virt_cpu_index_to_props; 1183 mc->get_default_cpu_node_id = virt_get_default_cpu_node_id; 1184 mc->numa_mem_supported = true; 1185 mc->auto_enable_numa_with_memhp = true; 1186 mc->auto_enable_numa_with_memdev = true; 1187 mc->get_hotplug_handler = virt_machine_get_hotplug_handler; 1188 mc->default_nic = "virtio-net-pci"; 1189 hc->plug = loongarch_machine_device_plug_cb; 1190 hc->pre_plug = virt_machine_device_pre_plug; 1191 hc->unplug_request = virt_machine_device_unplug_request; 1192 hc->unplug = virt_machine_device_unplug; 1193 1194 object_class_property_add(oc, "acpi", "OnOffAuto", 1195 loongarch_get_acpi, loongarch_set_acpi, 1196 NULL, NULL); 1197 object_class_property_set_description(oc, "acpi", 1198 "Enable ACPI"); 1199 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_RAMFB_DEVICE); 1200 #ifdef CONFIG_TPM 1201 machine_class_allow_dynamic_sysbus_dev(mc, TYPE_TPM_TIS_SYSBUS); 1202 #endif 1203 } 1204 1205 static const TypeInfo loongarch_machine_types[] = { 1206 { 1207 .name = TYPE_LOONGARCH_MACHINE, 1208 .parent = TYPE_MACHINE, 1209 .instance_size = sizeof(LoongArchMachineState), 1210 .class_init = loongarch_class_init, 1211 .instance_init = loongarch_machine_initfn, 1212 .interfaces = (InterfaceInfo[]) { 1213 { TYPE_HOTPLUG_HANDLER }, 1214 { } 1215 }, 1216 } 1217 }; 1218 1219 DEFINE_TYPES(loongarch_machine_types) 1220