1 /* SPDX-License-Identifier: GPL-2.0-or-later */ 2 /* 3 * Support for generating ACPI tables and passing them to Guests 4 * 5 * Copyright (C) 2021 Loongson Technology Corporation Limited 6 */ 7 8 #include "qemu/osdep.h" 9 #include "qapi/error.h" 10 #include "qemu/bitmap.h" 11 #include "hw/pci/pci.h" 12 #include "hw/core/cpu.h" 13 #include "target/loongarch/cpu.h" 14 #include "hw/acpi/acpi-defs.h" 15 #include "hw/acpi/acpi.h" 16 #include "hw/nvram/fw_cfg.h" 17 #include "hw/acpi/bios-linker-loader.h" 18 #include "migration/vmstate.h" 19 #include "hw/mem/memory-device.h" 20 #include "sysemu/reset.h" 21 22 /* Supported chipsets: */ 23 #include "hw/pci-host/ls7a.h" 24 #include "hw/loongarch/virt.h" 25 26 #include "hw/acpi/utils.h" 27 #include "hw/acpi/pci.h" 28 29 #include "qom/qom-qobject.h" 30 31 #include "hw/acpi/generic_event_device.h" 32 #include "hw/pci-host/gpex.h" 33 #include "sysemu/tpm.h" 34 #include "hw/platform-bus.h" 35 #include "hw/acpi/aml-build.h" 36 37 #define ACPI_BUILD_ALIGN_SIZE 0x1000 38 #define ACPI_BUILD_TABLE_SIZE 0x20000 39 40 #ifdef DEBUG_ACPI_BUILD 41 #define ACPI_BUILD_DPRINTF(fmt, ...) \ 42 do {printf("ACPI_BUILD: " fmt, ## __VA_ARGS__); } while (0) 43 #else 44 #define ACPI_BUILD_DPRINTF(fmt, ...) 45 #endif 46 47 /* build FADT */ 48 static void init_common_fadt_data(AcpiFadtData *data) 49 { 50 AcpiFadtData fadt = { 51 /* ACPI 5.0: 4.1 Hardware-Reduced ACPI */ 52 .rev = 5, 53 .flags = ((1 << ACPI_FADT_F_HW_REDUCED_ACPI) | 54 (1 << ACPI_FADT_F_RESET_REG_SUP)), 55 56 /* ACPI 5.0: 4.8.3.7 Sleep Control and Status Registers */ 57 .sleep_ctl = { 58 .space_id = AML_AS_SYSTEM_MEMORY, 59 .bit_width = 8, 60 .address = VIRT_GED_REG_ADDR + ACPI_GED_REG_SLEEP_CTL, 61 }, 62 .sleep_sts = { 63 .space_id = AML_AS_SYSTEM_MEMORY, 64 .bit_width = 8, 65 .address = VIRT_GED_REG_ADDR + ACPI_GED_REG_SLEEP_STS, 66 }, 67 68 /* ACPI 5.0: 4.8.3.6 Reset Register */ 69 .reset_reg = { 70 .space_id = AML_AS_SYSTEM_MEMORY, 71 .bit_width = 8, 72 .address = VIRT_GED_REG_ADDR + ACPI_GED_REG_RESET, 73 }, 74 .reset_val = ACPI_GED_RESET_VALUE, 75 }; 76 *data = fadt; 77 } 78 79 static void acpi_align_size(GArray *blob, unsigned align) 80 { 81 /* 82 * Align size to multiple of given size. This reduces the chance 83 * we need to change size in the future (breaking cross version migration). 84 */ 85 g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); 86 } 87 88 /* build FACS */ 89 static void 90 build_facs(GArray *table_data) 91 { 92 const char *sig = "FACS"; 93 const uint8_t reserved[40] = {}; 94 95 g_array_append_vals(table_data, sig, 4); /* Signature */ 96 build_append_int_noprefix(table_data, 64, 4); /* Length */ 97 build_append_int_noprefix(table_data, 0, 4); /* Hardware Signature */ 98 build_append_int_noprefix(table_data, 0, 4); /* Firmware Waking Vector */ 99 build_append_int_noprefix(table_data, 0, 4); /* Global Lock */ 100 build_append_int_noprefix(table_data, 0, 4); /* Flags */ 101 g_array_append_vals(table_data, reserved, 40); /* Reserved */ 102 } 103 104 /* build MADT */ 105 static void 106 build_madt(GArray *table_data, BIOSLinker *linker, LoongArchMachineState *lams) 107 { 108 MachineState *ms = MACHINE(lams); 109 int i; 110 AcpiTable table = { .sig = "APIC", .rev = 1, .oem_id = lams->oem_id, 111 .oem_table_id = lams->oem_table_id }; 112 113 acpi_table_begin(&table, table_data); 114 115 /* Local APIC Address */ 116 build_append_int_noprefix(table_data, 0, 4); 117 build_append_int_noprefix(table_data, 1 /* PCAT_COMPAT */, 4); /* Flags */ 118 119 for (i = 0; i < ms->smp.cpus; i++) { 120 /* Processor Core Interrupt Controller Structure */ 121 build_append_int_noprefix(table_data, 17, 1); /* Type */ 122 build_append_int_noprefix(table_data, 15, 1); /* Length */ 123 build_append_int_noprefix(table_data, 1, 1); /* Version */ 124 build_append_int_noprefix(table_data, i + 1, 4); /* ACPI Processor ID */ 125 build_append_int_noprefix(table_data, i, 4); /* Core ID */ 126 build_append_int_noprefix(table_data, 1, 4); /* Flags */ 127 } 128 129 /* Extend I/O Interrupt Controller Structure */ 130 build_append_int_noprefix(table_data, 20, 1); /* Type */ 131 build_append_int_noprefix(table_data, 13, 1); /* Length */ 132 build_append_int_noprefix(table_data, 1, 1); /* Version */ 133 build_append_int_noprefix(table_data, 3, 1); /* Cascade */ 134 build_append_int_noprefix(table_data, 0, 1); /* Node */ 135 build_append_int_noprefix(table_data, 0xffff, 8); /* Node map */ 136 137 /* MSI Interrupt Controller Structure */ 138 build_append_int_noprefix(table_data, 21, 1); /* Type */ 139 build_append_int_noprefix(table_data, 19, 1); /* Length */ 140 build_append_int_noprefix(table_data, 1, 1); /* Version */ 141 build_append_int_noprefix(table_data, VIRT_PCH_MSI_ADDR_LOW, 8);/* Address */ 142 build_append_int_noprefix(table_data, 0x40, 4); /* Start */ 143 build_append_int_noprefix(table_data, 0xc0, 4); /* Count */ 144 145 /* Bridge I/O Interrupt Controller Structure */ 146 build_append_int_noprefix(table_data, 22, 1); /* Type */ 147 build_append_int_noprefix(table_data, 17, 1); /* Length */ 148 build_append_int_noprefix(table_data, 1, 1); /* Version */ 149 build_append_int_noprefix(table_data, VIRT_PCH_REG_BASE, 8);/* Address */ 150 build_append_int_noprefix(table_data, 0x1000, 2); /* Size */ 151 build_append_int_noprefix(table_data, 0, 2); /* Id */ 152 build_append_int_noprefix(table_data, 0x40, 2); /* Base */ 153 154 acpi_table_end(linker, &table); 155 } 156 157 /* build SRAT */ 158 static void 159 build_srat(GArray *table_data, BIOSLinker *linker, MachineState *machine) 160 { 161 uint64_t i; 162 LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); 163 MachineState *ms = MACHINE(lams); 164 AcpiTable table = { .sig = "SRAT", .rev = 1, .oem_id = lams->oem_id, 165 .oem_table_id = lams->oem_table_id }; 166 167 acpi_table_begin(&table, table_data); 168 build_append_int_noprefix(table_data, 1, 4); /* Reserved */ 169 build_append_int_noprefix(table_data, 0, 8); /* Reserved */ 170 171 for (i = 0; i < ms->smp.cpus; ++i) { 172 /* Processor Local APIC/SAPIC Affinity Structure */ 173 build_append_int_noprefix(table_data, 0, 1); /* Type */ 174 build_append_int_noprefix(table_data, 16, 1); /* Length */ 175 /* Proximity Domain [7:0] */ 176 build_append_int_noprefix(table_data, 0, 1); 177 build_append_int_noprefix(table_data, i, 1); /* APIC ID */ 178 /* Flags, Table 5-36 */ 179 build_append_int_noprefix(table_data, 1, 4); 180 build_append_int_noprefix(table_data, 0, 1); /* Local SAPIC EID */ 181 /* Proximity Domain [31:8] */ 182 build_append_int_noprefix(table_data, 0, 3); 183 build_append_int_noprefix(table_data, 0, 4); /* Reserved */ 184 } 185 186 build_srat_memory(table_data, VIRT_LOWMEM_BASE, VIRT_LOWMEM_SIZE, 187 0, MEM_AFFINITY_ENABLED); 188 189 build_srat_memory(table_data, VIRT_HIGHMEM_BASE, machine->ram_size - VIRT_LOWMEM_SIZE, 190 0, MEM_AFFINITY_ENABLED); 191 192 if (ms->device_memory) { 193 build_srat_memory(table_data, ms->device_memory->base, 194 memory_region_size(&ms->device_memory->mr), 195 0, MEM_AFFINITY_HOTPLUGGABLE | MEM_AFFINITY_ENABLED); 196 } 197 198 acpi_table_end(linker, &table); 199 } 200 201 typedef 202 struct AcpiBuildState { 203 /* Copy of table in RAM (for patching). */ 204 MemoryRegion *table_mr; 205 /* Is table patched? */ 206 uint8_t patched; 207 void *rsdp; 208 MemoryRegion *rsdp_mr; 209 MemoryRegion *linker_mr; 210 } AcpiBuildState; 211 212 static void build_uart_device_aml(Aml *table) 213 { 214 Aml *dev; 215 Aml *crs; 216 Aml *pkg0, *pkg1, *pkg2; 217 uint32_t uart_irq = VIRT_UART_IRQ; 218 219 Aml *scope = aml_scope("_SB"); 220 dev = aml_device("COMA"); 221 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0501"))); 222 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 223 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 224 crs = aml_resource_template(); 225 aml_append(crs, 226 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 227 AML_NON_CACHEABLE, AML_READ_WRITE, 228 0, VIRT_UART_BASE, VIRT_UART_BASE + VIRT_UART_SIZE - 1, 229 0, VIRT_UART_SIZE)); 230 aml_append(crs, aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 231 AML_SHARED, &uart_irq, 1)); 232 aml_append(dev, aml_name_decl("_CRS", crs)); 233 pkg0 = aml_package(0x2); 234 aml_append(pkg0, aml_int(0x05F5E100)); 235 aml_append(pkg0, aml_string("clock-frenquency")); 236 pkg1 = aml_package(0x1); 237 aml_append(pkg1, pkg0); 238 pkg2 = aml_package(0x2); 239 aml_append(pkg2, aml_touuid("DAFFD814-6EBA-4D8C-8A91-BC9BBF4AA301")); 240 aml_append(pkg2, pkg1); 241 aml_append(dev, aml_name_decl("_DSD", pkg2)); 242 aml_append(scope, dev); 243 aml_append(table, scope); 244 } 245 246 static void 247 build_la_ged_aml(Aml *dsdt, MachineState *machine) 248 { 249 uint32_t event; 250 LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); 251 252 build_ged_aml(dsdt, "\\_SB."GED_DEVICE, 253 HOTPLUG_HANDLER(lams->acpi_ged), 254 VIRT_SCI_IRQ, AML_SYSTEM_MEMORY, 255 VIRT_GED_EVT_ADDR); 256 event = object_property_get_uint(OBJECT(lams->acpi_ged), 257 "ged-event", &error_abort); 258 if (event & ACPI_GED_MEM_HOTPLUG_EVT) { 259 build_memory_hotplug_aml(dsdt, machine->ram_slots, "\\_SB", NULL, 260 AML_SYSTEM_MEMORY, 261 VIRT_GED_MEM_ADDR); 262 } 263 } 264 265 static void build_pci_device_aml(Aml *scope, LoongArchMachineState *lams) 266 { 267 struct GPEXConfig cfg = { 268 .mmio64.base = VIRT_PCI_MEM_BASE, 269 .mmio64.size = VIRT_PCI_MEM_SIZE, 270 .pio.base = VIRT_PCI_IO_BASE, 271 .pio.size = VIRT_PCI_IO_SIZE, 272 .ecam.base = VIRT_PCI_CFG_BASE, 273 .ecam.size = VIRT_PCI_CFG_SIZE, 274 .irq = PCH_PIC_IRQ_OFFSET + VIRT_DEVICE_IRQS, 275 .bus = lams->pci_bus, 276 }; 277 278 acpi_dsdt_add_gpex(scope, &cfg); 279 } 280 281 static void build_flash_aml(Aml *scope, LoongArchMachineState *lams) 282 { 283 Aml *dev, *crs; 284 285 hwaddr flash_base = VIRT_FLASH_BASE; 286 hwaddr flash_size = VIRT_FLASH_SIZE; 287 288 dev = aml_device("FLS0"); 289 aml_append(dev, aml_name_decl("_HID", aml_string("LNRO0015"))); 290 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 291 292 crs = aml_resource_template(); 293 aml_append(crs, aml_memory32_fixed(flash_base, flash_size, AML_READ_WRITE)); 294 aml_append(dev, aml_name_decl("_CRS", crs)); 295 aml_append(scope, dev); 296 } 297 298 #ifdef CONFIG_TPM 299 static void acpi_dsdt_add_tpm(Aml *scope, LoongArchMachineState *vms) 300 { 301 PlatformBusDevice *pbus = PLATFORM_BUS_DEVICE(vms->platform_bus_dev); 302 hwaddr pbus_base = VIRT_PLATFORM_BUS_BASEADDRESS; 303 SysBusDevice *sbdev = SYS_BUS_DEVICE(tpm_find()); 304 MemoryRegion *sbdev_mr; 305 hwaddr tpm_base; 306 307 if (!sbdev) { 308 return; 309 } 310 311 tpm_base = platform_bus_get_mmio_addr(pbus, sbdev, 0); 312 assert(tpm_base != -1); 313 314 tpm_base += pbus_base; 315 316 sbdev_mr = sysbus_mmio_get_region(sbdev, 0); 317 318 Aml *dev = aml_device("TPM0"); 319 aml_append(dev, aml_name_decl("_HID", aml_string("MSFT0101"))); 320 aml_append(dev, aml_name_decl("_STR", aml_string("TPM 2.0 Device"))); 321 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 322 323 Aml *crs = aml_resource_template(); 324 aml_append(crs, 325 aml_memory32_fixed(tpm_base, 326 (uint32_t)memory_region_size(sbdev_mr), 327 AML_READ_WRITE)); 328 aml_append(dev, aml_name_decl("_CRS", crs)); 329 aml_append(scope, dev); 330 } 331 #endif 332 333 /* build DSDT */ 334 static void 335 build_dsdt(GArray *table_data, BIOSLinker *linker, MachineState *machine) 336 { 337 Aml *dsdt, *scope, *pkg; 338 LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); 339 AcpiTable table = { .sig = "DSDT", .rev = 1, .oem_id = lams->oem_id, 340 .oem_table_id = lams->oem_table_id }; 341 342 acpi_table_begin(&table, table_data); 343 dsdt = init_aml_allocator(); 344 build_uart_device_aml(dsdt); 345 build_pci_device_aml(dsdt, lams); 346 build_la_ged_aml(dsdt, machine); 347 build_flash_aml(dsdt, lams); 348 #ifdef CONFIG_TPM 349 acpi_dsdt_add_tpm(dsdt, lams); 350 #endif 351 /* System State Package */ 352 scope = aml_scope("\\"); 353 pkg = aml_package(4); 354 aml_append(pkg, aml_int(ACPI_GED_SLP_TYP_S5)); 355 aml_append(pkg, aml_int(0)); /* ignored */ 356 aml_append(pkg, aml_int(0)); /* reserved */ 357 aml_append(pkg, aml_int(0)); /* reserved */ 358 aml_append(scope, aml_name_decl("_S5", pkg)); 359 aml_append(dsdt, scope); 360 /* Copy AML table into ACPI tables blob and patch header there */ 361 g_array_append_vals(table_data, dsdt->buf->data, dsdt->buf->len); 362 acpi_table_end(linker, &table); 363 free_aml_allocator(); 364 } 365 366 static void acpi_build(AcpiBuildTables *tables, MachineState *machine) 367 { 368 LoongArchMachineState *lams = LOONGARCH_MACHINE(machine); 369 GArray *table_offsets; 370 AcpiFadtData fadt_data; 371 unsigned facs, rsdt, dsdt; 372 uint8_t *u; 373 GArray *tables_blob = tables->table_data; 374 375 init_common_fadt_data(&fadt_data); 376 377 table_offsets = g_array_new(false, true, sizeof(uint32_t)); 378 ACPI_BUILD_DPRINTF("init ACPI tables\n"); 379 380 bios_linker_loader_alloc(tables->linker, 381 ACPI_BUILD_TABLE_FILE, tables_blob, 382 64, false); 383 384 /* 385 * FACS is pointed to by FADT. 386 * We place it first since it's the only table that has alignment 387 * requirements. 388 */ 389 facs = tables_blob->len; 390 build_facs(tables_blob); 391 392 /* DSDT is pointed to by FADT */ 393 dsdt = tables_blob->len; 394 build_dsdt(tables_blob, tables->linker, machine); 395 396 /* ACPI tables pointed to by RSDT */ 397 acpi_add_table(table_offsets, tables_blob); 398 fadt_data.facs_tbl_offset = &facs; 399 fadt_data.dsdt_tbl_offset = &dsdt; 400 fadt_data.xdsdt_tbl_offset = &dsdt; 401 build_fadt(tables_blob, tables->linker, &fadt_data, 402 lams->oem_id, lams->oem_table_id); 403 404 acpi_add_table(table_offsets, tables_blob); 405 build_madt(tables_blob, tables->linker, lams); 406 407 acpi_add_table(table_offsets, tables_blob); 408 build_srat(tables_blob, tables->linker, machine); 409 410 acpi_add_table(table_offsets, tables_blob); 411 { 412 AcpiMcfgInfo mcfg = { 413 .base = cpu_to_le64(VIRT_PCI_CFG_BASE), 414 .size = cpu_to_le64(VIRT_PCI_CFG_SIZE), 415 }; 416 build_mcfg(tables_blob, tables->linker, &mcfg, lams->oem_id, 417 lams->oem_table_id); 418 } 419 420 #ifdef CONFIG_TPM 421 /* TPM info */ 422 if (tpm_get_version(tpm_find()) == TPM_VERSION_2_0) { 423 acpi_add_table(table_offsets, tables_blob); 424 build_tpm2(tables_blob, tables->linker, 425 tables->tcpalog, lams->oem_id, 426 lams->oem_table_id); 427 } 428 #endif 429 /* Add tables supplied by user (if any) */ 430 for (u = acpi_table_first(); u; u = acpi_table_next(u)) { 431 unsigned len = acpi_table_len(u); 432 433 acpi_add_table(table_offsets, tables_blob); 434 g_array_append_vals(tables_blob, u, len); 435 } 436 437 /* RSDT is pointed to by RSDP */ 438 rsdt = tables_blob->len; 439 build_rsdt(tables_blob, tables->linker, table_offsets, 440 lams->oem_id, lams->oem_table_id); 441 442 /* RSDP is in FSEG memory, so allocate it separately */ 443 { 444 AcpiRsdpData rsdp_data = { 445 .revision = 0, 446 .oem_id = lams->oem_id, 447 .xsdt_tbl_offset = NULL, 448 .rsdt_tbl_offset = &rsdt, 449 }; 450 build_rsdp(tables->rsdp, tables->linker, &rsdp_data); 451 } 452 453 /* 454 * The align size is 128, warn if 64k is not enough therefore 455 * the align size could be resized. 456 */ 457 if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { 458 warn_report("ACPI table size %u exceeds %d bytes," 459 " migration may not work", 460 tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); 461 error_printf("Try removing CPUs, NUMA nodes, memory slots" 462 " or PCI bridges."); 463 } 464 465 acpi_align_size(tables->linker->cmd_blob, ACPI_BUILD_ALIGN_SIZE); 466 467 /* Cleanup memory that's no longer used. */ 468 g_array_free(table_offsets, true); 469 } 470 471 static void acpi_ram_update(MemoryRegion *mr, GArray *data) 472 { 473 uint32_t size = acpi_data_len(data); 474 475 /* 476 * Make sure RAM size is correct - in case it got changed 477 * e.g. by migration 478 */ 479 memory_region_ram_resize(mr, size, &error_abort); 480 481 memcpy(memory_region_get_ram_ptr(mr), data->data, size); 482 memory_region_set_dirty(mr, 0, size); 483 } 484 485 static void acpi_build_update(void *build_opaque) 486 { 487 AcpiBuildState *build_state = build_opaque; 488 AcpiBuildTables tables; 489 490 /* No state to update or already patched? Nothing to do. */ 491 if (!build_state || build_state->patched) { 492 return; 493 } 494 build_state->patched = 1; 495 496 acpi_build_tables_init(&tables); 497 498 acpi_build(&tables, MACHINE(qdev_get_machine())); 499 500 acpi_ram_update(build_state->table_mr, tables.table_data); 501 acpi_ram_update(build_state->rsdp_mr, tables.rsdp); 502 acpi_ram_update(build_state->linker_mr, tables.linker->cmd_blob); 503 504 acpi_build_tables_cleanup(&tables, true); 505 } 506 507 static void acpi_build_reset(void *build_opaque) 508 { 509 AcpiBuildState *build_state = build_opaque; 510 build_state->patched = 0; 511 } 512 513 static const VMStateDescription vmstate_acpi_build = { 514 .name = "acpi_build", 515 .version_id = 1, 516 .minimum_version_id = 1, 517 .fields = (VMStateField[]) { 518 VMSTATE_UINT8(patched, AcpiBuildState), 519 VMSTATE_END_OF_LIST() 520 }, 521 }; 522 523 void loongarch_acpi_setup(LoongArchMachineState *lams) 524 { 525 AcpiBuildTables tables; 526 AcpiBuildState *build_state; 527 528 if (!lams->fw_cfg) { 529 ACPI_BUILD_DPRINTF("No fw cfg. Bailing out.\n"); 530 return; 531 } 532 533 if (!loongarch_is_acpi_enabled(lams)) { 534 ACPI_BUILD_DPRINTF("ACPI disabled. Bailing out.\n"); 535 return; 536 } 537 538 build_state = g_malloc0(sizeof *build_state); 539 540 acpi_build_tables_init(&tables); 541 acpi_build(&tables, MACHINE(lams)); 542 543 /* Now expose it all to Guest */ 544 build_state->table_mr = acpi_add_rom_blob(acpi_build_update, 545 build_state, tables.table_data, 546 ACPI_BUILD_TABLE_FILE); 547 assert(build_state->table_mr != NULL); 548 549 build_state->linker_mr = 550 acpi_add_rom_blob(acpi_build_update, build_state, 551 tables.linker->cmd_blob, ACPI_BUILD_LOADER_FILE); 552 553 build_state->rsdp_mr = acpi_add_rom_blob(acpi_build_update, 554 build_state, tables.rsdp, 555 ACPI_BUILD_RSDP_FILE); 556 557 qemu_register_reset(acpi_build_reset, build_state); 558 acpi_build_reset(build_state); 559 vmstate_register(NULL, 0, &vmstate_acpi_build, build_state); 560 561 /* 562 * Cleanup tables but don't free the memory: we track it 563 * in build_state. 564 */ 565 acpi_build_tables_cleanup(&tables, false); 566 } 567