1 /* 2 * VT82C686B south bridge support 3 * 4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org) 5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) 6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) 7 * This code is licensed under the GNU GPL v2. 8 * 9 * Contributions after 2012-01-13 are licensed under the terms of the 10 * GNU GPL, version 2 or (at your option) any later version. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "hw/isa/vt82c686.h" 15 #include "hw/pci/pci.h" 16 #include "hw/qdev-properties.h" 17 #include "hw/isa/isa.h" 18 #include "hw/isa/superio.h" 19 #include "hw/intc/i8259.h" 20 #include "hw/irq.h" 21 #include "hw/dma/i8257.h" 22 #include "hw/timer/i8254.h" 23 #include "hw/rtc/mc146818rtc.h" 24 #include "migration/vmstate.h" 25 #include "hw/isa/apm.h" 26 #include "hw/acpi/acpi.h" 27 #include "hw/i2c/pm_smbus.h" 28 #include "qapi/error.h" 29 #include "qemu/log.h" 30 #include "qemu/module.h" 31 #include "qemu/range.h" 32 #include "qemu/timer.h" 33 #include "trace.h" 34 35 #define TYPE_VIA_PM "via-pm" 36 OBJECT_DECLARE_SIMPLE_TYPE(ViaPMState, VIA_PM) 37 38 struct ViaPMState { 39 PCIDevice dev; 40 MemoryRegion io; 41 ACPIREGS ar; 42 APMState apm; 43 PMSMBus smb; 44 }; 45 46 static void pm_io_space_update(ViaPMState *s) 47 { 48 uint32_t pmbase = pci_get_long(s->dev.config + 0x48) & 0xff80UL; 49 50 memory_region_transaction_begin(); 51 memory_region_set_address(&s->io, pmbase); 52 memory_region_set_enabled(&s->io, s->dev.config[0x41] & BIT(7)); 53 memory_region_transaction_commit(); 54 } 55 56 static void smb_io_space_update(ViaPMState *s) 57 { 58 uint32_t smbase = pci_get_long(s->dev.config + 0x90) & 0xfff0UL; 59 60 memory_region_transaction_begin(); 61 memory_region_set_address(&s->smb.io, smbase); 62 memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & BIT(0)); 63 memory_region_transaction_commit(); 64 } 65 66 static int vmstate_acpi_post_load(void *opaque, int version_id) 67 { 68 ViaPMState *s = opaque; 69 70 pm_io_space_update(s); 71 smb_io_space_update(s); 72 return 0; 73 } 74 75 static const VMStateDescription vmstate_acpi = { 76 .name = "vt82c686b_pm", 77 .version_id = 1, 78 .minimum_version_id = 1, 79 .post_load = vmstate_acpi_post_load, 80 .fields = (VMStateField[]) { 81 VMSTATE_PCI_DEVICE(dev, ViaPMState), 82 VMSTATE_UINT16(ar.pm1.evt.sts, ViaPMState), 83 VMSTATE_UINT16(ar.pm1.evt.en, ViaPMState), 84 VMSTATE_UINT16(ar.pm1.cnt.cnt, ViaPMState), 85 VMSTATE_STRUCT(apm, ViaPMState, 0, vmstate_apm, APMState), 86 VMSTATE_TIMER_PTR(ar.tmr.timer, ViaPMState), 87 VMSTATE_INT64(ar.tmr.overflow_time, ViaPMState), 88 VMSTATE_END_OF_LIST() 89 } 90 }; 91 92 static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len) 93 { 94 ViaPMState *s = VIA_PM(d); 95 96 trace_via_pm_write(addr, val, len); 97 pci_default_write_config(d, addr, val, len); 98 if (ranges_overlap(addr, len, 0x48, 4)) { 99 uint32_t v = pci_get_long(s->dev.config + 0x48); 100 pci_set_long(s->dev.config + 0x48, (v & 0xff80UL) | 1); 101 } 102 if (range_covers_byte(addr, len, 0x41)) { 103 pm_io_space_update(s); 104 } 105 if (ranges_overlap(addr, len, 0x90, 4)) { 106 uint32_t v = pci_get_long(s->dev.config + 0x90); 107 pci_set_long(s->dev.config + 0x90, (v & 0xfff0UL) | 1); 108 } 109 if (range_covers_byte(addr, len, 0xd2)) { 110 s->dev.config[0xd2] &= 0xf; 111 smb_io_space_update(s); 112 } 113 } 114 115 static void pm_io_write(void *op, hwaddr addr, uint64_t data, unsigned size) 116 { 117 trace_via_pm_io_write(addr, data, size); 118 } 119 120 static uint64_t pm_io_read(void *op, hwaddr addr, unsigned size) 121 { 122 trace_via_pm_io_read(addr, 0, size); 123 return 0; 124 } 125 126 static const MemoryRegionOps pm_io_ops = { 127 .read = pm_io_read, 128 .write = pm_io_write, 129 .endianness = DEVICE_NATIVE_ENDIAN, 130 .impl = { 131 .min_access_size = 1, 132 .max_access_size = 1, 133 }, 134 }; 135 136 static void pm_update_sci(ViaPMState *s) 137 { 138 int sci_level, pmsts; 139 140 pmsts = acpi_pm1_evt_get_sts(&s->ar); 141 sci_level = (((pmsts & s->ar.pm1.evt.en) & 142 (ACPI_BITMASK_RT_CLOCK_ENABLE | 143 ACPI_BITMASK_POWER_BUTTON_ENABLE | 144 ACPI_BITMASK_GLOBAL_LOCK_ENABLE | 145 ACPI_BITMASK_TIMER_ENABLE)) != 0); 146 if (pci_get_byte(s->dev.config + PCI_INTERRUPT_PIN)) { 147 /* 148 * FIXME: 149 * Fix device model that realizes this PM device and remove 150 * this work around. 151 * The device model should wire SCI and setup 152 * PCI_INTERRUPT_PIN properly. 153 * If PIN# = 0(interrupt pin isn't used), don't raise SCI as 154 * work around. 155 */ 156 pci_set_irq(&s->dev, sci_level); 157 } 158 /* schedule a timer interruption if needed */ 159 acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && 160 !(pmsts & ACPI_BITMASK_TIMER_STATUS)); 161 } 162 163 static void pm_tmr_timer(ACPIREGS *ar) 164 { 165 ViaPMState *s = container_of(ar, ViaPMState, ar); 166 pm_update_sci(s); 167 } 168 169 static void via_pm_reset(DeviceState *d) 170 { 171 ViaPMState *s = VIA_PM(d); 172 173 memset(s->dev.config + PCI_CONFIG_HEADER_SIZE, 0, 174 PCI_CONFIG_SPACE_SIZE - PCI_CONFIG_HEADER_SIZE); 175 /* Power Management IO base */ 176 pci_set_long(s->dev.config + 0x48, 1); 177 /* SMBus IO base */ 178 pci_set_long(s->dev.config + 0x90, 1); 179 180 acpi_pm1_evt_reset(&s->ar); 181 acpi_pm1_cnt_reset(&s->ar); 182 acpi_pm_tmr_reset(&s->ar); 183 pm_update_sci(s); 184 185 pm_io_space_update(s); 186 smb_io_space_update(s); 187 } 188 189 static void via_pm_realize(PCIDevice *dev, Error **errp) 190 { 191 ViaPMState *s = VIA_PM(dev); 192 193 pci_set_word(dev->config + PCI_STATUS, PCI_STATUS_FAST_BACK | 194 PCI_STATUS_DEVSEL_MEDIUM); 195 196 pm_smbus_init(DEVICE(s), &s->smb, false); 197 memory_region_add_subregion(pci_address_space_io(dev), 0, &s->smb.io); 198 memory_region_set_enabled(&s->smb.io, false); 199 200 apm_init(dev, &s->apm, NULL, s); 201 202 memory_region_init_io(&s->io, OBJECT(dev), &pm_io_ops, s, "via-pm", 128); 203 memory_region_add_subregion(pci_address_space_io(dev), 0, &s->io); 204 memory_region_set_enabled(&s->io, false); 205 206 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 207 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 208 acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2, false); 209 } 210 211 typedef struct via_pm_init_info { 212 uint16_t device_id; 213 } ViaPMInitInfo; 214 215 static void via_pm_class_init(ObjectClass *klass, void *data) 216 { 217 DeviceClass *dc = DEVICE_CLASS(klass); 218 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 219 ViaPMInitInfo *info = data; 220 221 k->realize = via_pm_realize; 222 k->config_write = pm_write_config; 223 k->vendor_id = PCI_VENDOR_ID_VIA; 224 k->device_id = info->device_id; 225 k->class_id = PCI_CLASS_BRIDGE_OTHER; 226 k->revision = 0x40; 227 dc->reset = via_pm_reset; 228 /* Reason: part of VIA south bridge, does not exist stand alone */ 229 dc->user_creatable = false; 230 dc->vmsd = &vmstate_acpi; 231 } 232 233 static const TypeInfo via_pm_info = { 234 .name = TYPE_VIA_PM, 235 .parent = TYPE_PCI_DEVICE, 236 .instance_size = sizeof(ViaPMState), 237 .abstract = true, 238 .interfaces = (InterfaceInfo[]) { 239 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 240 { }, 241 }, 242 }; 243 244 static const ViaPMInitInfo vt82c686b_pm_init_info = { 245 .device_id = PCI_DEVICE_ID_VIA_82C686B_PM, 246 }; 247 248 static const TypeInfo vt82c686b_pm_info = { 249 .name = TYPE_VT82C686B_PM, 250 .parent = TYPE_VIA_PM, 251 .class_init = via_pm_class_init, 252 .class_data = (void *)&vt82c686b_pm_init_info, 253 }; 254 255 static const ViaPMInitInfo vt8231_pm_init_info = { 256 .device_id = PCI_DEVICE_ID_VIA_8231_PM, 257 }; 258 259 static const TypeInfo vt8231_pm_info = { 260 .name = TYPE_VT8231_PM, 261 .parent = TYPE_VIA_PM, 262 .class_init = via_pm_class_init, 263 .class_data = (void *)&vt8231_pm_init_info, 264 }; 265 266 267 typedef struct SuperIOConfig { 268 uint8_t regs[0x100]; 269 MemoryRegion io; 270 } SuperIOConfig; 271 272 static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data, 273 unsigned size) 274 { 275 SuperIOConfig *sc = opaque; 276 uint8_t idx = sc->regs[0]; 277 278 if (addr == 0) { /* config index register */ 279 sc->regs[0] = data; 280 return; 281 } 282 283 /* config data register */ 284 trace_via_superio_write(idx, data); 285 switch (idx) { 286 case 0x00 ... 0xdf: 287 case 0xe4: 288 case 0xe5: 289 case 0xe9 ... 0xed: 290 case 0xf3: 291 case 0xf5: 292 case 0xf7: 293 case 0xf9 ... 0xfb: 294 case 0xfd ... 0xff: 295 /* ignore write to read only registers */ 296 return; 297 /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */ 298 default: 299 qemu_log_mask(LOG_UNIMP, 300 "via_superio_cfg: unimplemented register 0x%x\n", idx); 301 break; 302 } 303 sc->regs[idx] = data; 304 } 305 306 static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size) 307 { 308 SuperIOConfig *sc = opaque; 309 uint8_t idx = sc->regs[0]; 310 uint8_t val = sc->regs[idx]; 311 312 if (addr == 0) { 313 return idx; 314 } 315 if (addr == 1 && idx == 0) { 316 val = 0; /* reading reg 0 where we store index value */ 317 } 318 trace_via_superio_read(idx, val); 319 return val; 320 } 321 322 static const MemoryRegionOps superio_cfg_ops = { 323 .read = superio_cfg_read, 324 .write = superio_cfg_write, 325 .endianness = DEVICE_NATIVE_ENDIAN, 326 .impl = { 327 .min_access_size = 1, 328 .max_access_size = 1, 329 }, 330 }; 331 332 333 OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA) 334 335 struct VT82C686BISAState { 336 PCIDevice dev; 337 qemu_irq cpu_intr; 338 SuperIOConfig superio_cfg; 339 }; 340 341 static void via_isa_request_i8259_irq(void *opaque, int irq, int level) 342 { 343 VT82C686BISAState *s = opaque; 344 qemu_set_irq(s->cpu_intr, level); 345 } 346 347 static void vt82c686b_write_config(PCIDevice *d, uint32_t addr, 348 uint32_t val, int len) 349 { 350 VT82C686BISAState *s = VT82C686B_ISA(d); 351 352 trace_via_isa_write(addr, val, len); 353 pci_default_write_config(d, addr, val, len); 354 if (addr == 0x85) { 355 /* BIT(1): enable or disable superio config io ports */ 356 memory_region_set_enabled(&s->superio_cfg.io, val & BIT(1)); 357 } 358 } 359 360 static const VMStateDescription vmstate_via = { 361 .name = "vt82c686b", 362 .version_id = 1, 363 .minimum_version_id = 1, 364 .fields = (VMStateField[]) { 365 VMSTATE_PCI_DEVICE(dev, VT82C686BISAState), 366 VMSTATE_END_OF_LIST() 367 } 368 }; 369 370 static void vt82c686b_isa_reset(DeviceState *dev) 371 { 372 VT82C686BISAState *s = VT82C686B_ISA(dev); 373 uint8_t *pci_conf = s->dev.config; 374 375 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); 376 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 377 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); 378 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); 379 380 pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ 381 pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ 382 pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ 383 pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ 384 pci_conf[0x59] = 0x04; 385 pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ 386 pci_conf[0x5f] = 0x04; 387 pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ 388 389 s->superio_cfg.regs[0xe0] = 0x3c; /* Device ID */ 390 s->superio_cfg.regs[0xe2] = 0x03; /* Function select */ 391 s->superio_cfg.regs[0xe3] = 0xfc; /* Floppy ctrl base addr */ 392 s->superio_cfg.regs[0xe6] = 0xde; /* Parallel port base addr */ 393 s->superio_cfg.regs[0xe7] = 0xfe; /* Serial port 1 base addr */ 394 s->superio_cfg.regs[0xe8] = 0xbe; /* Serial port 2 base addr */ 395 } 396 397 static void vt82c686b_realize(PCIDevice *d, Error **errp) 398 { 399 VT82C686BISAState *s = VT82C686B_ISA(d); 400 DeviceState *dev = DEVICE(d); 401 ISABus *isa_bus; 402 qemu_irq *isa_irq; 403 int i; 404 405 qdev_init_gpio_out(dev, &s->cpu_intr, 1); 406 isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1); 407 isa_bus = isa_bus_new(dev, get_system_memory(), pci_address_space_io(d), 408 &error_fatal); 409 isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq)); 410 i8254_pit_init(isa_bus, 0x40, 0, NULL); 411 i8257_dma_init(isa_bus, 0); 412 isa_create_simple(isa_bus, TYPE_VT82C686B_SUPERIO); 413 mc146818_rtc_init(isa_bus, 2000, NULL); 414 415 for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) { 416 if (i < PCI_COMMAND || i >= PCI_REVISION_ID) { 417 d->wmask[i] = 0; 418 } 419 } 420 421 memory_region_init_io(&s->superio_cfg.io, OBJECT(d), &superio_cfg_ops, 422 &s->superio_cfg, "superio_cfg", 2); 423 memory_region_set_enabled(&s->superio_cfg.io, false); 424 /* 425 * The floppy also uses 0x3f0 and 0x3f1. 426 * But we do not emulate a floppy, so just set it here. 427 */ 428 memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, 429 &s->superio_cfg.io); 430 } 431 432 static void via_class_init(ObjectClass *klass, void *data) 433 { 434 DeviceClass *dc = DEVICE_CLASS(klass); 435 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 436 437 k->realize = vt82c686b_realize; 438 k->config_write = vt82c686b_write_config; 439 k->vendor_id = PCI_VENDOR_ID_VIA; 440 k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; 441 k->class_id = PCI_CLASS_BRIDGE_ISA; 442 k->revision = 0x40; 443 dc->reset = vt82c686b_isa_reset; 444 dc->desc = "ISA bridge"; 445 dc->vmsd = &vmstate_via; 446 /* 447 * Reason: part of VIA VT82C686 southbridge, needs to be wired up, 448 * e.g. by mips_fuloong2e_init() 449 */ 450 dc->user_creatable = false; 451 } 452 453 static const TypeInfo via_info = { 454 .name = TYPE_VT82C686B_ISA, 455 .parent = TYPE_PCI_DEVICE, 456 .instance_size = sizeof(VT82C686BISAState), 457 .class_init = via_class_init, 458 .interfaces = (InterfaceInfo[]) { 459 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 460 { }, 461 }, 462 }; 463 464 465 static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) 466 { 467 ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); 468 469 sc->serial.count = 2; 470 sc->parallel.count = 1; 471 sc->ide.count = 0; 472 sc->floppy.count = 1; 473 } 474 475 static const TypeInfo via_superio_info = { 476 .name = TYPE_VT82C686B_SUPERIO, 477 .parent = TYPE_ISA_SUPERIO, 478 .instance_size = sizeof(ISASuperIODevice), 479 .class_size = sizeof(ISASuperIOClass), 480 .class_init = vt82c686b_superio_class_init, 481 }; 482 483 484 static void vt82c686b_register_types(void) 485 { 486 type_register_static(&via_pm_info); 487 type_register_static(&vt82c686b_pm_info); 488 type_register_static(&vt8231_pm_info); 489 type_register_static(&via_info); 490 type_register_static(&via_superio_info); 491 } 492 493 type_init(vt82c686b_register_types) 494