1 /* 2 * VT82C686B south bridge support 3 * 4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org) 5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) 6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) 7 * This code is licensed under the GNU GPL v2. 8 * 9 * Contributions after 2012-01-13 are licensed under the terms of the 10 * GNU GPL, version 2 or (at your option) any later version. 11 * 12 * VT8231 south bridge support and general clean up to allow it 13 * Copyright (c) 2018-2020 BALATON Zoltan 14 */ 15 16 #include "qemu/osdep.h" 17 #include "hw/isa/vt82c686.h" 18 #include "hw/pci/pci.h" 19 #include "hw/qdev-properties.h" 20 #include "hw/isa/isa.h" 21 #include "hw/isa/superio.h" 22 #include "hw/intc/i8259.h" 23 #include "hw/irq.h" 24 #include "hw/dma/i8257.h" 25 #include "hw/timer/i8254.h" 26 #include "hw/rtc/mc146818rtc.h" 27 #include "migration/vmstate.h" 28 #include "hw/isa/apm.h" 29 #include "hw/acpi/acpi.h" 30 #include "hw/i2c/pm_smbus.h" 31 #include "qapi/error.h" 32 #include "qemu/log.h" 33 #include "qemu/module.h" 34 #include "qemu/range.h" 35 #include "qemu/timer.h" 36 #include "trace.h" 37 38 #define TYPE_VIA_PM "via-pm" 39 OBJECT_DECLARE_SIMPLE_TYPE(ViaPMState, VIA_PM) 40 41 struct ViaPMState { 42 PCIDevice dev; 43 MemoryRegion io; 44 ACPIREGS ar; 45 APMState apm; 46 PMSMBus smb; 47 }; 48 49 static void pm_io_space_update(ViaPMState *s) 50 { 51 uint32_t pmbase = pci_get_long(s->dev.config + 0x48) & 0xff80UL; 52 53 memory_region_transaction_begin(); 54 memory_region_set_address(&s->io, pmbase); 55 memory_region_set_enabled(&s->io, s->dev.config[0x41] & BIT(7)); 56 memory_region_transaction_commit(); 57 } 58 59 static void smb_io_space_update(ViaPMState *s) 60 { 61 uint32_t smbase = pci_get_long(s->dev.config + 0x90) & 0xfff0UL; 62 63 memory_region_transaction_begin(); 64 memory_region_set_address(&s->smb.io, smbase); 65 memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & BIT(0)); 66 memory_region_transaction_commit(); 67 } 68 69 static int vmstate_acpi_post_load(void *opaque, int version_id) 70 { 71 ViaPMState *s = opaque; 72 73 pm_io_space_update(s); 74 smb_io_space_update(s); 75 return 0; 76 } 77 78 static const VMStateDescription vmstate_acpi = { 79 .name = "vt82c686b_pm", 80 .version_id = 1, 81 .minimum_version_id = 1, 82 .post_load = vmstate_acpi_post_load, 83 .fields = (VMStateField[]) { 84 VMSTATE_PCI_DEVICE(dev, ViaPMState), 85 VMSTATE_UINT16(ar.pm1.evt.sts, ViaPMState), 86 VMSTATE_UINT16(ar.pm1.evt.en, ViaPMState), 87 VMSTATE_UINT16(ar.pm1.cnt.cnt, ViaPMState), 88 VMSTATE_STRUCT(apm, ViaPMState, 0, vmstate_apm, APMState), 89 VMSTATE_TIMER_PTR(ar.tmr.timer, ViaPMState), 90 VMSTATE_INT64(ar.tmr.overflow_time, ViaPMState), 91 VMSTATE_END_OF_LIST() 92 } 93 }; 94 95 static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len) 96 { 97 ViaPMState *s = VIA_PM(d); 98 99 trace_via_pm_write(addr, val, len); 100 pci_default_write_config(d, addr, val, len); 101 if (ranges_overlap(addr, len, 0x48, 4)) { 102 uint32_t v = pci_get_long(s->dev.config + 0x48); 103 pci_set_long(s->dev.config + 0x48, (v & 0xff80UL) | 1); 104 } 105 if (range_covers_byte(addr, len, 0x41)) { 106 pm_io_space_update(s); 107 } 108 if (ranges_overlap(addr, len, 0x90, 4)) { 109 uint32_t v = pci_get_long(s->dev.config + 0x90); 110 pci_set_long(s->dev.config + 0x90, (v & 0xfff0UL) | 1); 111 } 112 if (range_covers_byte(addr, len, 0xd2)) { 113 s->dev.config[0xd2] &= 0xf; 114 smb_io_space_update(s); 115 } 116 } 117 118 static void pm_io_write(void *op, hwaddr addr, uint64_t data, unsigned size) 119 { 120 trace_via_pm_io_write(addr, data, size); 121 } 122 123 static uint64_t pm_io_read(void *op, hwaddr addr, unsigned size) 124 { 125 trace_via_pm_io_read(addr, 0, size); 126 return 0; 127 } 128 129 static const MemoryRegionOps pm_io_ops = { 130 .read = pm_io_read, 131 .write = pm_io_write, 132 .endianness = DEVICE_NATIVE_ENDIAN, 133 .impl = { 134 .min_access_size = 1, 135 .max_access_size = 1, 136 }, 137 }; 138 139 static void pm_update_sci(ViaPMState *s) 140 { 141 int sci_level, pmsts; 142 143 pmsts = acpi_pm1_evt_get_sts(&s->ar); 144 sci_level = (((pmsts & s->ar.pm1.evt.en) & 145 (ACPI_BITMASK_RT_CLOCK_ENABLE | 146 ACPI_BITMASK_POWER_BUTTON_ENABLE | 147 ACPI_BITMASK_GLOBAL_LOCK_ENABLE | 148 ACPI_BITMASK_TIMER_ENABLE)) != 0); 149 if (pci_get_byte(s->dev.config + PCI_INTERRUPT_PIN)) { 150 /* 151 * FIXME: 152 * Fix device model that realizes this PM device and remove 153 * this work around. 154 * The device model should wire SCI and setup 155 * PCI_INTERRUPT_PIN properly. 156 * If PIN# = 0(interrupt pin isn't used), don't raise SCI as 157 * work around. 158 */ 159 pci_set_irq(&s->dev, sci_level); 160 } 161 /* schedule a timer interruption if needed */ 162 acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && 163 !(pmsts & ACPI_BITMASK_TIMER_STATUS)); 164 } 165 166 static void pm_tmr_timer(ACPIREGS *ar) 167 { 168 ViaPMState *s = container_of(ar, ViaPMState, ar); 169 pm_update_sci(s); 170 } 171 172 static void via_pm_reset(DeviceState *d) 173 { 174 ViaPMState *s = VIA_PM(d); 175 176 memset(s->dev.config + PCI_CONFIG_HEADER_SIZE, 0, 177 PCI_CONFIG_SPACE_SIZE - PCI_CONFIG_HEADER_SIZE); 178 /* Power Management IO base */ 179 pci_set_long(s->dev.config + 0x48, 1); 180 /* SMBus IO base */ 181 pci_set_long(s->dev.config + 0x90, 1); 182 183 acpi_pm1_evt_reset(&s->ar); 184 acpi_pm1_cnt_reset(&s->ar); 185 acpi_pm_tmr_reset(&s->ar); 186 pm_update_sci(s); 187 188 pm_io_space_update(s); 189 smb_io_space_update(s); 190 } 191 192 static void via_pm_realize(PCIDevice *dev, Error **errp) 193 { 194 ViaPMState *s = VIA_PM(dev); 195 196 pci_set_word(dev->config + PCI_STATUS, PCI_STATUS_FAST_BACK | 197 PCI_STATUS_DEVSEL_MEDIUM); 198 199 pm_smbus_init(DEVICE(s), &s->smb, false); 200 memory_region_add_subregion(pci_address_space_io(dev), 0, &s->smb.io); 201 memory_region_set_enabled(&s->smb.io, false); 202 203 apm_init(dev, &s->apm, NULL, s); 204 205 memory_region_init_io(&s->io, OBJECT(dev), &pm_io_ops, s, "via-pm", 128); 206 memory_region_add_subregion(pci_address_space_io(dev), 0, &s->io); 207 memory_region_set_enabled(&s->io, false); 208 209 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 210 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 211 acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2, false); 212 } 213 214 typedef struct via_pm_init_info { 215 uint16_t device_id; 216 } ViaPMInitInfo; 217 218 static void via_pm_class_init(ObjectClass *klass, void *data) 219 { 220 DeviceClass *dc = DEVICE_CLASS(klass); 221 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 222 ViaPMInitInfo *info = data; 223 224 k->realize = via_pm_realize; 225 k->config_write = pm_write_config; 226 k->vendor_id = PCI_VENDOR_ID_VIA; 227 k->device_id = info->device_id; 228 k->class_id = PCI_CLASS_BRIDGE_OTHER; 229 k->revision = 0x40; 230 dc->reset = via_pm_reset; 231 /* Reason: part of VIA south bridge, does not exist stand alone */ 232 dc->user_creatable = false; 233 dc->vmsd = &vmstate_acpi; 234 } 235 236 static const TypeInfo via_pm_info = { 237 .name = TYPE_VIA_PM, 238 .parent = TYPE_PCI_DEVICE, 239 .instance_size = sizeof(ViaPMState), 240 .abstract = true, 241 .interfaces = (InterfaceInfo[]) { 242 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 243 { }, 244 }, 245 }; 246 247 static const ViaPMInitInfo vt82c686b_pm_init_info = { 248 .device_id = PCI_DEVICE_ID_VIA_82C686B_PM, 249 }; 250 251 static const TypeInfo vt82c686b_pm_info = { 252 .name = TYPE_VT82C686B_PM, 253 .parent = TYPE_VIA_PM, 254 .class_init = via_pm_class_init, 255 .class_data = (void *)&vt82c686b_pm_init_info, 256 }; 257 258 static const ViaPMInitInfo vt8231_pm_init_info = { 259 .device_id = PCI_DEVICE_ID_VIA_8231_PM, 260 }; 261 262 static const TypeInfo vt8231_pm_info = { 263 .name = TYPE_VT8231_PM, 264 .parent = TYPE_VIA_PM, 265 .class_init = via_pm_class_init, 266 .class_data = (void *)&vt8231_pm_init_info, 267 }; 268 269 270 #define TYPE_VIA_SUPERIO "via-superio" 271 OBJECT_DECLARE_SIMPLE_TYPE(ViaSuperIOState, VIA_SUPERIO) 272 273 struct ViaSuperIOState { 274 ISASuperIODevice superio; 275 uint8_t regs[0x100]; 276 const MemoryRegionOps *io_ops; 277 MemoryRegion io; 278 }; 279 280 static inline void via_superio_io_enable(ViaSuperIOState *s, bool enable) 281 { 282 memory_region_set_enabled(&s->io, enable); 283 } 284 285 static void via_superio_realize(DeviceState *d, Error **errp) 286 { 287 ViaSuperIOState *s = VIA_SUPERIO(d); 288 ISASuperIOClass *ic = ISA_SUPERIO_GET_CLASS(s); 289 Error *local_err = NULL; 290 291 assert(s->io_ops); 292 ic->parent_realize(d, &local_err); 293 if (local_err) { 294 error_propagate(errp, local_err); 295 return; 296 } 297 memory_region_init_io(&s->io, OBJECT(d), s->io_ops, s, "via-superio", 2); 298 memory_region_set_enabled(&s->io, false); 299 /* The floppy also uses 0x3f0 and 0x3f1 but this seems to work anyway */ 300 memory_region_add_subregion(isa_address_space_io(ISA_DEVICE(s)), 0x3f0, 301 &s->io); 302 } 303 304 static uint64_t via_superio_cfg_read(void *opaque, hwaddr addr, unsigned size) 305 { 306 ViaSuperIOState *sc = opaque; 307 uint8_t idx = sc->regs[0]; 308 uint8_t val = sc->regs[idx]; 309 310 if (addr == 0) { 311 return idx; 312 } 313 if (addr == 1 && idx == 0) { 314 val = 0; /* reading reg 0 where we store index value */ 315 } 316 trace_via_superio_read(idx, val); 317 return val; 318 } 319 320 static void via_superio_class_init(ObjectClass *klass, void *data) 321 { 322 DeviceClass *dc = DEVICE_CLASS(klass); 323 ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); 324 325 sc->parent_realize = dc->realize; 326 dc->realize = via_superio_realize; 327 } 328 329 static const TypeInfo via_superio_info = { 330 .name = TYPE_VIA_SUPERIO, 331 .parent = TYPE_ISA_SUPERIO, 332 .instance_size = sizeof(ViaSuperIOState), 333 .class_size = sizeof(ISASuperIOClass), 334 .class_init = via_superio_class_init, 335 .abstract = true, 336 }; 337 338 #define TYPE_VT82C686B_SUPERIO "vt82c686b-superio" 339 340 static void vt82c686b_superio_cfg_write(void *opaque, hwaddr addr, 341 uint64_t data, unsigned size) 342 { 343 ViaSuperIOState *sc = opaque; 344 uint8_t idx = sc->regs[0]; 345 346 if (addr == 0) { /* config index register */ 347 sc->regs[0] = data; 348 return; 349 } 350 351 /* config data register */ 352 trace_via_superio_write(idx, data); 353 switch (idx) { 354 case 0x00 ... 0xdf: 355 case 0xe4: 356 case 0xe5: 357 case 0xe9 ... 0xed: 358 case 0xf3: 359 case 0xf5: 360 case 0xf7: 361 case 0xf9 ... 0xfb: 362 case 0xfd ... 0xff: 363 /* ignore write to read only registers */ 364 return; 365 /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */ 366 default: 367 qemu_log_mask(LOG_UNIMP, 368 "via_superio_cfg: unimplemented register 0x%x\n", idx); 369 break; 370 } 371 sc->regs[idx] = data; 372 } 373 374 static const MemoryRegionOps vt82c686b_superio_cfg_ops = { 375 .read = via_superio_cfg_read, 376 .write = vt82c686b_superio_cfg_write, 377 .endianness = DEVICE_NATIVE_ENDIAN, 378 .impl = { 379 .min_access_size = 1, 380 .max_access_size = 1, 381 }, 382 }; 383 384 static void vt82c686b_superio_reset(DeviceState *dev) 385 { 386 ViaSuperIOState *s = VIA_SUPERIO(dev); 387 388 memset(s->regs, 0, sizeof(s->regs)); 389 /* Device ID */ 390 vt82c686b_superio_cfg_write(s, 0, 0xe0, 1); 391 vt82c686b_superio_cfg_write(s, 1, 0x3c, 1); 392 /* Function select - all disabled */ 393 vt82c686b_superio_cfg_write(s, 0, 0xe2, 1); 394 vt82c686b_superio_cfg_write(s, 1, 0x03, 1); 395 /* Floppy ctrl base addr 0x3f0-7 */ 396 vt82c686b_superio_cfg_write(s, 0, 0xe3, 1); 397 vt82c686b_superio_cfg_write(s, 1, 0xfc, 1); 398 /* Parallel port base addr 0x378-f */ 399 vt82c686b_superio_cfg_write(s, 0, 0xe6, 1); 400 vt82c686b_superio_cfg_write(s, 1, 0xde, 1); 401 /* Serial port 1 base addr 0x3f8-f */ 402 vt82c686b_superio_cfg_write(s, 0, 0xe7, 1); 403 vt82c686b_superio_cfg_write(s, 1, 0xfe, 1); 404 /* Serial port 2 base addr 0x2f8-f */ 405 vt82c686b_superio_cfg_write(s, 0, 0xe8, 1); 406 vt82c686b_superio_cfg_write(s, 1, 0xbe, 1); 407 408 vt82c686b_superio_cfg_write(s, 0, 0, 1); 409 } 410 411 static void vt82c686b_superio_init(Object *obj) 412 { 413 VIA_SUPERIO(obj)->io_ops = &vt82c686b_superio_cfg_ops; 414 } 415 416 static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) 417 { 418 DeviceClass *dc = DEVICE_CLASS(klass); 419 ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); 420 421 dc->reset = vt82c686b_superio_reset; 422 sc->serial.count = 2; 423 sc->parallel.count = 1; 424 sc->ide.count = 0; /* emulated by via-ide */ 425 sc->floppy.count = 1; 426 } 427 428 static const TypeInfo vt82c686b_superio_info = { 429 .name = TYPE_VT82C686B_SUPERIO, 430 .parent = TYPE_VIA_SUPERIO, 431 .instance_size = sizeof(ViaSuperIOState), 432 .instance_init = vt82c686b_superio_init, 433 .class_size = sizeof(ISASuperIOClass), 434 .class_init = vt82c686b_superio_class_init, 435 }; 436 437 438 #define TYPE_VT8231_SUPERIO "vt8231-superio" 439 440 static void vt8231_superio_cfg_write(void *opaque, hwaddr addr, 441 uint64_t data, unsigned size) 442 { 443 ViaSuperIOState *sc = opaque; 444 uint8_t idx = sc->regs[0]; 445 446 if (addr == 0) { /* config index register */ 447 sc->regs[0] = data; 448 return; 449 } 450 451 /* config data register */ 452 trace_via_superio_write(idx, data); 453 switch (idx) { 454 case 0x00 ... 0xdf: 455 case 0xe7 ... 0xef: 456 case 0xf0 ... 0xf1: 457 case 0xf5: 458 case 0xf8: 459 case 0xfd: 460 /* ignore write to read only registers */ 461 return; 462 default: 463 qemu_log_mask(LOG_UNIMP, 464 "via_superio_cfg: unimplemented register 0x%x\n", idx); 465 break; 466 } 467 sc->regs[idx] = data; 468 } 469 470 static const MemoryRegionOps vt8231_superio_cfg_ops = { 471 .read = via_superio_cfg_read, 472 .write = vt8231_superio_cfg_write, 473 .endianness = DEVICE_NATIVE_ENDIAN, 474 .impl = { 475 .min_access_size = 1, 476 .max_access_size = 1, 477 }, 478 }; 479 480 static void vt8231_superio_reset(DeviceState *dev) 481 { 482 ViaSuperIOState *s = VIA_SUPERIO(dev); 483 484 memset(s->regs, 0, sizeof(s->regs)); 485 /* Device ID */ 486 s->regs[0xf0] = 0x3c; 487 /* Device revision */ 488 s->regs[0xf1] = 0x01; 489 /* Function select - all disabled */ 490 vt8231_superio_cfg_write(s, 0, 0xf2, 1); 491 vt8231_superio_cfg_write(s, 1, 0x03, 1); 492 /* Serial port base addr */ 493 vt8231_superio_cfg_write(s, 0, 0xf4, 1); 494 vt8231_superio_cfg_write(s, 1, 0xfe, 1); 495 /* Parallel port base addr */ 496 vt8231_superio_cfg_write(s, 0, 0xf6, 1); 497 vt8231_superio_cfg_write(s, 1, 0xde, 1); 498 /* Floppy ctrl base addr */ 499 vt8231_superio_cfg_write(s, 0, 0xf7, 1); 500 vt8231_superio_cfg_write(s, 1, 0xfc, 1); 501 502 vt8231_superio_cfg_write(s, 0, 0, 1); 503 } 504 505 static void vt8231_superio_init(Object *obj) 506 { 507 VIA_SUPERIO(obj)->io_ops = &vt8231_superio_cfg_ops; 508 } 509 510 static uint16_t vt8231_superio_serial_iobase(ISASuperIODevice *sio, 511 uint8_t index) 512 { 513 return 0x2f8; /* FIXME: This should be settable via registers f2-f4 */ 514 } 515 516 static void vt8231_superio_class_init(ObjectClass *klass, void *data) 517 { 518 DeviceClass *dc = DEVICE_CLASS(klass); 519 ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); 520 521 dc->reset = vt8231_superio_reset; 522 sc->serial.count = 1; 523 sc->serial.get_iobase = vt8231_superio_serial_iobase; 524 sc->parallel.count = 1; 525 sc->ide.count = 0; /* emulated by via-ide */ 526 sc->floppy.count = 1; 527 } 528 529 static const TypeInfo vt8231_superio_info = { 530 .name = TYPE_VT8231_SUPERIO, 531 .parent = TYPE_VIA_SUPERIO, 532 .instance_size = sizeof(ViaSuperIOState), 533 .instance_init = vt8231_superio_init, 534 .class_size = sizeof(ISASuperIOClass), 535 .class_init = vt8231_superio_class_init, 536 }; 537 538 539 #define TYPE_VIA_ISA "via-isa" 540 OBJECT_DECLARE_SIMPLE_TYPE(ViaISAState, VIA_ISA) 541 542 struct ViaISAState { 543 PCIDevice dev; 544 qemu_irq cpu_intr; 545 qemu_irq *isa_irqs; 546 ISABus *isa_bus; 547 ViaSuperIOState *via_sio; 548 }; 549 550 static const VMStateDescription vmstate_via = { 551 .name = "via-isa", 552 .version_id = 1, 553 .minimum_version_id = 1, 554 .fields = (VMStateField[]) { 555 VMSTATE_PCI_DEVICE(dev, ViaISAState), 556 VMSTATE_END_OF_LIST() 557 } 558 }; 559 560 static const TypeInfo via_isa_info = { 561 .name = TYPE_VIA_ISA, 562 .parent = TYPE_PCI_DEVICE, 563 .instance_size = sizeof(ViaISAState), 564 .abstract = true, 565 .interfaces = (InterfaceInfo[]) { 566 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 567 { }, 568 }, 569 }; 570 571 void via_isa_set_irq(PCIDevice *d, int n, int level) 572 { 573 ViaISAState *s = VIA_ISA(d); 574 qemu_set_irq(s->isa_irqs[n], level); 575 } 576 577 static void via_isa_request_i8259_irq(void *opaque, int irq, int level) 578 { 579 ViaISAState *s = opaque; 580 qemu_set_irq(s->cpu_intr, level); 581 } 582 583 static void via_isa_realize(PCIDevice *d, Error **errp) 584 { 585 ViaISAState *s = VIA_ISA(d); 586 DeviceState *dev = DEVICE(d); 587 qemu_irq *isa_irq; 588 int i; 589 590 qdev_init_gpio_out(dev, &s->cpu_intr, 1); 591 isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1); 592 s->isa_bus = isa_bus_new(dev, get_system_memory(), pci_address_space_io(d), 593 &error_fatal); 594 s->isa_irqs = i8259_init(s->isa_bus, *isa_irq); 595 isa_bus_irqs(s->isa_bus, s->isa_irqs); 596 i8254_pit_init(s->isa_bus, 0x40, 0, NULL); 597 i8257_dma_init(s->isa_bus, 0); 598 mc146818_rtc_init(s->isa_bus, 2000, NULL); 599 600 for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) { 601 if (i < PCI_COMMAND || i >= PCI_REVISION_ID) { 602 d->wmask[i] = 0; 603 } 604 } 605 } 606 607 /* TYPE_VT82C686B_ISA */ 608 609 static void vt82c686b_write_config(PCIDevice *d, uint32_t addr, 610 uint32_t val, int len) 611 { 612 ViaISAState *s = VIA_ISA(d); 613 614 trace_via_isa_write(addr, val, len); 615 pci_default_write_config(d, addr, val, len); 616 if (addr == 0x85) { 617 /* BIT(1): enable or disable superio config io ports */ 618 via_superio_io_enable(s->via_sio, val & BIT(1)); 619 } 620 } 621 622 static void vt82c686b_isa_reset(DeviceState *dev) 623 { 624 ViaISAState *s = VIA_ISA(dev); 625 uint8_t *pci_conf = s->dev.config; 626 627 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); 628 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 629 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); 630 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); 631 632 pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ 633 pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ 634 pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ 635 pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ 636 pci_conf[0x59] = 0x04; 637 pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ 638 pci_conf[0x5f] = 0x04; 639 pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ 640 } 641 642 static void vt82c686b_realize(PCIDevice *d, Error **errp) 643 { 644 ViaISAState *s = VIA_ISA(d); 645 646 via_isa_realize(d, errp); 647 s->via_sio = VIA_SUPERIO(isa_create_simple(s->isa_bus, 648 TYPE_VT82C686B_SUPERIO)); 649 } 650 651 static void vt82c686b_class_init(ObjectClass *klass, void *data) 652 { 653 DeviceClass *dc = DEVICE_CLASS(klass); 654 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 655 656 k->realize = vt82c686b_realize; 657 k->config_write = vt82c686b_write_config; 658 k->vendor_id = PCI_VENDOR_ID_VIA; 659 k->device_id = PCI_DEVICE_ID_VIA_82C686B_ISA; 660 k->class_id = PCI_CLASS_BRIDGE_ISA; 661 k->revision = 0x40; 662 dc->reset = vt82c686b_isa_reset; 663 dc->desc = "ISA bridge"; 664 dc->vmsd = &vmstate_via; 665 /* Reason: part of VIA VT82C686 southbridge, needs to be wired up */ 666 dc->user_creatable = false; 667 } 668 669 static const TypeInfo vt82c686b_isa_info = { 670 .name = TYPE_VT82C686B_ISA, 671 .parent = TYPE_VIA_ISA, 672 .instance_size = sizeof(ViaISAState), 673 .class_init = vt82c686b_class_init, 674 }; 675 676 /* TYPE_VT8231_ISA */ 677 678 static void vt8231_write_config(PCIDevice *d, uint32_t addr, 679 uint32_t val, int len) 680 { 681 ViaISAState *s = VIA_ISA(d); 682 683 trace_via_isa_write(addr, val, len); 684 pci_default_write_config(d, addr, val, len); 685 if (addr == 0x50) { 686 /* BIT(2): enable or disable superio config io ports */ 687 via_superio_io_enable(s->via_sio, val & BIT(2)); 688 } 689 } 690 691 static void vt8231_isa_reset(DeviceState *dev) 692 { 693 ViaISAState *s = VIA_ISA(dev); 694 uint8_t *pci_conf = s->dev.config; 695 696 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); 697 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 698 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); 699 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); 700 701 pci_conf[0x58] = 0x40; /* Miscellaneous Control 0 */ 702 pci_conf[0x67] = 0x08; /* Fast IR Config */ 703 pci_conf[0x6b] = 0x01; /* Fast IR I/O Base */ 704 } 705 706 static void vt8231_realize(PCIDevice *d, Error **errp) 707 { 708 ViaISAState *s = VIA_ISA(d); 709 710 via_isa_realize(d, errp); 711 s->via_sio = VIA_SUPERIO(isa_create_simple(s->isa_bus, 712 TYPE_VT8231_SUPERIO)); 713 } 714 715 static void vt8231_class_init(ObjectClass *klass, void *data) 716 { 717 DeviceClass *dc = DEVICE_CLASS(klass); 718 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 719 720 k->realize = vt8231_realize; 721 k->config_write = vt8231_write_config; 722 k->vendor_id = PCI_VENDOR_ID_VIA; 723 k->device_id = PCI_DEVICE_ID_VIA_8231_ISA; 724 k->class_id = PCI_CLASS_BRIDGE_ISA; 725 k->revision = 0x10; 726 dc->reset = vt8231_isa_reset; 727 dc->desc = "ISA bridge"; 728 dc->vmsd = &vmstate_via; 729 /* Reason: part of VIA VT8231 southbridge, needs to be wired up */ 730 dc->user_creatable = false; 731 } 732 733 static const TypeInfo vt8231_isa_info = { 734 .name = TYPE_VT8231_ISA, 735 .parent = TYPE_VIA_ISA, 736 .instance_size = sizeof(ViaISAState), 737 .class_init = vt8231_class_init, 738 }; 739 740 741 static void vt82c686b_register_types(void) 742 { 743 type_register_static(&via_pm_info); 744 type_register_static(&vt82c686b_pm_info); 745 type_register_static(&vt8231_pm_info); 746 type_register_static(&via_superio_info); 747 type_register_static(&vt82c686b_superio_info); 748 type_register_static(&vt8231_superio_info); 749 type_register_static(&via_isa_info); 750 type_register_static(&vt82c686b_isa_info); 751 type_register_static(&vt8231_isa_info); 752 } 753 754 type_init(vt82c686b_register_types) 755