1 /* 2 * VT82C686B south bridge support 3 * 4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org) 5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) 6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) 7 * This code is licensed under the GNU GPL v2. 8 * 9 * Contributions after 2012-01-13 are licensed under the terms of the 10 * GNU GPL, version 2 or (at your option) any later version. 11 */ 12 13 #include "hw/hw.h" 14 #include "hw/i386/pc.h" 15 #include "hw/isa/vt82c686.h" 16 #include "hw/i2c/i2c.h" 17 #include "hw/i2c/smbus.h" 18 #include "hw/pci/pci.h" 19 #include "hw/isa/isa.h" 20 #include "hw/sysbus.h" 21 #include "hw/mips/mips.h" 22 #include "hw/isa/apm.h" 23 #include "hw/acpi/acpi.h" 24 #include "hw/i2c/pm_smbus.h" 25 #include "sysemu/sysemu.h" 26 #include "qemu/timer.h" 27 #include "exec/address-spaces.h" 28 29 //#define DEBUG_VT82C686B 30 31 #ifdef DEBUG_VT82C686B 32 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) 33 #else 34 #define DPRINTF(fmt, ...) 35 #endif 36 37 typedef struct SuperIOConfig 38 { 39 uint8_t config[0xff]; 40 uint8_t index; 41 uint8_t data; 42 } SuperIOConfig; 43 44 typedef struct VT82C686BState { 45 PCIDevice dev; 46 SuperIOConfig superio_conf; 47 } VT82C686BState; 48 49 static void superio_ioport_writeb(void *opaque, uint32_t addr, uint32_t data) 50 { 51 int can_write; 52 SuperIOConfig *superio_conf = opaque; 53 54 DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data); 55 if (addr == 0x3f0) { 56 superio_conf->index = data & 0xff; 57 } else { 58 /* 0x3f1 */ 59 switch (superio_conf->index) { 60 case 0x00 ... 0xdf: 61 case 0xe4: 62 case 0xe5: 63 case 0xe9 ... 0xed: 64 case 0xf3: 65 case 0xf5: 66 case 0xf7: 67 case 0xf9 ... 0xfb: 68 case 0xfd ... 0xff: 69 can_write = 0; 70 break; 71 default: 72 can_write = 1; 73 74 if (can_write) { 75 switch (superio_conf->index) { 76 case 0xe7: 77 if ((data & 0xff) != 0xfe) { 78 DPRINTF("chage uart 1 base. unsupported yet\n"); 79 } 80 break; 81 case 0xe8: 82 if ((data & 0xff) != 0xbe) { 83 DPRINTF("chage uart 2 base. unsupported yet\n"); 84 } 85 break; 86 87 default: 88 superio_conf->config[superio_conf->index] = data & 0xff; 89 } 90 } 91 } 92 superio_conf->config[superio_conf->index] = data & 0xff; 93 } 94 } 95 96 static uint32_t superio_ioport_readb(void *opaque, uint32_t addr) 97 { 98 SuperIOConfig *superio_conf = opaque; 99 100 DPRINTF("superio_ioport_readb address 0x%x\n", addr); 101 return (superio_conf->config[superio_conf->index]); 102 } 103 104 static void vt82c686b_reset(void * opaque) 105 { 106 PCIDevice *d = opaque; 107 uint8_t *pci_conf = d->config; 108 VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d); 109 110 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); 111 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 112 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); 113 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); 114 115 pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ 116 pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ 117 pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ 118 pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ 119 pci_conf[0x59] = 0x04; 120 pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ 121 pci_conf[0x5f] = 0x04; 122 pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ 123 124 vt82c->superio_conf.config[0xe0] = 0x3c; 125 vt82c->superio_conf.config[0xe2] = 0x03; 126 vt82c->superio_conf.config[0xe3] = 0xfc; 127 vt82c->superio_conf.config[0xe6] = 0xde; 128 vt82c->superio_conf.config[0xe7] = 0xfe; 129 vt82c->superio_conf.config[0xe8] = 0xbe; 130 } 131 132 /* write config pci function0 registers. PCI-ISA bridge */ 133 static void vt82c686b_write_config(PCIDevice * d, uint32_t address, 134 uint32_t val, int len) 135 { 136 VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d); 137 138 DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n", 139 address, val, len); 140 141 pci_default_write_config(d, address, val, len); 142 if (address == 0x85) { /* enable or disable super IO configure */ 143 if (val & 0x2) { 144 /* floppy also uses 0x3f0 and 0x3f1. 145 * But we do not emulate flopy,so just set it here. */ 146 isa_unassign_ioport(0x3f0, 2); 147 register_ioport_read(0x3f0, 2, 1, superio_ioport_readb, 148 &vt686->superio_conf); 149 register_ioport_write(0x3f0, 2, 1, superio_ioport_writeb, 150 &vt686->superio_conf); 151 } else { 152 isa_unassign_ioport(0x3f0, 2); 153 } 154 } 155 } 156 157 #define ACPI_DBG_IO_ADDR 0xb044 158 159 typedef struct VT686PMState { 160 PCIDevice dev; 161 MemoryRegion io; 162 ACPIREGS ar; 163 APMState apm; 164 PMSMBus smb; 165 uint32_t smb_io_base; 166 } VT686PMState; 167 168 typedef struct VT686AC97State { 169 PCIDevice dev; 170 } VT686AC97State; 171 172 typedef struct VT686MC97State { 173 PCIDevice dev; 174 } VT686MC97State; 175 176 static void pm_update_sci(VT686PMState *s) 177 { 178 int sci_level, pmsts; 179 180 pmsts = acpi_pm1_evt_get_sts(&s->ar); 181 sci_level = (((pmsts & s->ar.pm1.evt.en) & 182 (ACPI_BITMASK_RT_CLOCK_ENABLE | 183 ACPI_BITMASK_POWER_BUTTON_ENABLE | 184 ACPI_BITMASK_GLOBAL_LOCK_ENABLE | 185 ACPI_BITMASK_TIMER_ENABLE)) != 0); 186 qemu_set_irq(s->dev.irq[0], sci_level); 187 /* schedule a timer interruption if needed */ 188 acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && 189 !(pmsts & ACPI_BITMASK_TIMER_STATUS)); 190 } 191 192 static void pm_tmr_timer(ACPIREGS *ar) 193 { 194 VT686PMState *s = container_of(ar, VT686PMState, ar); 195 pm_update_sci(s); 196 } 197 198 static void pm_io_space_update(VT686PMState *s) 199 { 200 uint32_t pm_io_base; 201 202 pm_io_base = pci_get_long(s->dev.config + 0x40); 203 pm_io_base &= 0xffc0; 204 205 memory_region_transaction_begin(); 206 memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); 207 memory_region_set_address(&s->io, pm_io_base); 208 memory_region_transaction_commit(); 209 } 210 211 static void pm_write_config(PCIDevice *d, 212 uint32_t address, uint32_t val, int len) 213 { 214 DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n", 215 address, val, len); 216 pci_default_write_config(d, address, val, len); 217 } 218 219 static int vmstate_acpi_post_load(void *opaque, int version_id) 220 { 221 VT686PMState *s = opaque; 222 223 pm_io_space_update(s); 224 return 0; 225 } 226 227 static const VMStateDescription vmstate_acpi = { 228 .name = "vt82c686b_pm", 229 .version_id = 1, 230 .minimum_version_id = 1, 231 .minimum_version_id_old = 1, 232 .post_load = vmstate_acpi_post_load, 233 .fields = (VMStateField []) { 234 VMSTATE_PCI_DEVICE(dev, VT686PMState), 235 VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState), 236 VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState), 237 VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState), 238 VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState), 239 VMSTATE_TIMER(ar.tmr.timer, VT686PMState), 240 VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState), 241 VMSTATE_END_OF_LIST() 242 } 243 }; 244 245 /* 246 * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init() 247 * just register a PCI device now, functionalities will be implemented later. 248 */ 249 250 static int vt82c686b_ac97_initfn(PCIDevice *dev) 251 { 252 VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev); 253 uint8_t *pci_conf = s->dev.config; 254 255 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | 256 PCI_COMMAND_PARITY); 257 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST | 258 PCI_STATUS_DEVSEL_MEDIUM); 259 pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); 260 261 return 0; 262 } 263 264 void vt82c686b_ac97_init(PCIBus *bus, int devfn) 265 { 266 PCIDevice *dev; 267 268 dev = pci_create(bus, devfn, "VT82C686B_AC97"); 269 qdev_init_nofail(&dev->qdev); 270 } 271 272 static void via_ac97_class_init(ObjectClass *klass, void *data) 273 { 274 DeviceClass *dc = DEVICE_CLASS(klass); 275 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 276 277 k->init = vt82c686b_ac97_initfn; 278 k->vendor_id = PCI_VENDOR_ID_VIA; 279 k->device_id = PCI_DEVICE_ID_VIA_AC97; 280 k->revision = 0x50; 281 k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; 282 dc->desc = "AC97"; 283 } 284 285 static const TypeInfo via_ac97_info = { 286 .name = "VT82C686B_AC97", 287 .parent = TYPE_PCI_DEVICE, 288 .instance_size = sizeof(VT686AC97State), 289 .class_init = via_ac97_class_init, 290 }; 291 292 static int vt82c686b_mc97_initfn(PCIDevice *dev) 293 { 294 VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev); 295 uint8_t *pci_conf = s->dev.config; 296 297 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | 298 PCI_COMMAND_VGA_PALETTE); 299 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); 300 pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); 301 302 return 0; 303 } 304 305 void vt82c686b_mc97_init(PCIBus *bus, int devfn) 306 { 307 PCIDevice *dev; 308 309 dev = pci_create(bus, devfn, "VT82C686B_MC97"); 310 qdev_init_nofail(&dev->qdev); 311 } 312 313 static void via_mc97_class_init(ObjectClass *klass, void *data) 314 { 315 DeviceClass *dc = DEVICE_CLASS(klass); 316 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 317 318 k->init = vt82c686b_mc97_initfn; 319 k->vendor_id = PCI_VENDOR_ID_VIA; 320 k->device_id = PCI_DEVICE_ID_VIA_MC97; 321 k->class_id = PCI_CLASS_COMMUNICATION_OTHER; 322 k->revision = 0x30; 323 dc->desc = "MC97"; 324 } 325 326 static const TypeInfo via_mc97_info = { 327 .name = "VT82C686B_MC97", 328 .parent = TYPE_PCI_DEVICE, 329 .instance_size = sizeof(VT686MC97State), 330 .class_init = via_mc97_class_init, 331 }; 332 333 /* vt82c686 pm init */ 334 static int vt82c686b_pm_initfn(PCIDevice *dev) 335 { 336 VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev); 337 uint8_t *pci_conf; 338 339 pci_conf = s->dev.config; 340 pci_set_word(pci_conf + PCI_COMMAND, 0); 341 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | 342 PCI_STATUS_DEVSEL_MEDIUM); 343 344 /* 0x48-0x4B is Power Management I/O Base */ 345 pci_set_long(pci_conf + 0x48, 0x00000001); 346 347 /* SMB ports:0xeee0~0xeeef */ 348 s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0); 349 pci_conf[0x90] = s->smb_io_base | 1; 350 pci_conf[0x91] = s->smb_io_base >> 8; 351 pci_conf[0xd2] = 0x90; 352 pm_smbus_init(&s->dev.qdev, &s->smb); 353 memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); 354 355 apm_init(dev, &s->apm, NULL, s); 356 357 memory_region_init(&s->io, "vt82c686-pm", 64); 358 memory_region_set_enabled(&s->io, false); 359 memory_region_add_subregion(get_system_io(), 0, &s->io); 360 361 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 362 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 363 acpi_pm1_cnt_init(&s->ar, &s->io, 2); 364 365 return 0; 366 } 367 368 i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 369 qemu_irq sci_irq) 370 { 371 PCIDevice *dev; 372 VT686PMState *s; 373 374 dev = pci_create(bus, devfn, "VT82C686B_PM"); 375 qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); 376 377 s = DO_UPCAST(VT686PMState, dev, dev); 378 379 qdev_init_nofail(&dev->qdev); 380 381 return s->smb.smbus; 382 } 383 384 static Property via_pm_properties[] = { 385 DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0), 386 DEFINE_PROP_END_OF_LIST(), 387 }; 388 389 static void via_pm_class_init(ObjectClass *klass, void *data) 390 { 391 DeviceClass *dc = DEVICE_CLASS(klass); 392 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 393 394 k->init = vt82c686b_pm_initfn; 395 k->config_write = pm_write_config; 396 k->vendor_id = PCI_VENDOR_ID_VIA; 397 k->device_id = PCI_DEVICE_ID_VIA_ACPI; 398 k->class_id = PCI_CLASS_BRIDGE_OTHER; 399 k->revision = 0x40; 400 dc->desc = "PM"; 401 dc->vmsd = &vmstate_acpi; 402 dc->props = via_pm_properties; 403 } 404 405 static const TypeInfo via_pm_info = { 406 .name = "VT82C686B_PM", 407 .parent = TYPE_PCI_DEVICE, 408 .instance_size = sizeof(VT686PMState), 409 .class_init = via_pm_class_init, 410 }; 411 412 static const VMStateDescription vmstate_via = { 413 .name = "vt82c686b", 414 .version_id = 1, 415 .minimum_version_id = 1, 416 .minimum_version_id_old = 1, 417 .fields = (VMStateField []) { 418 VMSTATE_PCI_DEVICE(dev, VT82C686BState), 419 VMSTATE_END_OF_LIST() 420 } 421 }; 422 423 /* init the PCI-to-ISA bridge */ 424 static int vt82c686b_initfn(PCIDevice *d) 425 { 426 uint8_t *pci_conf; 427 uint8_t *wmask; 428 int i; 429 430 isa_bus_new(&d->qdev, pci_address_space_io(d)); 431 432 pci_conf = d->config; 433 pci_config_set_prog_interface(pci_conf, 0x0); 434 435 wmask = d->wmask; 436 for (i = 0x00; i < 0xff; i++) { 437 if (i<=0x03 || (i>=0x08 && i<=0x3f)) { 438 wmask[i] = 0x00; 439 } 440 } 441 442 qemu_register_reset(vt82c686b_reset, d); 443 444 return 0; 445 } 446 447 ISABus *vt82c686b_init(PCIBus *bus, int devfn) 448 { 449 PCIDevice *d; 450 451 d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B"); 452 453 return ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0")); 454 } 455 456 static void via_class_init(ObjectClass *klass, void *data) 457 { 458 DeviceClass *dc = DEVICE_CLASS(klass); 459 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 460 461 k->init = vt82c686b_initfn; 462 k->config_write = vt82c686b_write_config; 463 k->vendor_id = PCI_VENDOR_ID_VIA; 464 k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; 465 k->class_id = PCI_CLASS_BRIDGE_ISA; 466 k->revision = 0x40; 467 dc->desc = "ISA bridge"; 468 dc->no_user = 1; 469 dc->vmsd = &vmstate_via; 470 } 471 472 static const TypeInfo via_info = { 473 .name = "VT82C686B", 474 .parent = TYPE_PCI_DEVICE, 475 .instance_size = sizeof(VT82C686BState), 476 .class_init = via_class_init, 477 }; 478 479 static void vt82c686b_register_types(void) 480 { 481 type_register_static(&via_ac97_info); 482 type_register_static(&via_mc97_info); 483 type_register_static(&via_pm_info); 484 type_register_static(&via_info); 485 } 486 487 type_init(vt82c686b_register_types) 488