1 /* 2 * VT82C686B south bridge support 3 * 4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org) 5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) 6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) 7 * This code is licensed under the GNU GPL v2. 8 * 9 * Contributions after 2012-01-13 are licensed under the terms of the 10 * GNU GPL, version 2 or (at your option) any later version. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "hw/isa/vt82c686.h" 15 #include "hw/pci/pci.h" 16 #include "hw/qdev-properties.h" 17 #include "hw/isa/isa.h" 18 #include "hw/isa/superio.h" 19 #include "hw/intc/i8259.h" 20 #include "hw/irq.h" 21 #include "hw/dma/i8257.h" 22 #include "hw/timer/i8254.h" 23 #include "hw/rtc/mc146818rtc.h" 24 #include "migration/vmstate.h" 25 #include "hw/isa/apm.h" 26 #include "hw/acpi/acpi.h" 27 #include "hw/i2c/pm_smbus.h" 28 #include "qapi/error.h" 29 #include "qemu/log.h" 30 #include "qemu/module.h" 31 #include "qemu/range.h" 32 #include "qemu/timer.h" 33 #include "exec/address-spaces.h" 34 #include "trace.h" 35 36 #define TYPE_VIA_PM "via-pm" 37 OBJECT_DECLARE_SIMPLE_TYPE(ViaPMState, VIA_PM) 38 39 struct ViaPMState { 40 PCIDevice dev; 41 MemoryRegion io; 42 ACPIREGS ar; 43 APMState apm; 44 PMSMBus smb; 45 }; 46 47 static void pm_io_space_update(ViaPMState *s) 48 { 49 uint32_t pmbase = pci_get_long(s->dev.config + 0x48) & 0xff80UL; 50 51 memory_region_transaction_begin(); 52 memory_region_set_address(&s->io, pmbase); 53 memory_region_set_enabled(&s->io, s->dev.config[0x41] & BIT(7)); 54 memory_region_transaction_commit(); 55 } 56 57 static void smb_io_space_update(ViaPMState *s) 58 { 59 uint32_t smbase = pci_get_long(s->dev.config + 0x90) & 0xfff0UL; 60 61 memory_region_transaction_begin(); 62 memory_region_set_address(&s->smb.io, smbase); 63 memory_region_set_enabled(&s->smb.io, s->dev.config[0xd2] & BIT(0)); 64 memory_region_transaction_commit(); 65 } 66 67 static int vmstate_acpi_post_load(void *opaque, int version_id) 68 { 69 ViaPMState *s = opaque; 70 71 pm_io_space_update(s); 72 smb_io_space_update(s); 73 return 0; 74 } 75 76 static const VMStateDescription vmstate_acpi = { 77 .name = "vt82c686b_pm", 78 .version_id = 1, 79 .minimum_version_id = 1, 80 .post_load = vmstate_acpi_post_load, 81 .fields = (VMStateField[]) { 82 VMSTATE_PCI_DEVICE(dev, ViaPMState), 83 VMSTATE_UINT16(ar.pm1.evt.sts, ViaPMState), 84 VMSTATE_UINT16(ar.pm1.evt.en, ViaPMState), 85 VMSTATE_UINT16(ar.pm1.cnt.cnt, ViaPMState), 86 VMSTATE_STRUCT(apm, ViaPMState, 0, vmstate_apm, APMState), 87 VMSTATE_TIMER_PTR(ar.tmr.timer, ViaPMState), 88 VMSTATE_INT64(ar.tmr.overflow_time, ViaPMState), 89 VMSTATE_END_OF_LIST() 90 } 91 }; 92 93 static void pm_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int len) 94 { 95 ViaPMState *s = VIA_PM(d); 96 97 trace_via_pm_write(addr, val, len); 98 pci_default_write_config(d, addr, val, len); 99 if (ranges_overlap(addr, len, 0x48, 4)) { 100 uint32_t v = pci_get_long(s->dev.config + 0x48); 101 pci_set_long(s->dev.config + 0x48, (v & 0xff80UL) | 1); 102 } 103 if (range_covers_byte(addr, len, 0x41)) { 104 pm_io_space_update(s); 105 } 106 if (ranges_overlap(addr, len, 0x90, 4)) { 107 uint32_t v = pci_get_long(s->dev.config + 0x90); 108 pci_set_long(s->dev.config + 0x90, (v & 0xfff0UL) | 1); 109 } 110 if (range_covers_byte(addr, len, 0xd2)) { 111 s->dev.config[0xd2] &= 0xf; 112 smb_io_space_update(s); 113 } 114 } 115 116 static void pm_io_write(void *op, hwaddr addr, uint64_t data, unsigned size) 117 { 118 trace_via_pm_io_write(addr, data, size); 119 } 120 121 static uint64_t pm_io_read(void *op, hwaddr addr, unsigned size) 122 { 123 trace_via_pm_io_read(addr, 0, size); 124 return 0; 125 } 126 127 static const MemoryRegionOps pm_io_ops = { 128 .read = pm_io_read, 129 .write = pm_io_write, 130 .endianness = DEVICE_NATIVE_ENDIAN, 131 .impl = { 132 .min_access_size = 1, 133 .max_access_size = 1, 134 }, 135 }; 136 137 static void pm_update_sci(ViaPMState *s) 138 { 139 int sci_level, pmsts; 140 141 pmsts = acpi_pm1_evt_get_sts(&s->ar); 142 sci_level = (((pmsts & s->ar.pm1.evt.en) & 143 (ACPI_BITMASK_RT_CLOCK_ENABLE | 144 ACPI_BITMASK_POWER_BUTTON_ENABLE | 145 ACPI_BITMASK_GLOBAL_LOCK_ENABLE | 146 ACPI_BITMASK_TIMER_ENABLE)) != 0); 147 pci_set_irq(&s->dev, sci_level); 148 /* schedule a timer interruption if needed */ 149 acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && 150 !(pmsts & ACPI_BITMASK_TIMER_STATUS)); 151 } 152 153 static void pm_tmr_timer(ACPIREGS *ar) 154 { 155 ViaPMState *s = container_of(ar, ViaPMState, ar); 156 pm_update_sci(s); 157 } 158 159 static void via_pm_reset(DeviceState *d) 160 { 161 ViaPMState *s = VIA_PM(d); 162 163 memset(s->dev.config + PCI_CONFIG_HEADER_SIZE, 0, 164 PCI_CONFIG_SPACE_SIZE - PCI_CONFIG_HEADER_SIZE); 165 /* Power Management IO base */ 166 pci_set_long(s->dev.config + 0x48, 1); 167 /* SMBus IO base */ 168 pci_set_long(s->dev.config + 0x90, 1); 169 170 pm_io_space_update(s); 171 smb_io_space_update(s); 172 } 173 174 static void via_pm_realize(PCIDevice *dev, Error **errp) 175 { 176 ViaPMState *s = VIA_PM(dev); 177 178 pci_set_word(dev->config + PCI_STATUS, PCI_STATUS_FAST_BACK | 179 PCI_STATUS_DEVSEL_MEDIUM); 180 181 pm_smbus_init(DEVICE(s), &s->smb, false); 182 memory_region_add_subregion(pci_address_space_io(dev), 0, &s->smb.io); 183 memory_region_set_enabled(&s->smb.io, false); 184 185 apm_init(dev, &s->apm, NULL, s); 186 187 memory_region_init_io(&s->io, OBJECT(dev), &pm_io_ops, s, "via-pm", 128); 188 memory_region_add_subregion(pci_address_space_io(dev), 0, &s->io); 189 memory_region_set_enabled(&s->io, false); 190 191 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 192 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 193 acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2, false); 194 } 195 196 typedef struct via_pm_init_info { 197 uint16_t device_id; 198 } ViaPMInitInfo; 199 200 static void via_pm_class_init(ObjectClass *klass, void *data) 201 { 202 DeviceClass *dc = DEVICE_CLASS(klass); 203 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 204 ViaPMInitInfo *info = data; 205 206 k->realize = via_pm_realize; 207 k->config_write = pm_write_config; 208 k->vendor_id = PCI_VENDOR_ID_VIA; 209 k->device_id = info->device_id; 210 k->class_id = PCI_CLASS_BRIDGE_OTHER; 211 k->revision = 0x40; 212 dc->reset = via_pm_reset; 213 /* Reason: part of VIA south bridge, does not exist stand alone */ 214 dc->user_creatable = false; 215 dc->vmsd = &vmstate_acpi; 216 } 217 218 static const TypeInfo via_pm_info = { 219 .name = TYPE_VIA_PM, 220 .parent = TYPE_PCI_DEVICE, 221 .instance_size = sizeof(ViaPMState), 222 .abstract = true, 223 .interfaces = (InterfaceInfo[]) { 224 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 225 { }, 226 }, 227 }; 228 229 static const ViaPMInitInfo vt82c686b_pm_init_info = { 230 .device_id = PCI_DEVICE_ID_VIA_82C686B_PM, 231 }; 232 233 static const TypeInfo vt82c686b_pm_info = { 234 .name = TYPE_VT82C686B_PM, 235 .parent = TYPE_VIA_PM, 236 .class_init = via_pm_class_init, 237 .class_data = (void *)&vt82c686b_pm_init_info, 238 }; 239 240 static const ViaPMInitInfo vt8231_pm_init_info = { 241 .device_id = PCI_DEVICE_ID_VIA_8231_PM, 242 }; 243 244 static const TypeInfo vt8231_pm_info = { 245 .name = TYPE_VT8231_PM, 246 .parent = TYPE_VIA_PM, 247 .class_init = via_pm_class_init, 248 .class_data = (void *)&vt8231_pm_init_info, 249 }; 250 251 252 typedef struct SuperIOConfig { 253 uint8_t regs[0x100]; 254 MemoryRegion io; 255 } SuperIOConfig; 256 257 static void superio_cfg_write(void *opaque, hwaddr addr, uint64_t data, 258 unsigned size) 259 { 260 SuperIOConfig *sc = opaque; 261 uint8_t idx = sc->regs[0]; 262 263 if (addr == 0) { /* config index register */ 264 sc->regs[0] = data; 265 return; 266 } 267 268 /* config data register */ 269 trace_via_superio_write(idx, data); 270 switch (idx) { 271 case 0x00 ... 0xdf: 272 case 0xe4: 273 case 0xe5: 274 case 0xe9 ... 0xed: 275 case 0xf3: 276 case 0xf5: 277 case 0xf7: 278 case 0xf9 ... 0xfb: 279 case 0xfd ... 0xff: 280 /* ignore write to read only registers */ 281 return; 282 /* case 0xe6 ... 0xe8: Should set base port of parallel and serial */ 283 default: 284 qemu_log_mask(LOG_UNIMP, 285 "via_superio_cfg: unimplemented register 0x%x\n", idx); 286 break; 287 } 288 sc->regs[idx] = data; 289 } 290 291 static uint64_t superio_cfg_read(void *opaque, hwaddr addr, unsigned size) 292 { 293 SuperIOConfig *sc = opaque; 294 uint8_t idx = sc->regs[0]; 295 uint8_t val = sc->regs[idx]; 296 297 if (addr == 0) { 298 return idx; 299 } 300 if (addr == 1 && idx == 0) { 301 val = 0; /* reading reg 0 where we store index value */ 302 } 303 trace_via_superio_read(idx, val); 304 return val; 305 } 306 307 static const MemoryRegionOps superio_cfg_ops = { 308 .read = superio_cfg_read, 309 .write = superio_cfg_write, 310 .endianness = DEVICE_NATIVE_ENDIAN, 311 .impl = { 312 .min_access_size = 1, 313 .max_access_size = 1, 314 }, 315 }; 316 317 318 OBJECT_DECLARE_SIMPLE_TYPE(VT82C686BISAState, VT82C686B_ISA) 319 320 struct VT82C686BISAState { 321 PCIDevice dev; 322 qemu_irq cpu_intr; 323 SuperIOConfig superio_cfg; 324 }; 325 326 static void via_isa_request_i8259_irq(void *opaque, int irq, int level) 327 { 328 VT82C686BISAState *s = opaque; 329 qemu_set_irq(s->cpu_intr, level); 330 } 331 332 static void vt82c686b_write_config(PCIDevice *d, uint32_t addr, 333 uint32_t val, int len) 334 { 335 VT82C686BISAState *s = VT82C686B_ISA(d); 336 337 trace_via_isa_write(addr, val, len); 338 pci_default_write_config(d, addr, val, len); 339 if (addr == 0x85) { 340 /* BIT(1): enable or disable superio config io ports */ 341 memory_region_set_enabled(&s->superio_cfg.io, val & BIT(1)); 342 } 343 } 344 345 static const VMStateDescription vmstate_via = { 346 .name = "vt82c686b", 347 .version_id = 1, 348 .minimum_version_id = 1, 349 .fields = (VMStateField[]) { 350 VMSTATE_PCI_DEVICE(dev, VT82C686BISAState), 351 VMSTATE_END_OF_LIST() 352 } 353 }; 354 355 static void vt82c686b_isa_reset(DeviceState *dev) 356 { 357 VT82C686BISAState *s = VT82C686B_ISA(dev); 358 uint8_t *pci_conf = s->dev.config; 359 360 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); 361 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 362 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); 363 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); 364 365 pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ 366 pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ 367 pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ 368 pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ 369 pci_conf[0x59] = 0x04; 370 pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ 371 pci_conf[0x5f] = 0x04; 372 pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ 373 374 s->superio_cfg.regs[0xe0] = 0x3c; /* Device ID */ 375 s->superio_cfg.regs[0xe2] = 0x03; /* Function select */ 376 s->superio_cfg.regs[0xe3] = 0xfc; /* Floppy ctrl base addr */ 377 s->superio_cfg.regs[0xe6] = 0xde; /* Parallel port base addr */ 378 s->superio_cfg.regs[0xe7] = 0xfe; /* Serial port 1 base addr */ 379 s->superio_cfg.regs[0xe8] = 0xbe; /* Serial port 2 base addr */ 380 } 381 382 static void vt82c686b_realize(PCIDevice *d, Error **errp) 383 { 384 VT82C686BISAState *s = VT82C686B_ISA(d); 385 DeviceState *dev = DEVICE(d); 386 ISABus *isa_bus; 387 qemu_irq *isa_irq; 388 int i; 389 390 qdev_init_gpio_out(dev, &s->cpu_intr, 1); 391 isa_irq = qemu_allocate_irqs(via_isa_request_i8259_irq, s, 1); 392 isa_bus = isa_bus_new(dev, get_system_memory(), pci_address_space_io(d), 393 &error_fatal); 394 isa_bus_irqs(isa_bus, i8259_init(isa_bus, *isa_irq)); 395 i8254_pit_init(isa_bus, 0x40, 0, NULL); 396 i8257_dma_init(isa_bus, 0); 397 isa_create_simple(isa_bus, TYPE_VT82C686B_SUPERIO); 398 mc146818_rtc_init(isa_bus, 2000, NULL); 399 400 for (i = 0; i < PCI_CONFIG_HEADER_SIZE; i++) { 401 if (i < PCI_COMMAND || i >= PCI_REVISION_ID) { 402 d->wmask[i] = 0; 403 } 404 } 405 406 memory_region_init_io(&s->superio_cfg.io, OBJECT(d), &superio_cfg_ops, 407 &s->superio_cfg, "superio_cfg", 2); 408 memory_region_set_enabled(&s->superio_cfg.io, false); 409 /* 410 * The floppy also uses 0x3f0 and 0x3f1. 411 * But we do not emulate a floppy, so just set it here. 412 */ 413 memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, 414 &s->superio_cfg.io); 415 } 416 417 static void via_class_init(ObjectClass *klass, void *data) 418 { 419 DeviceClass *dc = DEVICE_CLASS(klass); 420 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 421 422 k->realize = vt82c686b_realize; 423 k->config_write = vt82c686b_write_config; 424 k->vendor_id = PCI_VENDOR_ID_VIA; 425 k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; 426 k->class_id = PCI_CLASS_BRIDGE_ISA; 427 k->revision = 0x40; 428 dc->reset = vt82c686b_isa_reset; 429 dc->desc = "ISA bridge"; 430 dc->vmsd = &vmstate_via; 431 /* 432 * Reason: part of VIA VT82C686 southbridge, needs to be wired up, 433 * e.g. by mips_fuloong2e_init() 434 */ 435 dc->user_creatable = false; 436 } 437 438 static const TypeInfo via_info = { 439 .name = TYPE_VT82C686B_ISA, 440 .parent = TYPE_PCI_DEVICE, 441 .instance_size = sizeof(VT82C686BISAState), 442 .class_init = via_class_init, 443 .interfaces = (InterfaceInfo[]) { 444 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 445 { }, 446 }, 447 }; 448 449 450 static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) 451 { 452 ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); 453 454 sc->serial.count = 2; 455 sc->parallel.count = 1; 456 sc->ide.count = 0; 457 sc->floppy.count = 1; 458 } 459 460 static const TypeInfo via_superio_info = { 461 .name = TYPE_VT82C686B_SUPERIO, 462 .parent = TYPE_ISA_SUPERIO, 463 .instance_size = sizeof(ISASuperIODevice), 464 .class_size = sizeof(ISASuperIOClass), 465 .class_init = vt82c686b_superio_class_init, 466 }; 467 468 469 static void vt82c686b_register_types(void) 470 { 471 type_register_static(&via_pm_info); 472 type_register_static(&vt82c686b_pm_info); 473 type_register_static(&vt8231_pm_info); 474 type_register_static(&via_info); 475 type_register_static(&via_superio_info); 476 } 477 478 type_init(vt82c686b_register_types) 479