1 /* 2 * VT82C686B south bridge support 3 * 4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org) 5 * Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn) 6 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) 7 * This code is licensed under the GNU GPL v2. 8 * 9 * Contributions after 2012-01-13 are licensed under the terms of the 10 * GNU GPL, version 2 or (at your option) any later version. 11 */ 12 13 #include "qemu/osdep.h" 14 #include "hw/hw.h" 15 #include "hw/isa/vt82c686.h" 16 #include "hw/i2c/i2c.h" 17 #include "hw/i2c/smbus.h" 18 #include "hw/pci/pci.h" 19 #include "hw/isa/isa.h" 20 #include "hw/isa/superio.h" 21 #include "hw/sysbus.h" 22 #include "hw/mips/mips.h" 23 #include "hw/isa/apm.h" 24 #include "hw/acpi/acpi.h" 25 #include "hw/i2c/pm_smbus.h" 26 #include "sysemu/sysemu.h" 27 #include "qemu/timer.h" 28 #include "exec/address-spaces.h" 29 30 //#define DEBUG_VT82C686B 31 32 #ifdef DEBUG_VT82C686B 33 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__) 34 #else 35 #define DPRINTF(fmt, ...) 36 #endif 37 38 typedef struct SuperIOConfig 39 { 40 uint8_t config[0x100]; 41 uint8_t index; 42 uint8_t data; 43 } SuperIOConfig; 44 45 typedef struct VT82C686BState { 46 PCIDevice dev; 47 MemoryRegion superio; 48 SuperIOConfig superio_conf; 49 } VT82C686BState; 50 51 #define TYPE_VT82C686B_DEVICE "VT82C686B" 52 #define VT82C686B_DEVICE(obj) \ 53 OBJECT_CHECK(VT82C686BState, (obj), TYPE_VT82C686B_DEVICE) 54 55 static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data, 56 unsigned size) 57 { 58 SuperIOConfig *superio_conf = opaque; 59 60 DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data); 61 if (addr == 0x3f0) { 62 superio_conf->index = data & 0xff; 63 } else { 64 bool can_write = true; 65 /* 0x3f1 */ 66 switch (superio_conf->index) { 67 case 0x00 ... 0xdf: 68 case 0xe4: 69 case 0xe5: 70 case 0xe9 ... 0xed: 71 case 0xf3: 72 case 0xf5: 73 case 0xf7: 74 case 0xf9 ... 0xfb: 75 case 0xfd ... 0xff: 76 can_write = false; 77 break; 78 case 0xe7: 79 if ((data & 0xff) != 0xfe) { 80 DPRINTF("change uart 1 base. unsupported yet\n"); 81 can_write = false; 82 } 83 break; 84 case 0xe8: 85 if ((data & 0xff) != 0xbe) { 86 DPRINTF("change uart 2 base. unsupported yet\n"); 87 can_write = false; 88 } 89 break; 90 default: 91 break; 92 93 } 94 if (can_write) { 95 superio_conf->config[superio_conf->index] = data & 0xff; 96 } 97 } 98 } 99 100 static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size) 101 { 102 SuperIOConfig *superio_conf = opaque; 103 104 DPRINTF("superio_ioport_readb address 0x%x\n", addr); 105 return (superio_conf->config[superio_conf->index]); 106 } 107 108 static const MemoryRegionOps superio_ops = { 109 .read = superio_ioport_readb, 110 .write = superio_ioport_writeb, 111 .endianness = DEVICE_NATIVE_ENDIAN, 112 .impl = { 113 .min_access_size = 1, 114 .max_access_size = 1, 115 }, 116 }; 117 118 static void vt82c686b_reset(void * opaque) 119 { 120 PCIDevice *d = opaque; 121 uint8_t *pci_conf = d->config; 122 VT82C686BState *vt82c = VT82C686B_DEVICE(d); 123 124 pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0); 125 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY | 126 PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); 127 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); 128 129 pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */ 130 pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */ 131 pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */ 132 pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */ 133 pci_conf[0x59] = 0x04; 134 pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/ 135 pci_conf[0x5f] = 0x04; 136 pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */ 137 138 vt82c->superio_conf.config[0xe0] = 0x3c; 139 vt82c->superio_conf.config[0xe2] = 0x03; 140 vt82c->superio_conf.config[0xe3] = 0xfc; 141 vt82c->superio_conf.config[0xe6] = 0xde; 142 vt82c->superio_conf.config[0xe7] = 0xfe; 143 vt82c->superio_conf.config[0xe8] = 0xbe; 144 } 145 146 /* write config pci function0 registers. PCI-ISA bridge */ 147 static void vt82c686b_write_config(PCIDevice * d, uint32_t address, 148 uint32_t val, int len) 149 { 150 VT82C686BState *vt686 = VT82C686B_DEVICE(d); 151 152 DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n", 153 address, val, len); 154 155 pci_default_write_config(d, address, val, len); 156 if (address == 0x85) { /* enable or disable super IO configure */ 157 memory_region_set_enabled(&vt686->superio, val & 0x2); 158 } 159 } 160 161 #define ACPI_DBG_IO_ADDR 0xb044 162 163 typedef struct VT686PMState { 164 PCIDevice dev; 165 MemoryRegion io; 166 ACPIREGS ar; 167 APMState apm; 168 PMSMBus smb; 169 uint32_t smb_io_base; 170 } VT686PMState; 171 172 typedef struct VT686AC97State { 173 PCIDevice dev; 174 } VT686AC97State; 175 176 typedef struct VT686MC97State { 177 PCIDevice dev; 178 } VT686MC97State; 179 180 #define TYPE_VT82C686B_PM_DEVICE "VT82C686B_PM" 181 #define VT82C686B_PM_DEVICE(obj) \ 182 OBJECT_CHECK(VT686PMState, (obj), TYPE_VT82C686B_PM_DEVICE) 183 184 #define TYPE_VT82C686B_MC97_DEVICE "VT82C686B_MC97" 185 #define VT82C686B_MC97_DEVICE(obj) \ 186 OBJECT_CHECK(VT686MC97State, (obj), TYPE_VT82C686B_MC97_DEVICE) 187 188 #define TYPE_VT82C686B_AC97_DEVICE "VT82C686B_AC97" 189 #define VT82C686B_AC97_DEVICE(obj) \ 190 OBJECT_CHECK(VT686AC97State, (obj), TYPE_VT82C686B_AC97_DEVICE) 191 192 static void pm_update_sci(VT686PMState *s) 193 { 194 int sci_level, pmsts; 195 196 pmsts = acpi_pm1_evt_get_sts(&s->ar); 197 sci_level = (((pmsts & s->ar.pm1.evt.en) & 198 (ACPI_BITMASK_RT_CLOCK_ENABLE | 199 ACPI_BITMASK_POWER_BUTTON_ENABLE | 200 ACPI_BITMASK_GLOBAL_LOCK_ENABLE | 201 ACPI_BITMASK_TIMER_ENABLE)) != 0); 202 pci_set_irq(&s->dev, sci_level); 203 /* schedule a timer interruption if needed */ 204 acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) && 205 !(pmsts & ACPI_BITMASK_TIMER_STATUS)); 206 } 207 208 static void pm_tmr_timer(ACPIREGS *ar) 209 { 210 VT686PMState *s = container_of(ar, VT686PMState, ar); 211 pm_update_sci(s); 212 } 213 214 static void pm_io_space_update(VT686PMState *s) 215 { 216 uint32_t pm_io_base; 217 218 pm_io_base = pci_get_long(s->dev.config + 0x40); 219 pm_io_base &= 0xffc0; 220 221 memory_region_transaction_begin(); 222 memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1); 223 memory_region_set_address(&s->io, pm_io_base); 224 memory_region_transaction_commit(); 225 } 226 227 static void pm_write_config(PCIDevice *d, 228 uint32_t address, uint32_t val, int len) 229 { 230 DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n", 231 address, val, len); 232 pci_default_write_config(d, address, val, len); 233 } 234 235 static int vmstate_acpi_post_load(void *opaque, int version_id) 236 { 237 VT686PMState *s = opaque; 238 239 pm_io_space_update(s); 240 return 0; 241 } 242 243 static const VMStateDescription vmstate_acpi = { 244 .name = "vt82c686b_pm", 245 .version_id = 1, 246 .minimum_version_id = 1, 247 .post_load = vmstate_acpi_post_load, 248 .fields = (VMStateField[]) { 249 VMSTATE_PCI_DEVICE(dev, VT686PMState), 250 VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState), 251 VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState), 252 VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState), 253 VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState), 254 VMSTATE_TIMER_PTR(ar.tmr.timer, VT686PMState), 255 VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState), 256 VMSTATE_END_OF_LIST() 257 } 258 }; 259 260 /* 261 * TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init() 262 * just register a PCI device now, functionalities will be implemented later. 263 */ 264 265 static void vt82c686b_ac97_realize(PCIDevice *dev, Error **errp) 266 { 267 VT686AC97State *s = VT82C686B_AC97_DEVICE(dev); 268 uint8_t *pci_conf = s->dev.config; 269 270 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | 271 PCI_COMMAND_PARITY); 272 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST | 273 PCI_STATUS_DEVSEL_MEDIUM); 274 pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); 275 } 276 277 void vt82c686b_ac97_init(PCIBus *bus, int devfn) 278 { 279 PCIDevice *dev; 280 281 dev = pci_create(bus, devfn, TYPE_VT82C686B_AC97_DEVICE); 282 qdev_init_nofail(&dev->qdev); 283 } 284 285 static void via_ac97_class_init(ObjectClass *klass, void *data) 286 { 287 DeviceClass *dc = DEVICE_CLASS(klass); 288 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 289 290 k->realize = vt82c686b_ac97_realize; 291 k->vendor_id = PCI_VENDOR_ID_VIA; 292 k->device_id = PCI_DEVICE_ID_VIA_AC97; 293 k->revision = 0x50; 294 k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO; 295 set_bit(DEVICE_CATEGORY_SOUND, dc->categories); 296 dc->desc = "AC97"; 297 } 298 299 static const TypeInfo via_ac97_info = { 300 .name = TYPE_VT82C686B_AC97_DEVICE, 301 .parent = TYPE_PCI_DEVICE, 302 .instance_size = sizeof(VT686AC97State), 303 .class_init = via_ac97_class_init, 304 .interfaces = (InterfaceInfo[]) { 305 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 306 { }, 307 }, 308 }; 309 310 static void vt82c686b_mc97_realize(PCIDevice *dev, Error **errp) 311 { 312 VT686MC97State *s = VT82C686B_MC97_DEVICE(dev); 313 uint8_t *pci_conf = s->dev.config; 314 315 pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE | 316 PCI_COMMAND_VGA_PALETTE); 317 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM); 318 pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03); 319 } 320 321 void vt82c686b_mc97_init(PCIBus *bus, int devfn) 322 { 323 PCIDevice *dev; 324 325 dev = pci_create(bus, devfn, TYPE_VT82C686B_MC97_DEVICE); 326 qdev_init_nofail(&dev->qdev); 327 } 328 329 static void via_mc97_class_init(ObjectClass *klass, void *data) 330 { 331 DeviceClass *dc = DEVICE_CLASS(klass); 332 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 333 334 k->realize = vt82c686b_mc97_realize; 335 k->vendor_id = PCI_VENDOR_ID_VIA; 336 k->device_id = PCI_DEVICE_ID_VIA_MC97; 337 k->class_id = PCI_CLASS_COMMUNICATION_OTHER; 338 k->revision = 0x30; 339 set_bit(DEVICE_CATEGORY_NETWORK, dc->categories); 340 dc->desc = "MC97"; 341 } 342 343 static const TypeInfo via_mc97_info = { 344 .name = TYPE_VT82C686B_MC97_DEVICE, 345 .parent = TYPE_PCI_DEVICE, 346 .instance_size = sizeof(VT686MC97State), 347 .class_init = via_mc97_class_init, 348 .interfaces = (InterfaceInfo[]) { 349 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 350 { }, 351 }, 352 }; 353 354 /* vt82c686 pm init */ 355 static void vt82c686b_pm_realize(PCIDevice *dev, Error **errp) 356 { 357 VT686PMState *s = VT82C686B_PM_DEVICE(dev); 358 uint8_t *pci_conf; 359 360 pci_conf = s->dev.config; 361 pci_set_word(pci_conf + PCI_COMMAND, 0); 362 pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK | 363 PCI_STATUS_DEVSEL_MEDIUM); 364 365 /* 0x48-0x4B is Power Management I/O Base */ 366 pci_set_long(pci_conf + 0x48, 0x00000001); 367 368 /* SMB ports:0xeee0~0xeeef */ 369 s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0); 370 pci_conf[0x90] = s->smb_io_base | 1; 371 pci_conf[0x91] = s->smb_io_base >> 8; 372 pci_conf[0xd2] = 0x90; 373 pm_smbus_init(&s->dev.qdev, &s->smb); 374 memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io); 375 376 apm_init(dev, &s->apm, NULL, s); 377 378 memory_region_init(&s->io, OBJECT(dev), "vt82c686-pm", 64); 379 memory_region_set_enabled(&s->io, false); 380 memory_region_add_subregion(get_system_io(), 0, &s->io); 381 382 acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); 383 acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); 384 acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2); 385 } 386 387 I2CBus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 388 qemu_irq sci_irq) 389 { 390 PCIDevice *dev; 391 VT686PMState *s; 392 393 dev = pci_create(bus, devfn, TYPE_VT82C686B_PM_DEVICE); 394 qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base); 395 396 s = VT82C686B_PM_DEVICE(dev); 397 398 qdev_init_nofail(&dev->qdev); 399 400 return s->smb.smbus; 401 } 402 403 static Property via_pm_properties[] = { 404 DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0), 405 DEFINE_PROP_END_OF_LIST(), 406 }; 407 408 static void via_pm_class_init(ObjectClass *klass, void *data) 409 { 410 DeviceClass *dc = DEVICE_CLASS(klass); 411 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 412 413 k->realize = vt82c686b_pm_realize; 414 k->config_write = pm_write_config; 415 k->vendor_id = PCI_VENDOR_ID_VIA; 416 k->device_id = PCI_DEVICE_ID_VIA_ACPI; 417 k->class_id = PCI_CLASS_BRIDGE_OTHER; 418 k->revision = 0x40; 419 dc->desc = "PM"; 420 dc->vmsd = &vmstate_acpi; 421 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 422 dc->props = via_pm_properties; 423 } 424 425 static const TypeInfo via_pm_info = { 426 .name = TYPE_VT82C686B_PM_DEVICE, 427 .parent = TYPE_PCI_DEVICE, 428 .instance_size = sizeof(VT686PMState), 429 .class_init = via_pm_class_init, 430 .interfaces = (InterfaceInfo[]) { 431 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 432 { }, 433 }, 434 }; 435 436 static const VMStateDescription vmstate_via = { 437 .name = "vt82c686b", 438 .version_id = 1, 439 .minimum_version_id = 1, 440 .fields = (VMStateField[]) { 441 VMSTATE_PCI_DEVICE(dev, VT82C686BState), 442 VMSTATE_END_OF_LIST() 443 } 444 }; 445 446 /* init the PCI-to-ISA bridge */ 447 static void vt82c686b_realize(PCIDevice *d, Error **errp) 448 { 449 VT82C686BState *vt82c = VT82C686B_DEVICE(d); 450 uint8_t *pci_conf; 451 ISABus *isa_bus; 452 uint8_t *wmask; 453 int i; 454 455 isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), 456 pci_address_space_io(d), errp); 457 if (!isa_bus) { 458 return; 459 } 460 461 pci_conf = d->config; 462 pci_config_set_prog_interface(pci_conf, 0x0); 463 464 wmask = d->wmask; 465 for (i = 0x00; i < 0xff; i++) { 466 if (i<=0x03 || (i>=0x08 && i<=0x3f)) { 467 wmask[i] = 0x00; 468 } 469 } 470 471 memory_region_init_io(&vt82c->superio, OBJECT(d), &superio_ops, 472 &vt82c->superio_conf, "superio", 2); 473 memory_region_set_enabled(&vt82c->superio, false); 474 /* The floppy also uses 0x3f0 and 0x3f1. 475 * But we do not emulate a floppy, so just set it here. */ 476 memory_region_add_subregion(isa_bus->address_space_io, 0x3f0, 477 &vt82c->superio); 478 479 qemu_register_reset(vt82c686b_reset, d); 480 } 481 482 ISABus *vt82c686b_isa_init(PCIBus *bus, int devfn) 483 { 484 PCIDevice *d; 485 486 d = pci_create_simple_multifunction(bus, devfn, true, 487 TYPE_VT82C686B_DEVICE); 488 489 return ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0")); 490 } 491 492 static void via_class_init(ObjectClass *klass, void *data) 493 { 494 DeviceClass *dc = DEVICE_CLASS(klass); 495 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 496 497 k->realize = vt82c686b_realize; 498 k->config_write = vt82c686b_write_config; 499 k->vendor_id = PCI_VENDOR_ID_VIA; 500 k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE; 501 k->class_id = PCI_CLASS_BRIDGE_ISA; 502 k->revision = 0x40; 503 dc->desc = "ISA bridge"; 504 dc->vmsd = &vmstate_via; 505 /* 506 * Reason: part of VIA VT82C686 southbridge, needs to be wired up, 507 * e.g. by mips_fulong2e_init() 508 */ 509 dc->user_creatable = false; 510 } 511 512 static const TypeInfo via_info = { 513 .name = TYPE_VT82C686B_DEVICE, 514 .parent = TYPE_PCI_DEVICE, 515 .instance_size = sizeof(VT82C686BState), 516 .class_init = via_class_init, 517 .interfaces = (InterfaceInfo[]) { 518 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 519 { }, 520 }, 521 }; 522 523 static void vt82c686b_superio_class_init(ObjectClass *klass, void *data) 524 { 525 ISASuperIOClass *sc = ISA_SUPERIO_CLASS(klass); 526 527 sc->serial.count = 2; 528 sc->parallel.count = 1; 529 sc->ide.count = 0; 530 sc->floppy.count = 1; 531 } 532 533 static const TypeInfo via_superio_info = { 534 .name = TYPE_VT82C686B_SUPERIO, 535 .parent = TYPE_ISA_SUPERIO, 536 .instance_size = sizeof(ISASuperIODevice), 537 .class_size = sizeof(ISASuperIOClass), 538 .class_init = vt82c686b_superio_class_init, 539 }; 540 541 static void vt82c686b_register_types(void) 542 { 543 type_register_static(&via_ac97_info); 544 type_register_static(&via_mc97_info); 545 type_register_static(&via_pm_info); 546 type_register_static(&via_superio_info); 547 type_register_static(&via_info); 548 } 549 550 type_init(vt82c686b_register_types) 551