1 /*
2 * QEMU PIIX PCI ISA Bridge Emulation
3 *
4 * Copyright (c) 2006 Fabrice Bellard
5 * Copyright (c) 2018 Hervé Poussineau
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25
26 #include "qemu/osdep.h"
27 #include "qemu/range.h"
28 #include "qapi/error.h"
29 #include "hw/dma/i8257.h"
30 #include "hw/southbridge/piix.h"
31 #include "hw/timer/i8254.h"
32 #include "hw/irq.h"
33 #include "hw/qdev-properties.h"
34 #include "hw/ide/piix.h"
35 #include "hw/intc/i8259.h"
36 #include "hw/isa/isa.h"
37 #include "sysemu/runstate.h"
38 #include "migration/vmstate.h"
39 #include "hw/acpi/acpi_aml_interface.h"
40
piix_set_irq_pic(PIIXState * s,int pic_irq)41 static void piix_set_irq_pic(PIIXState *s, int pic_irq)
42 {
43 qemu_set_irq(s->isa_irqs_in[pic_irq],
44 !!(s->pic_levels &
45 (((1ULL << PIIX_NUM_PIRQS) - 1) <<
46 (pic_irq * PIIX_NUM_PIRQS))));
47 }
48
piix_set_pci_irq_level_internal(PIIXState * s,int pirq,int level)49 static void piix_set_pci_irq_level_internal(PIIXState *s, int pirq, int level)
50 {
51 int pic_irq;
52 uint64_t mask;
53
54 pic_irq = s->dev.config[PIIX_PIRQCA + pirq];
55 if (pic_irq >= ISA_NUM_IRQS) {
56 return;
57 }
58
59 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
60 s->pic_levels &= ~mask;
61 s->pic_levels |= mask * !!level;
62 }
63
piix_set_pci_irq_level(PIIXState * s,int pirq,int level)64 static void piix_set_pci_irq_level(PIIXState *s, int pirq, int level)
65 {
66 int pic_irq;
67
68 pic_irq = s->dev.config[PIIX_PIRQCA + pirq];
69 if (pic_irq >= ISA_NUM_IRQS) {
70 return;
71 }
72
73 piix_set_pci_irq_level_internal(s, pirq, level);
74
75 piix_set_irq_pic(s, pic_irq);
76 }
77
piix_set_pci_irq(void * opaque,int pirq,int level)78 static void piix_set_pci_irq(void *opaque, int pirq, int level)
79 {
80 PIIXState *s = opaque;
81 piix_set_pci_irq_level(s, pirq, level);
82 }
83
piix_request_i8259_irq(void * opaque,int irq,int level)84 static void piix_request_i8259_irq(void *opaque, int irq, int level)
85 {
86 PIIXState *s = opaque;
87 qemu_set_irq(s->cpu_intr, level);
88 }
89
piix_route_intx_pin_to_irq(void * opaque,int pin)90 static PCIINTxRoute piix_route_intx_pin_to_irq(void *opaque, int pin)
91 {
92 PCIDevice *pci_dev = opaque;
93 int irq = pci_dev->config[PIIX_PIRQCA + pin];
94 PCIINTxRoute route;
95
96 if (irq < ISA_NUM_IRQS) {
97 route.mode = PCI_INTX_ENABLED;
98 route.irq = irq;
99 } else {
100 route.mode = PCI_INTX_DISABLED;
101 route.irq = -1;
102 }
103 return route;
104 }
105
106 /* irq routing is changed. so rebuild bitmap */
piix_update_pci_irq_levels(PIIXState * s)107 static void piix_update_pci_irq_levels(PIIXState *s)
108 {
109 PCIBus *bus = pci_get_bus(&s->dev);
110 int pirq;
111
112 s->pic_levels = 0;
113 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
114 piix_set_pci_irq_level(s, pirq, pci_bus_get_irq_level(bus, pirq));
115 }
116 }
117
piix_write_config(PCIDevice * dev,uint32_t address,uint32_t val,int len)118 static void piix_write_config(PCIDevice *dev, uint32_t address, uint32_t val,
119 int len)
120 {
121 pci_default_write_config(dev, address, val, len);
122 if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
123 PIIXState *s = PIIX_PCI_DEVICE(dev);
124 int pic_irq;
125
126 pci_bus_fire_intx_routing_notifier(pci_get_bus(&s->dev));
127 piix_update_pci_irq_levels(s);
128 for (pic_irq = 0; pic_irq < ISA_NUM_IRQS; pic_irq++) {
129 piix_set_irq_pic(s, pic_irq);
130 }
131 }
132 }
133
piix_reset(DeviceState * dev)134 static void piix_reset(DeviceState *dev)
135 {
136 PIIXState *d = PIIX_PCI_DEVICE(dev);
137 uint8_t *pci_conf = d->dev.config;
138
139 pci_conf[0x04] = 0x07; /* master, memory and I/O */
140 pci_conf[0x05] = 0x00;
141 pci_conf[0x06] = 0x00;
142 pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
143 pci_conf[0x4c] = 0x4d;
144 pci_conf[0x4e] = 0x03;
145 pci_conf[0x4f] = 0x00;
146 pci_conf[0x60] = 0x80;
147 pci_conf[0x61] = 0x80;
148 pci_conf[0x62] = 0x80;
149 pci_conf[0x63] = 0x80;
150 pci_conf[0x69] = 0x02;
151 pci_conf[0x70] = 0x80;
152 pci_conf[0x76] = 0x0c;
153 pci_conf[0x77] = 0x0c;
154 pci_conf[0x78] = 0x02;
155 pci_conf[0x79] = 0x00;
156 pci_conf[0x80] = 0x00;
157 pci_conf[0x82] = 0x00;
158 pci_conf[0xa0] = 0x08;
159 pci_conf[0xa2] = 0x00;
160 pci_conf[0xa3] = 0x00;
161 pci_conf[0xa4] = 0x00;
162 pci_conf[0xa5] = 0x00;
163 pci_conf[0xa6] = 0x00;
164 pci_conf[0xa7] = 0x00;
165 pci_conf[0xa8] = 0x0f;
166 pci_conf[0xaa] = 0x00;
167 pci_conf[0xab] = 0x00;
168 pci_conf[0xac] = 0x00;
169 pci_conf[0xae] = 0x00;
170
171 d->pic_levels = 0;
172 d->rcr = 0;
173 }
174
piix_post_load(void * opaque,int version_id)175 static int piix_post_load(void *opaque, int version_id)
176 {
177 PIIXState *s = opaque;
178 int pirq;
179
180 /*
181 * Because the i8259 has not been deserialized yet, qemu_irq_raise
182 * might bring the system to a different state than the saved one;
183 * for example, the interrupt could be masked but the i8259 would
184 * not know that yet and would trigger an interrupt in the CPU.
185 *
186 * Here, we update irq levels without raising the interrupt.
187 * Interrupt state will be deserialized separately through the i8259.
188 */
189 s->pic_levels = 0;
190 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
191 piix_set_pci_irq_level_internal(s, pirq,
192 pci_bus_get_irq_level(pci_get_bus(&s->dev), pirq));
193 }
194 return 0;
195 }
196
piix4_post_load(void * opaque,int version_id)197 static int piix4_post_load(void *opaque, int version_id)
198 {
199 PIIXState *s = opaque;
200
201 if (version_id == 2) {
202 s->rcr = 0;
203 }
204
205 return piix_post_load(opaque, version_id);
206 }
207
piix3_pre_save(void * opaque)208 static int piix3_pre_save(void *opaque)
209 {
210 int i;
211 PIIXState *piix3 = opaque;
212
213 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
214 piix3->pci_irq_levels_vmstate[i] =
215 pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
216 }
217
218 return 0;
219 }
220
piix3_rcr_needed(void * opaque)221 static bool piix3_rcr_needed(void *opaque)
222 {
223 PIIXState *piix3 = opaque;
224
225 return (piix3->rcr != 0);
226 }
227
228 static const VMStateDescription vmstate_piix3_rcr = {
229 .name = "PIIX3/rcr",
230 .version_id = 1,
231 .minimum_version_id = 1,
232 .needed = piix3_rcr_needed,
233 .fields = (const VMStateField[]) {
234 VMSTATE_UINT8(rcr, PIIXState),
235 VMSTATE_END_OF_LIST()
236 }
237 };
238
239 static const VMStateDescription vmstate_piix3 = {
240 .name = "PIIX3",
241 .version_id = 3,
242 .minimum_version_id = 2,
243 .post_load = piix_post_load,
244 .pre_save = piix3_pre_save,
245 .fields = (const VMStateField[]) {
246 VMSTATE_PCI_DEVICE(dev, PIIXState),
247 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIXState,
248 PIIX_NUM_PIRQS, 3),
249 VMSTATE_END_OF_LIST()
250 },
251 .subsections = (const VMStateDescription * const []) {
252 &vmstate_piix3_rcr,
253 NULL
254 }
255 };
256
257 static const VMStateDescription vmstate_piix4 = {
258 .name = "PIIX4",
259 .version_id = 3,
260 .minimum_version_id = 2,
261 .post_load = piix4_post_load,
262 .fields = (const VMStateField[]) {
263 VMSTATE_PCI_DEVICE(dev, PIIXState),
264 VMSTATE_UINT8_V(rcr, PIIXState, 3),
265 VMSTATE_END_OF_LIST()
266 }
267 };
268
rcr_write(void * opaque,hwaddr addr,uint64_t val,unsigned len)269 static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
270 {
271 PIIXState *d = opaque;
272
273 if (val & 4) {
274 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
275 return;
276 }
277 d->rcr = val & 2; /* keep System Reset type only */
278 }
279
rcr_read(void * opaque,hwaddr addr,unsigned len)280 static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
281 {
282 PIIXState *d = opaque;
283
284 return d->rcr;
285 }
286
287 static const MemoryRegionOps rcr_ops = {
288 .read = rcr_read,
289 .write = rcr_write,
290 .endianness = DEVICE_LITTLE_ENDIAN,
291 .impl = {
292 .min_access_size = 1,
293 .max_access_size = 1,
294 },
295 };
296
pci_piix_realize(PCIDevice * dev,const char * uhci_type,Error ** errp)297 static void pci_piix_realize(PCIDevice *dev, const char *uhci_type,
298 Error **errp)
299 {
300 PIIXState *d = PIIX_PCI_DEVICE(dev);
301 PCIBus *pci_bus = pci_get_bus(dev);
302 ISABus *isa_bus;
303 uint32_t irq;
304
305 isa_bus = isa_bus_new(DEVICE(d), pci_address_space(dev),
306 pci_address_space_io(dev), errp);
307 if (!isa_bus) {
308 return;
309 }
310
311 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
312 "piix-reset-control", 1);
313 memory_region_add_subregion_overlap(pci_address_space_io(dev),
314 PIIX_RCR_IOPORT, &d->rcr_mem, 1);
315
316 /* PIC */
317 if (d->has_pic) {
318 qemu_irq *i8259_out_irq = qemu_allocate_irqs(piix_request_i8259_irq, d,
319 1);
320 qemu_irq *i8259 = i8259_init(isa_bus, *i8259_out_irq);
321 size_t i;
322
323 for (i = 0; i < ISA_NUM_IRQS; i++) {
324 d->isa_irqs_in[i] = i8259[i];
325 }
326
327 g_free(i8259);
328
329 qdev_init_gpio_out_named(DEVICE(dev), &d->cpu_intr, "intr", 1);
330 }
331
332 isa_bus_register_input_irqs(isa_bus, d->isa_irqs_in);
333
334 /* PIT */
335 if (d->has_pit) {
336 i8254_pit_init(isa_bus, 0x40, 0, NULL);
337 }
338
339 i8257_dma_init(OBJECT(dev), isa_bus, 0);
340
341 /* RTC */
342 qdev_prop_set_int32(DEVICE(&d->rtc), "base_year", 2000);
343 if (!qdev_realize(DEVICE(&d->rtc), BUS(isa_bus), errp)) {
344 return;
345 }
346 irq = object_property_get_uint(OBJECT(&d->rtc), "irq", &error_fatal);
347 isa_connect_gpio_out(ISA_DEVICE(&d->rtc), 0, irq);
348
349 /* IDE */
350 qdev_prop_set_int32(DEVICE(&d->ide), "addr", dev->devfn + 1);
351 if (!qdev_realize(DEVICE(&d->ide), BUS(pci_bus), errp)) {
352 return;
353 }
354
355 /* USB */
356 if (d->has_usb) {
357 object_initialize_child(OBJECT(dev), "uhci", &d->uhci, uhci_type);
358 qdev_prop_set_int32(DEVICE(&d->uhci), "addr", dev->devfn + 2);
359 if (!qdev_realize(DEVICE(&d->uhci), BUS(pci_bus), errp)) {
360 return;
361 }
362 }
363
364 /* Power Management */
365 if (d->has_acpi) {
366 object_initialize_child(OBJECT(d), "pm", &d->pm, TYPE_PIIX4_PM);
367 qdev_prop_set_int32(DEVICE(&d->pm), "addr", dev->devfn + 3);
368 qdev_prop_set_uint32(DEVICE(&d->pm), "smb_io_base", d->smb_io_base);
369 qdev_prop_set_bit(DEVICE(&d->pm), "smm-enabled", d->smm_enabled);
370 if (!qdev_realize(DEVICE(&d->pm), BUS(pci_bus), errp)) {
371 return;
372 }
373 qdev_connect_gpio_out(DEVICE(&d->pm), 0, d->isa_irqs_in[9]);
374 }
375
376 pci_bus_irqs(pci_bus, piix_set_pci_irq, d, PIIX_NUM_PIRQS);
377 pci_bus_set_route_irq_fn(pci_bus, piix_route_intx_pin_to_irq);
378 }
379
build_pci_isa_aml(AcpiDevAmlIf * adev,Aml * scope)380 static void build_pci_isa_aml(AcpiDevAmlIf *adev, Aml *scope)
381 {
382 Aml *field;
383 Aml *sb_scope = aml_scope("\\_SB");
384 BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0");
385
386 /* PIIX PCI to ISA irq remapping */
387 aml_append(scope, aml_operation_region("P40C", AML_PCI_CONFIG,
388 aml_int(0x60), 0x04));
389 /* Fields declarion has to happen *after* operation region */
390 field = aml_field("PCI0.S08.P40C", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE);
391 aml_append(field, aml_named_field("PRQ0", 8));
392 aml_append(field, aml_named_field("PRQ1", 8));
393 aml_append(field, aml_named_field("PRQ2", 8));
394 aml_append(field, aml_named_field("PRQ3", 8));
395 aml_append(sb_scope, field);
396 aml_append(scope, sb_scope);
397
398 qbus_build_aml(bus, scope);
399 }
400
pci_piix_init(Object * obj)401 static void pci_piix_init(Object *obj)
402 {
403 PIIXState *d = PIIX_PCI_DEVICE(obj);
404
405 qdev_init_gpio_out_named(DEVICE(obj), d->isa_irqs_in, "isa-irqs",
406 ISA_NUM_IRQS);
407
408 object_initialize_child(obj, "rtc", &d->rtc, TYPE_MC146818_RTC);
409 }
410
411 static Property pci_piix_props[] = {
412 DEFINE_PROP_UINT32("smb_io_base", PIIXState, smb_io_base, 0),
413 DEFINE_PROP_BOOL("has-acpi", PIIXState, has_acpi, true),
414 DEFINE_PROP_BOOL("has-pic", PIIXState, has_pic, true),
415 DEFINE_PROP_BOOL("has-pit", PIIXState, has_pit, true),
416 DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true),
417 DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false),
418 DEFINE_PROP_END_OF_LIST(),
419 };
420
pci_piix_class_init(ObjectClass * klass,void * data)421 static void pci_piix_class_init(ObjectClass *klass, void *data)
422 {
423 DeviceClass *dc = DEVICE_CLASS(klass);
424 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
425 AcpiDevAmlIfClass *adevc = ACPI_DEV_AML_IF_CLASS(klass);
426
427 k->config_write = piix_write_config;
428 device_class_set_legacy_reset(dc, piix_reset);
429 dc->desc = "ISA bridge";
430 dc->hotpluggable = false;
431 k->vendor_id = PCI_VENDOR_ID_INTEL;
432 k->class_id = PCI_CLASS_BRIDGE_ISA;
433 /*
434 * Reason: part of PIIX southbridge, needs to be wired up by e.g.
435 * pc_piix.c's pc_init1()
436 */
437 dc->user_creatable = false;
438 device_class_set_props(dc, pci_piix_props);
439 adevc->build_dev_aml = build_pci_isa_aml;
440 }
441
442 static const TypeInfo piix_pci_type_info = {
443 .name = TYPE_PIIX_PCI_DEVICE,
444 .parent = TYPE_PCI_DEVICE,
445 .instance_size = sizeof(PIIXState),
446 .instance_init = pci_piix_init,
447 .abstract = true,
448 .class_init = pci_piix_class_init,
449 .interfaces = (InterfaceInfo[]) {
450 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
451 { TYPE_ACPI_DEV_AML_IF },
452 { },
453 },
454 };
455
piix3_realize(PCIDevice * dev,Error ** errp)456 static void piix3_realize(PCIDevice *dev, Error **errp)
457 {
458 pci_piix_realize(dev, TYPE_PIIX3_USB_UHCI, errp);
459 }
460
piix3_init(Object * obj)461 static void piix3_init(Object *obj)
462 {
463 PIIXState *d = PIIX_PCI_DEVICE(obj);
464
465 object_initialize_child(obj, "ide", &d->ide, TYPE_PIIX3_IDE);
466 }
467
piix3_class_init(ObjectClass * klass,void * data)468 static void piix3_class_init(ObjectClass *klass, void *data)
469 {
470 DeviceClass *dc = DEVICE_CLASS(klass);
471 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
472
473 k->realize = piix3_realize;
474 /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
475 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
476 dc->vmsd = &vmstate_piix3;
477 }
478
479 static const TypeInfo piix3_info = {
480 .name = TYPE_PIIX3_DEVICE,
481 .parent = TYPE_PIIX_PCI_DEVICE,
482 .instance_init = piix3_init,
483 .class_init = piix3_class_init,
484 };
485
piix4_realize(PCIDevice * dev,Error ** errp)486 static void piix4_realize(PCIDevice *dev, Error **errp)
487 {
488 pci_piix_realize(dev, TYPE_PIIX4_USB_UHCI, errp);
489 }
490
piix4_init(Object * obj)491 static void piix4_init(Object *obj)
492 {
493 PIIXState *s = PIIX_PCI_DEVICE(obj);
494
495 object_initialize_child(obj, "ide", &s->ide, TYPE_PIIX4_IDE);
496 }
497
piix4_class_init(ObjectClass * klass,void * data)498 static void piix4_class_init(ObjectClass *klass, void *data)
499 {
500 DeviceClass *dc = DEVICE_CLASS(klass);
501 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
502
503 k->realize = piix4_realize;
504 k->device_id = PCI_DEVICE_ID_INTEL_82371AB_0;
505 dc->vmsd = &vmstate_piix4;
506 }
507
508 static const TypeInfo piix4_info = {
509 .name = TYPE_PIIX4_PCI_DEVICE,
510 .parent = TYPE_PIIX_PCI_DEVICE,
511 .instance_init = piix4_init,
512 .class_init = piix4_class_init,
513 };
514
piix3_register_types(void)515 static void piix3_register_types(void)
516 {
517 type_register_static(&piix_pci_type_info);
518 type_register_static(&piix3_info);
519 type_register_static(&piix4_info);
520 }
521
522 type_init(piix3_register_types)
523