1 /* 2 * QEMU National Semiconductor PC87312 (Super I/O) 3 * 4 * Copyright (c) 2010-2012 Herve Poussineau 5 * Copyright (c) 2011-2012 Andreas Färber 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "hw/isa/pc87312.h" 27 #include "qemu/error-report.h" 28 #include "sysemu/blockdev.h" 29 #include "sysemu/sysemu.h" 30 #include "sysemu/char.h" 31 #include "trace.h" 32 33 34 #define REG_FER 0 35 #define REG_FAR 1 36 #define REG_PTR 2 37 38 #define FER_PARALLEL_EN 0x01 39 #define FER_UART1_EN 0x02 40 #define FER_UART2_EN 0x04 41 #define FER_FDC_EN 0x08 42 #define FER_FDC_4 0x10 43 #define FER_FDC_ADDR 0x20 44 #define FER_IDE_EN 0x40 45 #define FER_IDE_ADDR 0x80 46 47 #define FAR_PARALLEL_ADDR 0x03 48 #define FAR_UART1_ADDR 0x0C 49 #define FAR_UART2_ADDR 0x30 50 #define FAR_UART_3_4 0xC0 51 52 #define PTR_POWER_DOWN 0x01 53 #define PTR_CLOCK_DOWN 0x02 54 #define PTR_PWDN 0x04 55 #define PTR_IRQ_5_7 0x08 56 #define PTR_UART1_TEST 0x10 57 #define PTR_UART2_TEST 0x20 58 #define PTR_LOCK_CONF 0x40 59 #define PTR_EPP_MODE 0x80 60 61 62 /* Parallel port */ 63 64 static inline bool is_parallel_enabled(PC87312State *s) 65 { 66 return s->regs[REG_FER] & FER_PARALLEL_EN; 67 } 68 69 static const uint32_t parallel_base[] = { 0x378, 0x3bc, 0x278, 0x00 }; 70 71 static inline uint32_t get_parallel_iobase(PC87312State *s) 72 { 73 return parallel_base[s->regs[REG_FAR] & FAR_PARALLEL_ADDR]; 74 } 75 76 static const uint32_t parallel_irq[] = { 5, 7, 5, 0 }; 77 78 static inline uint32_t get_parallel_irq(PC87312State *s) 79 { 80 int idx; 81 idx = (s->regs[REG_FAR] & FAR_PARALLEL_ADDR); 82 if (idx == 0) { 83 return (s->regs[REG_PTR] & PTR_IRQ_5_7) ? 7 : 5; 84 } else { 85 return parallel_irq[idx]; 86 } 87 } 88 89 90 /* UARTs */ 91 92 static const uint32_t uart_base[2][4] = { 93 { 0x3e8, 0x338, 0x2e8, 0x220 }, 94 { 0x2e8, 0x238, 0x2e0, 0x228 } 95 }; 96 97 static inline uint32_t get_uart_iobase(PC87312State *s, int i) 98 { 99 int idx; 100 idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3; 101 if (idx == 0) { 102 return 0x3f8; 103 } else if (idx == 1) { 104 return 0x2f8; 105 } else { 106 return uart_base[idx & 1][(s->regs[REG_FAR] & FAR_UART_3_4) >> 6]; 107 } 108 } 109 110 static inline uint32_t get_uart_irq(PC87312State *s, int i) 111 { 112 int idx; 113 idx = (s->regs[REG_FAR] >> (2 * i + 2)) & 0x3; 114 return (idx & 1) ? 3 : 4; 115 } 116 117 static inline bool is_uart_enabled(PC87312State *s, int i) 118 { 119 return s->regs[REG_FER] & (FER_UART1_EN << i); 120 } 121 122 123 /* Floppy controller */ 124 125 static inline bool is_fdc_enabled(PC87312State *s) 126 { 127 return s->regs[REG_FER] & FER_FDC_EN; 128 } 129 130 static inline uint32_t get_fdc_iobase(PC87312State *s) 131 { 132 return (s->regs[REG_FER] & FER_FDC_ADDR) ? 0x370 : 0x3f0; 133 } 134 135 136 /* IDE controller */ 137 138 static inline bool is_ide_enabled(PC87312State *s) 139 { 140 return s->regs[REG_FER] & FER_IDE_EN; 141 } 142 143 static inline uint32_t get_ide_iobase(PC87312State *s) 144 { 145 return (s->regs[REG_FER] & FER_IDE_ADDR) ? 0x170 : 0x1f0; 146 } 147 148 149 static void reconfigure_devices(PC87312State *s) 150 { 151 error_report("pc87312: unsupported device reconfiguration (%02x %02x %02x)", 152 s->regs[REG_FER], s->regs[REG_FAR], s->regs[REG_PTR]); 153 } 154 155 static void pc87312_soft_reset(PC87312State *s) 156 { 157 static const uint8_t fer_init[] = { 158 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4f, 0x4b, 0x4b, 159 0x4b, 0x4b, 0x4b, 0x4b, 0x0f, 0x0f, 0x0f, 0x0f, 160 0x49, 0x49, 0x49, 0x49, 0x07, 0x07, 0x07, 0x07, 161 0x47, 0x47, 0x47, 0x47, 0x47, 0x47, 0x08, 0x00, 162 }; 163 static const uint8_t far_init[] = { 164 0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x00, 0x01, 165 0x01, 0x09, 0x08, 0x08, 0x10, 0x11, 0x39, 0x24, 166 0x00, 0x01, 0x01, 0x00, 0x10, 0x11, 0x39, 0x24, 167 0x10, 0x11, 0x11, 0x39, 0x24, 0x38, 0x10, 0x10, 168 }; 169 static const uint8_t ptr_init[] = { 170 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 171 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 172 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 173 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 174 }; 175 176 s->read_id_step = 0; 177 s->selected_index = REG_FER; 178 179 s->regs[REG_FER] = fer_init[s->config & 0x1f]; 180 s->regs[REG_FAR] = far_init[s->config & 0x1f]; 181 s->regs[REG_PTR] = ptr_init[s->config & 0x1f]; 182 } 183 184 static void pc87312_hard_reset(PC87312State *s) 185 { 186 pc87312_soft_reset(s); 187 } 188 189 static void pc87312_io_write(void *opaque, hwaddr addr, uint64_t val, 190 unsigned int size) 191 { 192 PC87312State *s = opaque; 193 194 trace_pc87312_io_write(addr, val); 195 196 if ((addr & 1) == 0) { 197 /* Index register */ 198 s->read_id_step = 2; 199 s->selected_index = val; 200 } else { 201 /* Data register */ 202 if (s->selected_index < 3) { 203 s->regs[s->selected_index] = val; 204 reconfigure_devices(s); 205 } 206 } 207 } 208 209 static uint64_t pc87312_io_read(void *opaque, hwaddr addr, unsigned int size) 210 { 211 PC87312State *s = opaque; 212 uint32_t val; 213 214 if ((addr & 1) == 0) { 215 /* Index register */ 216 if (s->read_id_step++ == 0) { 217 val = 0x88; 218 } else if (s->read_id_step++ == 1) { 219 val = 0; 220 } else { 221 val = s->selected_index; 222 } 223 } else { 224 /* Data register */ 225 if (s->selected_index < 3) { 226 val = s->regs[s->selected_index]; 227 } else { 228 /* Invalid selected index */ 229 val = 0; 230 } 231 } 232 233 trace_pc87312_io_read(addr, val); 234 return val; 235 } 236 237 static const MemoryRegionOps pc87312_io_ops = { 238 .read = pc87312_io_read, 239 .write = pc87312_io_write, 240 .endianness = DEVICE_LITTLE_ENDIAN, 241 .valid = { 242 .min_access_size = 1, 243 .max_access_size = 1, 244 }, 245 }; 246 247 static int pc87312_post_load(void *opaque, int version_id) 248 { 249 PC87312State *s = opaque; 250 251 reconfigure_devices(s); 252 return 0; 253 } 254 255 static void pc87312_reset(DeviceState *d) 256 { 257 PC87312State *s = PC87312(d); 258 259 pc87312_soft_reset(s); 260 } 261 262 static void pc87312_realize(DeviceState *dev, Error **errp) 263 { 264 PC87312State *s; 265 DeviceState *d; 266 ISADevice *isa; 267 ISABus *bus; 268 CharDriverState *chr; 269 DriveInfo *drive; 270 char name[5]; 271 int i; 272 273 s = PC87312(dev); 274 isa = ISA_DEVICE(dev); 275 bus = isa_bus_from_device(isa); 276 isa_register_ioport(isa, &s->io, s->iobase); 277 pc87312_hard_reset(s); 278 279 if (is_parallel_enabled(s)) { 280 chr = parallel_hds[0]; 281 if (chr == NULL) { 282 chr = qemu_chr_new("par0", "null", NULL); 283 } 284 isa = isa_create(bus, "isa-parallel"); 285 d = DEVICE(isa); 286 qdev_prop_set_uint32(d, "index", 0); 287 qdev_prop_set_uint32(d, "iobase", get_parallel_iobase(s)); 288 qdev_prop_set_uint32(d, "irq", get_parallel_irq(s)); 289 qdev_prop_set_chr(d, "chardev", chr); 290 qdev_init_nofail(d); 291 s->parallel.dev = isa; 292 trace_pc87312_info_parallel(get_parallel_iobase(s), 293 get_parallel_irq(s)); 294 } 295 296 for (i = 0; i < 2; i++) { 297 if (is_uart_enabled(s, i)) { 298 chr = serial_hds[i]; 299 if (chr == NULL) { 300 snprintf(name, sizeof(name), "ser%d", i); 301 chr = qemu_chr_new(name, "null", NULL); 302 } 303 isa = isa_create(bus, "isa-serial"); 304 d = DEVICE(isa); 305 qdev_prop_set_uint32(d, "index", i); 306 qdev_prop_set_uint32(d, "iobase", get_uart_iobase(s, i)); 307 qdev_prop_set_uint32(d, "irq", get_uart_irq(s, i)); 308 qdev_prop_set_chr(d, "chardev", chr); 309 qdev_init_nofail(d); 310 s->uart[i].dev = isa; 311 trace_pc87312_info_serial(i, get_uart_iobase(s, i), 312 get_uart_irq(s, i)); 313 } 314 } 315 316 if (is_fdc_enabled(s)) { 317 isa = isa_create(bus, "isa-fdc"); 318 d = DEVICE(isa); 319 qdev_prop_set_uint32(d, "iobase", get_fdc_iobase(s)); 320 qdev_prop_set_uint32(d, "irq", 6); 321 drive = drive_get(IF_FLOPPY, 0, 0); 322 if (drive != NULL) { 323 qdev_prop_set_drive_nofail(d, "driveA", drive->bdrv); 324 } 325 drive = drive_get(IF_FLOPPY, 0, 1); 326 if (drive != NULL) { 327 qdev_prop_set_drive_nofail(d, "driveB", drive->bdrv); 328 } 329 qdev_init_nofail(d); 330 s->fdc.dev = isa; 331 trace_pc87312_info_floppy(get_fdc_iobase(s)); 332 } 333 334 if (is_ide_enabled(s)) { 335 isa = isa_create(bus, "isa-ide"); 336 d = DEVICE(isa); 337 qdev_prop_set_uint32(d, "iobase", get_ide_iobase(s)); 338 qdev_prop_set_uint32(d, "iobase2", get_ide_iobase(s) + 0x206); 339 qdev_prop_set_uint32(d, "irq", 14); 340 qdev_init_nofail(d); 341 s->ide.dev = isa; 342 trace_pc87312_info_ide(get_ide_iobase(s)); 343 } 344 } 345 346 static void pc87312_initfn(Object *obj) 347 { 348 PC87312State *s = PC87312(obj); 349 350 memory_region_init_io(&s->io, obj, &pc87312_io_ops, s, "pc87312", 2); 351 } 352 353 static const VMStateDescription vmstate_pc87312 = { 354 .name = "pc87312", 355 .version_id = 1, 356 .minimum_version_id = 1, 357 .post_load = pc87312_post_load, 358 .fields = (VMStateField[]) { 359 VMSTATE_UINT8(read_id_step, PC87312State), 360 VMSTATE_UINT8(selected_index, PC87312State), 361 VMSTATE_UINT8_ARRAY(regs, PC87312State, 3), 362 VMSTATE_END_OF_LIST() 363 } 364 }; 365 366 static Property pc87312_properties[] = { 367 DEFINE_PROP_UINT32("iobase", PC87312State, iobase, 0x398), 368 DEFINE_PROP_UINT8("config", PC87312State, config, 1), 369 DEFINE_PROP_END_OF_LIST() 370 }; 371 372 static void pc87312_class_init(ObjectClass *klass, void *data) 373 { 374 DeviceClass *dc = DEVICE_CLASS(klass); 375 376 dc->realize = pc87312_realize; 377 dc->reset = pc87312_reset; 378 dc->vmsd = &vmstate_pc87312; 379 dc->props = pc87312_properties; 380 } 381 382 static const TypeInfo pc87312_type_info = { 383 .name = TYPE_PC87312, 384 .parent = TYPE_ISA_DEVICE, 385 .instance_size = sizeof(PC87312State), 386 .instance_init = pc87312_initfn, 387 .class_init = pc87312_class_init, 388 }; 389 390 static void pc87312_register_types(void) 391 { 392 type_register_static(&pc87312_type_info); 393 } 394 395 type_init(pc87312_register_types) 396