xref: /openbmc/qemu/hw/isa/lpc_ich9.c (revision a6e03739)
1 /*
2  * QEMU ICH9 Emulation
3  *
4  * Copyright (c) 2006 Fabrice Bellard
5  * Copyright (c) 2009, 2010, 2011
6  *               Isaku Yamahata <yamahata at valinux co jp>
7  *               VA Linux Systems Japan K.K.
8  * Copyright (C) 2012 Jason Baron <jbaron@redhat.com>
9  *
10  * This is based on piix.c, but heavily modified.
11  *
12  * Permission is hereby granted, free of charge, to any person obtaining a copy
13  * of this software and associated documentation files (the "Software"), to deal
14  * in the Software without restriction, including without limitation the rights
15  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
16  * copies of the Software, and to permit persons to whom the Software is
17  * furnished to do so, subject to the following conditions:
18  *
19  * The above copyright notice and this permission notice shall be included in
20  * all copies or substantial portions of the Software.
21  *
22  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
26  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
27  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
28  * THE SOFTWARE.
29  */
30 
31 #include "qemu/osdep.h"
32 #include "qemu/log.h"
33 #include "cpu.h"
34 #include "qapi/visitor.h"
35 #include "qemu/range.h"
36 #include "hw/isa/isa.h"
37 #include "hw/sysbus.h"
38 #include "migration/vmstate.h"
39 #include "hw/irq.h"
40 #include "hw/isa/apm.h"
41 #include "hw/pci/pci.h"
42 #include "hw/pci/pci_bridge.h"
43 #include "hw/i386/ich9.h"
44 #include "hw/acpi/acpi.h"
45 #include "hw/acpi/ich9.h"
46 #include "hw/pci/pci_bus.h"
47 #include "hw/qdev-properties.h"
48 #include "exec/address-spaces.h"
49 #include "sysemu/runstate.h"
50 #include "sysemu/sysemu.h"
51 #include "hw/core/cpu.h"
52 #include "hw/nvram/fw_cfg.h"
53 #include "qemu/cutils.h"
54 
55 /*****************************************************************************/
56 /* ICH9 LPC PCI to ISA bridge */
57 
58 static void ich9_lpc_reset(DeviceState *qdev);
59 
60 /* chipset configuration register
61  * to access chipset configuration registers, pci_[sg]et_{byte, word, long}
62  * are used.
63  * Although it's not pci configuration space, it's little endian as Intel.
64  */
65 
66 static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir)
67 {
68     int intx;
69     for (intx = 0; intx < PCI_NUM_PINS; intx++) {
70         irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK;
71     }
72 }
73 
74 static void ich9_cc_update(ICH9LPCState *lpc)
75 {
76     int slot;
77     int pci_intx;
78 
79     const int reg_offsets[] = {
80         ICH9_CC_D25IR,
81         ICH9_CC_D26IR,
82         ICH9_CC_D27IR,
83         ICH9_CC_D28IR,
84         ICH9_CC_D29IR,
85         ICH9_CC_D30IR,
86         ICH9_CC_D31IR,
87     };
88     const int *offset;
89 
90     /* D{25 - 31}IR, but D30IR is read only to 0. */
91     for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) {
92         if (slot == 30) {
93             continue;
94         }
95         ich9_cc_update_ir(lpc->irr[slot],
96                           pci_get_word(lpc->chip_config + *offset));
97     }
98 
99     /*
100      * D30: DMI2PCI bridge
101      * It is arbitrarily decided how INTx lines of PCI devices behind
102      * the bridge are connected to pirq lines. Our choice is PIRQ[E-H].
103      * INT[A-D] are connected to PIRQ[E-H]
104      */
105     for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) {
106         lpc->irr[30][pci_intx] = pci_intx + 4;
107     }
108 }
109 
110 static void ich9_cc_init(ICH9LPCState *lpc)
111 {
112     int slot;
113     int intx;
114 
115     /* the default irq routing is arbitrary as long as it matches with
116      * acpi irq routing table.
117      * The one that is incompatible with piix_pci(= bochs) one is
118      * intentionally chosen to let the users know that the different
119      * board is used.
120      *
121      * int[A-D] -> pirq[E-F]
122      * avoid pirq A-D because they are used for pci express port
123      */
124     for (slot = 0; slot < PCI_SLOT_MAX; slot++) {
125         for (intx = 0; intx < PCI_NUM_PINS; intx++) {
126             lpc->irr[slot][intx] = (slot + intx) % 4 + 4;
127         }
128     }
129     ich9_cc_update(lpc);
130 }
131 
132 static void ich9_cc_reset(ICH9LPCState *lpc)
133 {
134     uint8_t *c = lpc->chip_config;
135 
136     memset(lpc->chip_config, 0, sizeof(lpc->chip_config));
137 
138     pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT);
139     pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT);
140     pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT);
141     pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT);
142     pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT);
143     pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT);
144     pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT);
145     pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT);
146 
147     ich9_cc_update(lpc);
148 }
149 
150 static void ich9_cc_addr_len(uint64_t *addr, unsigned *len)
151 {
152     *addr &= ICH9_CC_ADDR_MASK;
153     if (*addr + *len >= ICH9_CC_SIZE) {
154         *len = ICH9_CC_SIZE - *addr;
155     }
156 }
157 
158 /* val: little endian */
159 static void ich9_cc_write(void *opaque, hwaddr addr,
160                           uint64_t val, unsigned len)
161 {
162     ICH9LPCState *lpc = (ICH9LPCState *)opaque;
163 
164     ich9_cc_addr_len(&addr, &len);
165     memcpy(lpc->chip_config + addr, &val, len);
166     pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
167     ich9_cc_update(lpc);
168 }
169 
170 /* return value: little endian */
171 static uint64_t ich9_cc_read(void *opaque, hwaddr addr,
172                               unsigned len)
173 {
174     ICH9LPCState *lpc = (ICH9LPCState *)opaque;
175 
176     uint32_t val = 0;
177     ich9_cc_addr_len(&addr, &len);
178     memcpy(&val, lpc->chip_config + addr, len);
179     return val;
180 }
181 
182 /* IRQ routing */
183 /* */
184 static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis)
185 {
186     *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK;
187     *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN;
188 }
189 
190 static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num,
191                              int *pic_irq, int *pic_dis)
192 {
193     switch (pirq_num) {
194     case 0 ... 3: /* A-D */
195         ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num],
196                       pic_irq, pic_dis);
197         return;
198     case 4 ... 7: /* E-H */
199         ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)],
200                       pic_irq, pic_dis);
201         return;
202     default:
203         break;
204     }
205     abort();
206 }
207 
208 /* gsi: i8259+ioapic irq 0-15, otherwise assert */
209 static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi)
210 {
211     int i, pic_level;
212 
213     assert(gsi < ICH9_LPC_PIC_NUM_PINS);
214 
215     /* The pic level is the logical OR of all the PCI irqs mapped to it */
216     pic_level = 0;
217     for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) {
218         int tmp_irq;
219         int tmp_dis;
220         ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis);
221         if (!tmp_dis && tmp_irq == gsi) {
222             pic_level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), i);
223         }
224     }
225     if (gsi == lpc->sci_gsi) {
226         pic_level |= lpc->sci_level;
227     }
228 
229     qemu_set_irq(lpc->gsi[gsi], pic_level);
230 }
231 
232 /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */
233 static int ich9_pirq_to_gsi(int pirq)
234 {
235     return pirq + ICH9_LPC_PIC_NUM_PINS;
236 }
237 
238 static int ich9_gsi_to_pirq(int gsi)
239 {
240     return gsi - ICH9_LPC_PIC_NUM_PINS;
241 }
242 
243 /* gsi: ioapic irq 16-23, otherwise assert */
244 static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi)
245 {
246     int level = 0;
247 
248     assert(gsi >= ICH9_LPC_PIC_NUM_PINS);
249 
250     level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), ich9_gsi_to_pirq(gsi));
251     if (gsi == lpc->sci_gsi) {
252         level |= lpc->sci_level;
253     }
254 
255     qemu_set_irq(lpc->gsi[gsi], level);
256 }
257 
258 void ich9_lpc_set_irq(void *opaque, int pirq, int level)
259 {
260     ICH9LPCState *lpc = opaque;
261     int pic_irq, pic_dis;
262 
263     assert(0 <= pirq);
264     assert(pirq < ICH9_LPC_NB_PIRQS);
265 
266     ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq));
267     ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis);
268     ich9_lpc_update_pic(lpc, pic_irq);
269 }
270 
271 /* return the pirq number (PIRQ[A-H]:0-7) corresponding to
272  * a given device irq pin.
273  */
274 int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx)
275 {
276     BusState *bus = qdev_get_parent_bus(&pci_dev->qdev);
277     PCIBus *pci_bus = PCI_BUS(bus);
278     PCIDevice *lpc_pdev =
279             pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)];
280     ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev);
281 
282     return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx];
283 }
284 
285 PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
286 {
287     ICH9LPCState *lpc = opaque;
288     PCIINTxRoute route;
289     int pic_irq;
290     int pic_dis;
291 
292     assert(0 <= pirq_pin);
293     assert(pirq_pin < ICH9_LPC_NB_PIRQS);
294 
295     route.mode = PCI_INTX_ENABLED;
296     ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis);
297     if (!pic_dis) {
298         if (pic_irq < ICH9_LPC_PIC_NUM_PINS) {
299             route.irq = pic_irq;
300         } else {
301             route.mode = PCI_INTX_DISABLED;
302             route.irq = -1;
303         }
304     } else {
305         route.irq = ich9_pirq_to_gsi(pirq_pin);
306     }
307 
308     return route;
309 }
310 
311 void ich9_generate_smi(void)
312 {
313     cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI);
314 }
315 
316 /* Returns -1 on error, IRQ number on success */
317 static int ich9_lpc_sci_irq(ICH9LPCState *lpc)
318 {
319     uint8_t sel = lpc->d.config[ICH9_LPC_ACPI_CTRL] &
320                   ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK;
321     switch (sel) {
322     case ICH9_LPC_ACPI_CTRL_9:
323         return 9;
324     case ICH9_LPC_ACPI_CTRL_10:
325         return 10;
326     case ICH9_LPC_ACPI_CTRL_11:
327         return 11;
328     case ICH9_LPC_ACPI_CTRL_20:
329         return 20;
330     case ICH9_LPC_ACPI_CTRL_21:
331         return 21;
332     default:
333         /* reserved */
334         qemu_log_mask(LOG_GUEST_ERROR,
335                       "ICH9 LPC: SCI IRQ SEL #%u is reserved\n", sel);
336         break;
337     }
338     return -1;
339 }
340 
341 static void ich9_set_sci(void *opaque, int irq_num, int level)
342 {
343     ICH9LPCState *lpc = opaque;
344     int irq;
345 
346     assert(irq_num == 0);
347     level = !!level;
348     if (level == lpc->sci_level) {
349         return;
350     }
351     lpc->sci_level = level;
352 
353     irq = lpc->sci_gsi;
354     if (irq < 0) {
355         return;
356     }
357 
358     if (irq >= ICH9_LPC_PIC_NUM_PINS) {
359         ich9_lpc_update_apic(lpc, irq);
360     } else {
361         ich9_lpc_update_pic(lpc, irq);
362     }
363 }
364 
365 static void smi_features_ok_callback(void *opaque)
366 {
367     ICH9LPCState *lpc = opaque;
368     uint64_t guest_features;
369 
370     if (lpc->smi_features_ok) {
371         /* negotiation already complete, features locked */
372         return;
373     }
374 
375     memcpy(&guest_features, lpc->smi_guest_features_le, sizeof guest_features);
376     le64_to_cpus(&guest_features);
377     if (guest_features & ~lpc->smi_host_features) {
378         /* guest requests invalid features, leave @features_ok at zero */
379         return;
380     }
381     if (!(guest_features & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT)) &&
382         guest_features & (BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT) |
383                           BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT))) {
384         /*
385          * cpu hot-[un]plug with SMI requires SMI broadcast,
386          * leave @features_ok at zero
387          */
388         return;
389     }
390 
391     /* valid feature subset requested, lock it down, report success */
392     lpc->smi_negotiated_features = guest_features;
393     lpc->smi_features_ok = 1;
394 }
395 
396 void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled)
397 {
398     ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci);
399     qemu_irq sci_irq;
400     FWCfgState *fw_cfg = fw_cfg_find();
401 
402     sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0);
403     ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq);
404 
405     if (lpc->smi_host_features && fw_cfg) {
406         uint64_t host_features_le;
407 
408         host_features_le = cpu_to_le64(lpc->smi_host_features);
409         memcpy(lpc->smi_host_features_le, &host_features_le,
410                sizeof host_features_le);
411         fw_cfg_add_file(fw_cfg, "etc/smi/supported-features",
412                         lpc->smi_host_features_le,
413                         sizeof lpc->smi_host_features_le);
414 
415         /* The other two guest-visible fields are cleared on device reset, we
416          * just link them into fw_cfg here.
417          */
418         fw_cfg_add_file_callback(fw_cfg, "etc/smi/requested-features",
419                                  NULL, NULL, NULL,
420                                  lpc->smi_guest_features_le,
421                                  sizeof lpc->smi_guest_features_le,
422                                  false);
423         fw_cfg_add_file_callback(fw_cfg, "etc/smi/features-ok",
424                                  smi_features_ok_callback, NULL, lpc,
425                                  &lpc->smi_features_ok,
426                                  sizeof lpc->smi_features_ok,
427                                  true);
428     }
429 
430     ich9_lpc_reset(DEVICE(lpc));
431 }
432 
433 /* APM */
434 
435 static void ich9_apm_ctrl_changed(uint32_t val, void *arg)
436 {
437     ICH9LPCState *lpc = arg;
438 
439     /* ACPI specs 3.0, 4.7.2.5 */
440     acpi_pm1_cnt_update(&lpc->pm.acpi_regs,
441                         val == ICH9_APM_ACPI_ENABLE,
442                         val == ICH9_APM_ACPI_DISABLE);
443     if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) {
444         return;
445     }
446 
447     /* SMI_EN = PMBASE + 30. SMI control and enable register */
448     if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) {
449         if (lpc->smi_negotiated_features &
450             (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) {
451             CPUState *cs;
452             CPU_FOREACH(cs) {
453                 cpu_interrupt(cs, CPU_INTERRUPT_SMI);
454             }
455         } else {
456             cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI);
457         }
458     }
459 }
460 
461 /* config:PMBASE */
462 static void
463 ich9_lpc_pmbase_sci_update(ICH9LPCState *lpc)
464 {
465     uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE);
466     uint8_t acpi_cntl = pci_get_long(lpc->d.config + ICH9_LPC_ACPI_CTRL);
467     int new_gsi;
468 
469     if (acpi_cntl & ICH9_LPC_ACPI_CTRL_ACPI_EN) {
470         pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK;
471     } else {
472         pm_io_base = 0;
473     }
474 
475     ich9_pm_iospace_update(&lpc->pm, pm_io_base);
476 
477     new_gsi = ich9_lpc_sci_irq(lpc);
478     if (new_gsi == -1) {
479         return;
480     }
481     if (lpc->sci_level && new_gsi != lpc->sci_gsi) {
482         qemu_set_irq(lpc->pm.irq, 0);
483         lpc->sci_gsi = new_gsi;
484         qemu_set_irq(lpc->pm.irq, 1);
485     }
486     lpc->sci_gsi = new_gsi;
487 }
488 
489 /* config:RCBA */
490 static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rcba_old)
491 {
492     uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA);
493 
494     if (rcba_old & ICH9_LPC_RCBA_EN) {
495         memory_region_del_subregion(get_system_memory(), &lpc->rcrb_mem);
496     }
497     if (rcba & ICH9_LPC_RCBA_EN) {
498         memory_region_add_subregion_overlap(get_system_memory(),
499                                             rcba & ICH9_LPC_RCBA_BA_MASK,
500                                             &lpc->rcrb_mem, 1);
501     }
502 }
503 
504 /* config:GEN_PMCON* */
505 static void
506 ich9_lpc_pmcon_update(ICH9LPCState *lpc)
507 {
508     uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1);
509     uint16_t wmask;
510 
511     if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) {
512         wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1);
513         wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK;
514         pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask);
515         lpc->pm.smi_en_wmask &= ~1;
516     }
517 }
518 
519 static int ich9_lpc_post_load(void *opaque, int version_id)
520 {
521     ICH9LPCState *lpc = opaque;
522 
523     ich9_lpc_pmbase_sci_update(lpc);
524     ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RCBA_EN */);
525     ich9_lpc_pmcon_update(lpc);
526     return 0;
527 }
528 
529 static void ich9_lpc_config_write(PCIDevice *d,
530                                   uint32_t addr, uint32_t val, int len)
531 {
532     ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
533     uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA);
534 
535     pci_default_write_config(d, addr, val, len);
536     if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4) ||
537         ranges_overlap(addr, len, ICH9_LPC_ACPI_CTRL, 1)) {
538         ich9_lpc_pmbase_sci_update(lpc);
539     }
540     if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) {
541         ich9_lpc_rcba_update(lpc, rcba_old);
542     }
543     if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) {
544         pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
545     }
546     if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) {
547         pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d));
548     }
549     if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) {
550         ich9_lpc_pmcon_update(lpc);
551     }
552 }
553 
554 static void ich9_lpc_reset(DeviceState *qdev)
555 {
556     PCIDevice *d = PCI_DEVICE(qdev);
557     ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
558     uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA);
559     int i;
560 
561     for (i = 0; i < 4; i++) {
562         pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i,
563                      ICH9_LPC_PIRQ_ROUT_DEFAULT);
564     }
565     for (i = 0; i < 4; i++) {
566         pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i,
567                      ICH9_LPC_PIRQ_ROUT_DEFAULT);
568     }
569     pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT);
570 
571     pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT);
572     pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT);
573 
574     ich9_cc_reset(lpc);
575 
576     ich9_lpc_pmbase_sci_update(lpc);
577     ich9_lpc_rcba_update(lpc, rcba_old);
578 
579     lpc->sci_level = 0;
580     lpc->rst_cnt = 0;
581 
582     memset(lpc->smi_guest_features_le, 0, sizeof lpc->smi_guest_features_le);
583     lpc->smi_features_ok = 0;
584     lpc->smi_negotiated_features = 0;
585 }
586 
587 /* root complex register block is mapped into memory space */
588 static const MemoryRegionOps rcrb_mmio_ops = {
589     .read = ich9_cc_read,
590     .write = ich9_cc_write,
591     .endianness = DEVICE_LITTLE_ENDIAN,
592 };
593 
594 static void ich9_lpc_machine_ready(Notifier *n, void *opaque)
595 {
596     ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready);
597     MemoryRegion *io_as = pci_address_space_io(&s->d);
598     uint8_t *pci_conf;
599 
600     pci_conf = s->d.config;
601     if (memory_region_present(io_as, 0x3f8)) {
602         /* com1 */
603         pci_conf[0x82] |= 0x01;
604     }
605     if (memory_region_present(io_as, 0x2f8)) {
606         /* com2 */
607         pci_conf[0x82] |= 0x02;
608     }
609     if (memory_region_present(io_as, 0x378)) {
610         /* lpt */
611         pci_conf[0x82] |= 0x04;
612     }
613     if (memory_region_present(io_as, 0x3f2)) {
614         /* floppy */
615         pci_conf[0x82] |= 0x08;
616     }
617 }
618 
619 /* reset control */
620 static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val,
621                                unsigned len)
622 {
623     ICH9LPCState *lpc = opaque;
624 
625     if (val & 4) {
626         qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
627         return;
628     }
629     lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */
630 }
631 
632 static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len)
633 {
634     ICH9LPCState *lpc = opaque;
635 
636     return lpc->rst_cnt;
637 }
638 
639 static const MemoryRegionOps ich9_rst_cnt_ops = {
640     .read = ich9_rst_cnt_read,
641     .write = ich9_rst_cnt_write,
642     .endianness = DEVICE_LITTLE_ENDIAN
643 };
644 
645 static void ich9_lpc_initfn(Object *obj)
646 {
647     ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj);
648 
649     static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE;
650     static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE;
651 
652     object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT,
653                                   &lpc->sci_gsi, OBJ_PROP_FLAG_READ);
654     object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD,
655                                   &acpi_enable_cmd, OBJ_PROP_FLAG_READ);
656     object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD,
657                                   &acpi_disable_cmd, OBJ_PROP_FLAG_READ);
658     object_property_add_uint64_ptr(obj, ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP,
659                                    &lpc->smi_negotiated_features,
660                                    OBJ_PROP_FLAG_READ);
661 
662     ich9_pm_add_properties(obj, &lpc->pm);
663 }
664 
665 static void ich9_lpc_realize(PCIDevice *d, Error **errp)
666 {
667     ICH9LPCState *lpc = ICH9_LPC_DEVICE(d);
668     DeviceState *dev = DEVICE(d);
669     ISABus *isa_bus;
670 
671     isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(),
672                           errp);
673     if (!isa_bus) {
674         return;
675     }
676 
677     pci_set_long(d->wmask + ICH9_LPC_PMBASE,
678                  ICH9_LPC_PMBASE_BASE_ADDRESS_MASK);
679     pci_set_byte(d->wmask + ICH9_LPC_PMBASE,
680                  ICH9_LPC_ACPI_CTRL_ACPI_EN |
681                  ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK);
682 
683     memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc,
684                           "lpc-rcrb-mmio", ICH9_CC_SIZE);
685 
686     lpc->isa_bus = isa_bus;
687 
688     ich9_cc_init(lpc);
689     apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc);
690 
691     lpc->machine_ready.notify = ich9_lpc_machine_ready;
692     qemu_add_machine_init_done_notifier(&lpc->machine_ready);
693 
694     memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc,
695                           "lpc-reset-control", 1);
696     memory_region_add_subregion_overlap(pci_address_space_io(d),
697                                         ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem,
698                                         1);
699 
700     qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS);
701 
702     isa_bus_irqs(isa_bus, lpc->gsi);
703 }
704 
705 static bool ich9_rst_cnt_needed(void *opaque)
706 {
707     ICH9LPCState *lpc = opaque;
708 
709     return (lpc->rst_cnt != 0);
710 }
711 
712 static const VMStateDescription vmstate_ich9_rst_cnt = {
713     .name = "ICH9LPC/rst_cnt",
714     .version_id = 1,
715     .minimum_version_id = 1,
716     .needed = ich9_rst_cnt_needed,
717     .fields = (VMStateField[]) {
718         VMSTATE_UINT8(rst_cnt, ICH9LPCState),
719         VMSTATE_END_OF_LIST()
720     }
721 };
722 
723 static bool ich9_smi_feat_needed(void *opaque)
724 {
725     ICH9LPCState *lpc = opaque;
726 
727     return !buffer_is_zero(lpc->smi_guest_features_le,
728                            sizeof lpc->smi_guest_features_le) ||
729            lpc->smi_features_ok;
730 }
731 
732 static const VMStateDescription vmstate_ich9_smi_feat = {
733     .name = "ICH9LPC/smi_feat",
734     .version_id = 1,
735     .minimum_version_id = 1,
736     .needed = ich9_smi_feat_needed,
737     .fields = (VMStateField[]) {
738         VMSTATE_UINT8_ARRAY(smi_guest_features_le, ICH9LPCState,
739                             sizeof(uint64_t)),
740         VMSTATE_UINT8(smi_features_ok, ICH9LPCState),
741         VMSTATE_UINT64(smi_negotiated_features, ICH9LPCState),
742         VMSTATE_END_OF_LIST()
743     }
744 };
745 
746 static const VMStateDescription vmstate_ich9_lpc = {
747     .name = "ICH9LPC",
748     .version_id = 1,
749     .minimum_version_id = 1,
750     .post_load = ich9_lpc_post_load,
751     .fields = (VMStateField[]) {
752         VMSTATE_PCI_DEVICE(d, ICH9LPCState),
753         VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState),
754         VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs),
755         VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE),
756         VMSTATE_UINT32(sci_level, ICH9LPCState),
757         VMSTATE_END_OF_LIST()
758     },
759     .subsections = (const VMStateDescription*[]) {
760         &vmstate_ich9_rst_cnt,
761         &vmstate_ich9_smi_feat,
762         NULL
763     }
764 };
765 
766 static Property ich9_lpc_properties[] = {
767     DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, true),
768     DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features,
769                       ICH9_LPC_SMI_F_BROADCAST_BIT, true),
770     DEFINE_PROP_BIT64("x-smi-cpu-hotplug", ICH9LPCState, smi_host_features,
771                       ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT, true),
772     DEFINE_PROP_BIT64("x-smi-cpu-hotunplug", ICH9LPCState, smi_host_features,
773                       ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT, false),
774     DEFINE_PROP_END_OF_LIST(),
775 };
776 
777 static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev)
778 {
779     ICH9LPCState *s = ICH9_LPC_DEVICE(adev);
780 
781     acpi_send_gpe_event(&s->pm.acpi_regs, s->pm.irq, ev);
782 }
783 
784 static void ich9_lpc_class_init(ObjectClass *klass, void *data)
785 {
786     DeviceClass *dc = DEVICE_CLASS(klass);
787     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
788     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
789     AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass);
790 
791     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
792     dc->reset = ich9_lpc_reset;
793     k->realize = ich9_lpc_realize;
794     dc->vmsd = &vmstate_ich9_lpc;
795     device_class_set_props(dc, ich9_lpc_properties);
796     k->config_write = ich9_lpc_config_write;
797     dc->desc = "ICH9 LPC bridge";
798     k->vendor_id = PCI_VENDOR_ID_INTEL;
799     k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8;
800     k->revision = ICH9_A2_LPC_REVISION;
801     k->class_id = PCI_CLASS_BRIDGE_ISA;
802     /*
803      * Reason: part of ICH9 southbridge, needs to be wired up by
804      * pc_q35_init()
805      */
806     dc->user_creatable = false;
807     hc->pre_plug = ich9_pm_device_pre_plug_cb;
808     hc->plug = ich9_pm_device_plug_cb;
809     hc->unplug_request = ich9_pm_device_unplug_request_cb;
810     hc->unplug = ich9_pm_device_unplug_cb;
811     adevc->ospm_status = ich9_pm_ospm_status;
812     adevc->send_event = ich9_send_gpe;
813     adevc->madt_cpu = pc_madt_cpu_entry;
814 }
815 
816 static const TypeInfo ich9_lpc_info = {
817     .name       = TYPE_ICH9_LPC_DEVICE,
818     .parent     = TYPE_PCI_DEVICE,
819     .instance_size = sizeof(ICH9LPCState),
820     .instance_init = ich9_lpc_initfn,
821     .class_init  = ich9_lpc_class_init,
822     .interfaces = (InterfaceInfo[]) {
823         { TYPE_HOTPLUG_HANDLER },
824         { TYPE_ACPI_DEVICE_IF },
825         { INTERFACE_CONVENTIONAL_PCI_DEVICE },
826         { }
827     }
828 };
829 
830 static void ich9_lpc_register(void)
831 {
832     type_register_static(&ich9_lpc_info);
833 }
834 
835 type_init(ich9_lpc_register);
836