1 /* 2 * QEMU ICH9 Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "cpu.h" 33 #include "qapi/visitor.h" 34 #include "qemu/range.h" 35 #include "hw/isa/isa.h" 36 #include "hw/sysbus.h" 37 #include "migration/vmstate.h" 38 #include "hw/irq.h" 39 #include "hw/isa/apm.h" 40 #include "hw/pci/pci.h" 41 #include "hw/pci/pci_bridge.h" 42 #include "hw/i386/ich9.h" 43 #include "hw/acpi/acpi.h" 44 #include "hw/acpi/ich9.h" 45 #include "hw/pci/pci_bus.h" 46 #include "hw/qdev-properties.h" 47 #include "exec/address-spaces.h" 48 #include "sysemu/runstate.h" 49 #include "sysemu/sysemu.h" 50 #include "hw/core/cpu.h" 51 #include "hw/nvram/fw_cfg.h" 52 #include "qemu/cutils.h" 53 54 /*****************************************************************************/ 55 /* ICH9 LPC PCI to ISA bridge */ 56 57 static void ich9_lpc_reset(DeviceState *qdev); 58 59 /* chipset configuration register 60 * to access chipset configuration registers, pci_[sg]et_{byte, word, long} 61 * are used. 62 * Although it's not pci configuration space, it's little endian as Intel. 63 */ 64 65 static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir) 66 { 67 int intx; 68 for (intx = 0; intx < PCI_NUM_PINS; intx++) { 69 irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK; 70 } 71 } 72 73 static void ich9_cc_update(ICH9LPCState *lpc) 74 { 75 int slot; 76 int pci_intx; 77 78 const int reg_offsets[] = { 79 ICH9_CC_D25IR, 80 ICH9_CC_D26IR, 81 ICH9_CC_D27IR, 82 ICH9_CC_D28IR, 83 ICH9_CC_D29IR, 84 ICH9_CC_D30IR, 85 ICH9_CC_D31IR, 86 }; 87 const int *offset; 88 89 /* D{25 - 31}IR, but D30IR is read only to 0. */ 90 for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) { 91 if (slot == 30) { 92 continue; 93 } 94 ich9_cc_update_ir(lpc->irr[slot], 95 pci_get_word(lpc->chip_config + *offset)); 96 } 97 98 /* 99 * D30: DMI2PCI bridge 100 * It is arbitrarily decided how INTx lines of PCI devices behind 101 * the bridge are connected to pirq lines. Our choice is PIRQ[E-H]. 102 * INT[A-D] are connected to PIRQ[E-H] 103 */ 104 for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) { 105 lpc->irr[30][pci_intx] = pci_intx + 4; 106 } 107 } 108 109 static void ich9_cc_init(ICH9LPCState *lpc) 110 { 111 int slot; 112 int intx; 113 114 /* the default irq routing is arbitrary as long as it matches with 115 * acpi irq routing table. 116 * The one that is incompatible with piix_pci(= bochs) one is 117 * intentionally chosen to let the users know that the different 118 * board is used. 119 * 120 * int[A-D] -> pirq[E-F] 121 * avoid pirq A-D because they are used for pci express port 122 */ 123 for (slot = 0; slot < PCI_SLOT_MAX; slot++) { 124 for (intx = 0; intx < PCI_NUM_PINS; intx++) { 125 lpc->irr[slot][intx] = (slot + intx) % 4 + 4; 126 } 127 } 128 ich9_cc_update(lpc); 129 } 130 131 static void ich9_cc_reset(ICH9LPCState *lpc) 132 { 133 uint8_t *c = lpc->chip_config; 134 135 memset(lpc->chip_config, 0, sizeof(lpc->chip_config)); 136 137 pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT); 138 pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT); 139 pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT); 140 pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT); 141 pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT); 142 pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT); 143 pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT); 144 pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT); 145 146 ich9_cc_update(lpc); 147 } 148 149 static void ich9_cc_addr_len(uint64_t *addr, unsigned *len) 150 { 151 *addr &= ICH9_CC_ADDR_MASK; 152 if (*addr + *len >= ICH9_CC_SIZE) { 153 *len = ICH9_CC_SIZE - *addr; 154 } 155 } 156 157 /* val: little endian */ 158 static void ich9_cc_write(void *opaque, hwaddr addr, 159 uint64_t val, unsigned len) 160 { 161 ICH9LPCState *lpc = (ICH9LPCState *)opaque; 162 163 ich9_cc_addr_len(&addr, &len); 164 memcpy(lpc->chip_config + addr, &val, len); 165 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 166 ich9_cc_update(lpc); 167 } 168 169 /* return value: little endian */ 170 static uint64_t ich9_cc_read(void *opaque, hwaddr addr, 171 unsigned len) 172 { 173 ICH9LPCState *lpc = (ICH9LPCState *)opaque; 174 175 uint32_t val = 0; 176 ich9_cc_addr_len(&addr, &len); 177 memcpy(&val, lpc->chip_config + addr, len); 178 return val; 179 } 180 181 /* IRQ routing */ 182 /* */ 183 static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis) 184 { 185 *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK; 186 *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN; 187 } 188 189 static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num, 190 int *pic_irq, int *pic_dis) 191 { 192 switch (pirq_num) { 193 case 0 ... 3: /* A-D */ 194 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num], 195 pic_irq, pic_dis); 196 return; 197 case 4 ... 7: /* E-H */ 198 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)], 199 pic_irq, pic_dis); 200 return; 201 default: 202 break; 203 } 204 abort(); 205 } 206 207 /* gsi: i8259+ioapic irq 0-15, otherwise assert */ 208 static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi) 209 { 210 int i, pic_level; 211 212 assert(gsi < ICH9_LPC_PIC_NUM_PINS); 213 214 /* The pic level is the logical OR of all the PCI irqs mapped to it */ 215 pic_level = 0; 216 for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) { 217 int tmp_irq; 218 int tmp_dis; 219 ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis); 220 if (!tmp_dis && tmp_irq == gsi) { 221 pic_level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), i); 222 } 223 } 224 if (gsi == lpc->sci_gsi) { 225 pic_level |= lpc->sci_level; 226 } 227 228 qemu_set_irq(lpc->gsi[gsi], pic_level); 229 } 230 231 /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */ 232 static int ich9_pirq_to_gsi(int pirq) 233 { 234 return pirq + ICH9_LPC_PIC_NUM_PINS; 235 } 236 237 static int ich9_gsi_to_pirq(int gsi) 238 { 239 return gsi - ICH9_LPC_PIC_NUM_PINS; 240 } 241 242 /* gsi: ioapic irq 16-23, otherwise assert */ 243 static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi) 244 { 245 int level = 0; 246 247 assert(gsi >= ICH9_LPC_PIC_NUM_PINS); 248 249 level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), ich9_gsi_to_pirq(gsi)); 250 if (gsi == lpc->sci_gsi) { 251 level |= lpc->sci_level; 252 } 253 254 qemu_set_irq(lpc->gsi[gsi], level); 255 } 256 257 void ich9_lpc_set_irq(void *opaque, int pirq, int level) 258 { 259 ICH9LPCState *lpc = opaque; 260 int pic_irq, pic_dis; 261 262 assert(0 <= pirq); 263 assert(pirq < ICH9_LPC_NB_PIRQS); 264 265 ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq)); 266 ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis); 267 ich9_lpc_update_pic(lpc, pic_irq); 268 } 269 270 /* return the pirq number (PIRQ[A-H]:0-7) corresponding to 271 * a given device irq pin. 272 */ 273 int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) 274 { 275 BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); 276 PCIBus *pci_bus = PCI_BUS(bus); 277 PCIDevice *lpc_pdev = 278 pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)]; 279 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev); 280 281 return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; 282 } 283 284 PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin) 285 { 286 ICH9LPCState *lpc = opaque; 287 PCIINTxRoute route; 288 int pic_irq; 289 int pic_dis; 290 291 assert(0 <= pirq_pin); 292 assert(pirq_pin < ICH9_LPC_NB_PIRQS); 293 294 route.mode = PCI_INTX_ENABLED; 295 ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis); 296 if (!pic_dis) { 297 if (pic_irq < ICH9_LPC_PIC_NUM_PINS) { 298 route.irq = pic_irq; 299 } else { 300 route.mode = PCI_INTX_DISABLED; 301 route.irq = -1; 302 } 303 } else { 304 route.irq = ich9_pirq_to_gsi(pirq_pin); 305 } 306 307 return route; 308 } 309 310 void ich9_generate_smi(void) 311 { 312 cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); 313 } 314 315 static int ich9_lpc_sci_irq(ICH9LPCState *lpc) 316 { 317 switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] & 318 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK) { 319 case ICH9_LPC_ACPI_CTRL_9: 320 return 9; 321 case ICH9_LPC_ACPI_CTRL_10: 322 return 10; 323 case ICH9_LPC_ACPI_CTRL_11: 324 return 11; 325 case ICH9_LPC_ACPI_CTRL_20: 326 return 20; 327 case ICH9_LPC_ACPI_CTRL_21: 328 return 21; 329 default: 330 /* reserved */ 331 break; 332 } 333 return -1; 334 } 335 336 static void ich9_set_sci(void *opaque, int irq_num, int level) 337 { 338 ICH9LPCState *lpc = opaque; 339 int irq; 340 341 assert(irq_num == 0); 342 level = !!level; 343 if (level == lpc->sci_level) { 344 return; 345 } 346 lpc->sci_level = level; 347 348 irq = lpc->sci_gsi; 349 if (irq < 0) { 350 return; 351 } 352 353 if (irq >= ICH9_LPC_PIC_NUM_PINS) { 354 ich9_lpc_update_apic(lpc, irq); 355 } else { 356 ich9_lpc_update_pic(lpc, irq); 357 } 358 } 359 360 static void smi_features_ok_callback(void *opaque) 361 { 362 ICH9LPCState *lpc = opaque; 363 uint64_t guest_features; 364 365 if (lpc->smi_features_ok) { 366 /* negotiation already complete, features locked */ 367 return; 368 } 369 370 memcpy(&guest_features, lpc->smi_guest_features_le, sizeof guest_features); 371 le64_to_cpus(&guest_features); 372 if (guest_features & ~lpc->smi_host_features) { 373 /* guest requests invalid features, leave @features_ok at zero */ 374 return; 375 } 376 if (!(guest_features & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT)) && 377 guest_features & (BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT) | 378 BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT))) { 379 /* 380 * cpu hot-[un]plug with SMI requires SMI broadcast, 381 * leave @features_ok at zero 382 */ 383 return; 384 } 385 386 /* valid feature subset requested, lock it down, report success */ 387 lpc->smi_negotiated_features = guest_features; 388 lpc->smi_features_ok = 1; 389 } 390 391 void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled) 392 { 393 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci); 394 qemu_irq sci_irq; 395 FWCfgState *fw_cfg = fw_cfg_find(); 396 397 sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0); 398 ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq); 399 400 if (lpc->smi_host_features && fw_cfg) { 401 uint64_t host_features_le; 402 403 host_features_le = cpu_to_le64(lpc->smi_host_features); 404 memcpy(lpc->smi_host_features_le, &host_features_le, 405 sizeof host_features_le); 406 fw_cfg_add_file(fw_cfg, "etc/smi/supported-features", 407 lpc->smi_host_features_le, 408 sizeof lpc->smi_host_features_le); 409 410 /* The other two guest-visible fields are cleared on device reset, we 411 * just link them into fw_cfg here. 412 */ 413 fw_cfg_add_file_callback(fw_cfg, "etc/smi/requested-features", 414 NULL, NULL, NULL, 415 lpc->smi_guest_features_le, 416 sizeof lpc->smi_guest_features_le, 417 false); 418 fw_cfg_add_file_callback(fw_cfg, "etc/smi/features-ok", 419 smi_features_ok_callback, NULL, lpc, 420 &lpc->smi_features_ok, 421 sizeof lpc->smi_features_ok, 422 true); 423 } 424 425 ich9_lpc_reset(DEVICE(lpc)); 426 } 427 428 /* APM */ 429 430 static void ich9_apm_ctrl_changed(uint32_t val, void *arg) 431 { 432 ICH9LPCState *lpc = arg; 433 434 /* ACPI specs 3.0, 4.7.2.5 */ 435 acpi_pm1_cnt_update(&lpc->pm.acpi_regs, 436 val == ICH9_APM_ACPI_ENABLE, 437 val == ICH9_APM_ACPI_DISABLE); 438 if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) { 439 return; 440 } 441 442 /* SMI_EN = PMBASE + 30. SMI control and enable register */ 443 if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { 444 if (lpc->smi_negotiated_features & 445 (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) { 446 CPUState *cs; 447 CPU_FOREACH(cs) { 448 cpu_interrupt(cs, CPU_INTERRUPT_SMI); 449 } 450 } else { 451 cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); 452 } 453 } 454 } 455 456 /* config:PMBASE */ 457 static void 458 ich9_lpc_pmbase_sci_update(ICH9LPCState *lpc) 459 { 460 uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE); 461 uint8_t acpi_cntl = pci_get_long(lpc->d.config + ICH9_LPC_ACPI_CTRL); 462 uint8_t new_gsi; 463 464 if (acpi_cntl & ICH9_LPC_ACPI_CTRL_ACPI_EN) { 465 pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK; 466 } else { 467 pm_io_base = 0; 468 } 469 470 ich9_pm_iospace_update(&lpc->pm, pm_io_base); 471 472 new_gsi = ich9_lpc_sci_irq(lpc); 473 if (lpc->sci_level && new_gsi != lpc->sci_gsi) { 474 qemu_set_irq(lpc->pm.irq, 0); 475 lpc->sci_gsi = new_gsi; 476 qemu_set_irq(lpc->pm.irq, 1); 477 } 478 lpc->sci_gsi = new_gsi; 479 } 480 481 /* config:RCBA */ 482 static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rcba_old) 483 { 484 uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA); 485 486 if (rcba_old & ICH9_LPC_RCBA_EN) { 487 memory_region_del_subregion(get_system_memory(), &lpc->rcrb_mem); 488 } 489 if (rcba & ICH9_LPC_RCBA_EN) { 490 memory_region_add_subregion_overlap(get_system_memory(), 491 rcba & ICH9_LPC_RCBA_BA_MASK, 492 &lpc->rcrb_mem, 1); 493 } 494 } 495 496 /* config:GEN_PMCON* */ 497 static void 498 ich9_lpc_pmcon_update(ICH9LPCState *lpc) 499 { 500 uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1); 501 uint16_t wmask; 502 503 if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) { 504 wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1); 505 wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK; 506 pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask); 507 lpc->pm.smi_en_wmask &= ~1; 508 } 509 } 510 511 static int ich9_lpc_post_load(void *opaque, int version_id) 512 { 513 ICH9LPCState *lpc = opaque; 514 515 ich9_lpc_pmbase_sci_update(lpc); 516 ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RCBA_EN */); 517 ich9_lpc_pmcon_update(lpc); 518 return 0; 519 } 520 521 static void ich9_lpc_config_write(PCIDevice *d, 522 uint32_t addr, uint32_t val, int len) 523 { 524 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 525 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); 526 527 pci_default_write_config(d, addr, val, len); 528 if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4) || 529 ranges_overlap(addr, len, ICH9_LPC_ACPI_CTRL, 1)) { 530 ich9_lpc_pmbase_sci_update(lpc); 531 } 532 if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) { 533 ich9_lpc_rcba_update(lpc, rcba_old); 534 } 535 if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) { 536 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 537 } 538 if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) { 539 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 540 } 541 if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) { 542 ich9_lpc_pmcon_update(lpc); 543 } 544 } 545 546 static void ich9_lpc_reset(DeviceState *qdev) 547 { 548 PCIDevice *d = PCI_DEVICE(qdev); 549 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 550 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); 551 int i; 552 553 for (i = 0; i < 4; i++) { 554 pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i, 555 ICH9_LPC_PIRQ_ROUT_DEFAULT); 556 } 557 for (i = 0; i < 4; i++) { 558 pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i, 559 ICH9_LPC_PIRQ_ROUT_DEFAULT); 560 } 561 pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT); 562 563 pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT); 564 pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT); 565 566 ich9_cc_reset(lpc); 567 568 ich9_lpc_pmbase_sci_update(lpc); 569 ich9_lpc_rcba_update(lpc, rcba_old); 570 571 lpc->sci_level = 0; 572 lpc->rst_cnt = 0; 573 574 memset(lpc->smi_guest_features_le, 0, sizeof lpc->smi_guest_features_le); 575 lpc->smi_features_ok = 0; 576 lpc->smi_negotiated_features = 0; 577 } 578 579 /* root complex register block is mapped into memory space */ 580 static const MemoryRegionOps rcrb_mmio_ops = { 581 .read = ich9_cc_read, 582 .write = ich9_cc_write, 583 .endianness = DEVICE_LITTLE_ENDIAN, 584 }; 585 586 static void ich9_lpc_machine_ready(Notifier *n, void *opaque) 587 { 588 ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready); 589 MemoryRegion *io_as = pci_address_space_io(&s->d); 590 uint8_t *pci_conf; 591 592 pci_conf = s->d.config; 593 if (memory_region_present(io_as, 0x3f8)) { 594 /* com1 */ 595 pci_conf[0x82] |= 0x01; 596 } 597 if (memory_region_present(io_as, 0x2f8)) { 598 /* com2 */ 599 pci_conf[0x82] |= 0x02; 600 } 601 if (memory_region_present(io_as, 0x378)) { 602 /* lpt */ 603 pci_conf[0x82] |= 0x04; 604 } 605 if (memory_region_present(io_as, 0x3f2)) { 606 /* floppy */ 607 pci_conf[0x82] |= 0x08; 608 } 609 } 610 611 /* reset control */ 612 static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val, 613 unsigned len) 614 { 615 ICH9LPCState *lpc = opaque; 616 617 if (val & 4) { 618 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 619 return; 620 } 621 lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */ 622 } 623 624 static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len) 625 { 626 ICH9LPCState *lpc = opaque; 627 628 return lpc->rst_cnt; 629 } 630 631 static const MemoryRegionOps ich9_rst_cnt_ops = { 632 .read = ich9_rst_cnt_read, 633 .write = ich9_rst_cnt_write, 634 .endianness = DEVICE_LITTLE_ENDIAN 635 }; 636 637 static void ich9_lpc_initfn(Object *obj) 638 { 639 ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj); 640 641 static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE; 642 static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE; 643 644 object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT, 645 &lpc->sci_gsi, OBJ_PROP_FLAG_READ); 646 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD, 647 &acpi_enable_cmd, OBJ_PROP_FLAG_READ); 648 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD, 649 &acpi_disable_cmd, OBJ_PROP_FLAG_READ); 650 object_property_add_uint64_ptr(obj, ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, 651 &lpc->smi_negotiated_features, 652 OBJ_PROP_FLAG_READ); 653 654 ich9_pm_add_properties(obj, &lpc->pm); 655 } 656 657 static void ich9_lpc_realize(PCIDevice *d, Error **errp) 658 { 659 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 660 DeviceState *dev = DEVICE(d); 661 ISABus *isa_bus; 662 663 isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(), 664 errp); 665 if (!isa_bus) { 666 return; 667 } 668 669 pci_set_long(d->wmask + ICH9_LPC_PMBASE, 670 ICH9_LPC_PMBASE_BASE_ADDRESS_MASK); 671 pci_set_byte(d->wmask + ICH9_LPC_PMBASE, 672 ICH9_LPC_ACPI_CTRL_ACPI_EN | 673 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK); 674 675 memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc, 676 "lpc-rcrb-mmio", ICH9_CC_SIZE); 677 678 lpc->isa_bus = isa_bus; 679 680 ich9_cc_init(lpc); 681 apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc); 682 683 lpc->machine_ready.notify = ich9_lpc_machine_ready; 684 qemu_add_machine_init_done_notifier(&lpc->machine_ready); 685 686 memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc, 687 "lpc-reset-control", 1); 688 memory_region_add_subregion_overlap(pci_address_space_io(d), 689 ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem, 690 1); 691 692 qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS); 693 694 isa_bus_irqs(isa_bus, lpc->gsi); 695 } 696 697 static bool ich9_rst_cnt_needed(void *opaque) 698 { 699 ICH9LPCState *lpc = opaque; 700 701 return (lpc->rst_cnt != 0); 702 } 703 704 static const VMStateDescription vmstate_ich9_rst_cnt = { 705 .name = "ICH9LPC/rst_cnt", 706 .version_id = 1, 707 .minimum_version_id = 1, 708 .needed = ich9_rst_cnt_needed, 709 .fields = (VMStateField[]) { 710 VMSTATE_UINT8(rst_cnt, ICH9LPCState), 711 VMSTATE_END_OF_LIST() 712 } 713 }; 714 715 static bool ich9_smi_feat_needed(void *opaque) 716 { 717 ICH9LPCState *lpc = opaque; 718 719 return !buffer_is_zero(lpc->smi_guest_features_le, 720 sizeof lpc->smi_guest_features_le) || 721 lpc->smi_features_ok; 722 } 723 724 static const VMStateDescription vmstate_ich9_smi_feat = { 725 .name = "ICH9LPC/smi_feat", 726 .version_id = 1, 727 .minimum_version_id = 1, 728 .needed = ich9_smi_feat_needed, 729 .fields = (VMStateField[]) { 730 VMSTATE_UINT8_ARRAY(smi_guest_features_le, ICH9LPCState, 731 sizeof(uint64_t)), 732 VMSTATE_UINT8(smi_features_ok, ICH9LPCState), 733 VMSTATE_UINT64(smi_negotiated_features, ICH9LPCState), 734 VMSTATE_END_OF_LIST() 735 } 736 }; 737 738 static const VMStateDescription vmstate_ich9_lpc = { 739 .name = "ICH9LPC", 740 .version_id = 1, 741 .minimum_version_id = 1, 742 .post_load = ich9_lpc_post_load, 743 .fields = (VMStateField[]) { 744 VMSTATE_PCI_DEVICE(d, ICH9LPCState), 745 VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState), 746 VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs), 747 VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE), 748 VMSTATE_UINT32(sci_level, ICH9LPCState), 749 VMSTATE_END_OF_LIST() 750 }, 751 .subsections = (const VMStateDescription*[]) { 752 &vmstate_ich9_rst_cnt, 753 &vmstate_ich9_smi_feat, 754 NULL 755 } 756 }; 757 758 static Property ich9_lpc_properties[] = { 759 DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, true), 760 DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features, 761 ICH9_LPC_SMI_F_BROADCAST_BIT, true), 762 DEFINE_PROP_BIT64("x-smi-cpu-hotplug", ICH9LPCState, smi_host_features, 763 ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT, true), 764 DEFINE_PROP_BIT64("x-smi-cpu-hotunplug", ICH9LPCState, smi_host_features, 765 ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT, false), 766 DEFINE_PROP_END_OF_LIST(), 767 }; 768 769 static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) 770 { 771 ICH9LPCState *s = ICH9_LPC_DEVICE(adev); 772 773 acpi_send_gpe_event(&s->pm.acpi_regs, s->pm.irq, ev); 774 } 775 776 static void ich9_lpc_class_init(ObjectClass *klass, void *data) 777 { 778 DeviceClass *dc = DEVICE_CLASS(klass); 779 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 780 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 781 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 782 783 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 784 dc->reset = ich9_lpc_reset; 785 k->realize = ich9_lpc_realize; 786 dc->vmsd = &vmstate_ich9_lpc; 787 device_class_set_props(dc, ich9_lpc_properties); 788 k->config_write = ich9_lpc_config_write; 789 dc->desc = "ICH9 LPC bridge"; 790 k->vendor_id = PCI_VENDOR_ID_INTEL; 791 k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8; 792 k->revision = ICH9_A2_LPC_REVISION; 793 k->class_id = PCI_CLASS_BRIDGE_ISA; 794 /* 795 * Reason: part of ICH9 southbridge, needs to be wired up by 796 * pc_q35_init() 797 */ 798 dc->user_creatable = false; 799 hc->pre_plug = ich9_pm_device_pre_plug_cb; 800 hc->plug = ich9_pm_device_plug_cb; 801 hc->unplug_request = ich9_pm_device_unplug_request_cb; 802 hc->unplug = ich9_pm_device_unplug_cb; 803 adevc->ospm_status = ich9_pm_ospm_status; 804 adevc->send_event = ich9_send_gpe; 805 adevc->madt_cpu = pc_madt_cpu_entry; 806 } 807 808 static const TypeInfo ich9_lpc_info = { 809 .name = TYPE_ICH9_LPC_DEVICE, 810 .parent = TYPE_PCI_DEVICE, 811 .instance_size = sizeof(ICH9LPCState), 812 .instance_init = ich9_lpc_initfn, 813 .class_init = ich9_lpc_class_init, 814 .interfaces = (InterfaceInfo[]) { 815 { TYPE_HOTPLUG_HANDLER }, 816 { TYPE_ACPI_DEVICE_IF }, 817 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 818 { } 819 } 820 }; 821 822 static void ich9_lpc_register(void) 823 { 824 type_register_static(&ich9_lpc_info); 825 } 826 827 type_init(ich9_lpc_register); 828