1 /* 2 * QEMU ICH9 Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "qemu/osdep.h" 31 #include "cpu.h" 32 #include "hw/hw.h" 33 #include "qapi/visitor.h" 34 #include "qemu/range.h" 35 #include "hw/isa/isa.h" 36 #include "hw/sysbus.h" 37 #include "hw/i386/pc.h" 38 #include "hw/isa/apm.h" 39 #include "hw/i386/ioapic.h" 40 #include "hw/pci/pci.h" 41 #include "hw/pci/pci_bridge.h" 42 #include "hw/i386/ich9.h" 43 #include "hw/acpi/acpi.h" 44 #include "hw/acpi/ich9.h" 45 #include "hw/pci/pci_bus.h" 46 #include "exec/address-spaces.h" 47 #include "sysemu/sysemu.h" 48 #include "qom/cpu.h" 49 #include "hw/nvram/fw_cfg.h" 50 #include "qemu/cutils.h" 51 52 /*****************************************************************************/ 53 /* ICH9 LPC PCI to ISA bridge */ 54 55 static void ich9_lpc_reset(DeviceState *qdev); 56 57 /* chipset configuration register 58 * to access chipset configuration registers, pci_[sg]et_{byte, word, long} 59 * are used. 60 * Although it's not pci configuration space, it's little endian as Intel. 61 */ 62 63 static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir) 64 { 65 int intx; 66 for (intx = 0; intx < PCI_NUM_PINS; intx++) { 67 irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK; 68 } 69 } 70 71 static void ich9_cc_update(ICH9LPCState *lpc) 72 { 73 int slot; 74 int pci_intx; 75 76 const int reg_offsets[] = { 77 ICH9_CC_D25IR, 78 ICH9_CC_D26IR, 79 ICH9_CC_D27IR, 80 ICH9_CC_D28IR, 81 ICH9_CC_D29IR, 82 ICH9_CC_D30IR, 83 ICH9_CC_D31IR, 84 }; 85 const int *offset; 86 87 /* D{25 - 31}IR, but D30IR is read only to 0. */ 88 for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) { 89 if (slot == 30) { 90 continue; 91 } 92 ich9_cc_update_ir(lpc->irr[slot], 93 pci_get_word(lpc->chip_config + *offset)); 94 } 95 96 /* 97 * D30: DMI2PCI bridge 98 * It is arbitrarily decided how INTx lines of PCI devices behind 99 * the bridge are connected to pirq lines. Our choice is PIRQ[E-H]. 100 * INT[A-D] are connected to PIRQ[E-H] 101 */ 102 for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) { 103 lpc->irr[30][pci_intx] = pci_intx + 4; 104 } 105 } 106 107 static void ich9_cc_init(ICH9LPCState *lpc) 108 { 109 int slot; 110 int intx; 111 112 /* the default irq routing is arbitrary as long as it matches with 113 * acpi irq routing table. 114 * The one that is incompatible with piix_pci(= bochs) one is 115 * intentionally chosen to let the users know that the different 116 * board is used. 117 * 118 * int[A-D] -> pirq[E-F] 119 * avoid pirq A-D because they are used for pci express port 120 */ 121 for (slot = 0; slot < PCI_SLOT_MAX; slot++) { 122 for (intx = 0; intx < PCI_NUM_PINS; intx++) { 123 lpc->irr[slot][intx] = (slot + intx) % 4 + 4; 124 } 125 } 126 ich9_cc_update(lpc); 127 } 128 129 static void ich9_cc_reset(ICH9LPCState *lpc) 130 { 131 uint8_t *c = lpc->chip_config; 132 133 memset(lpc->chip_config, 0, sizeof(lpc->chip_config)); 134 135 pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT); 136 pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT); 137 pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT); 138 pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT); 139 pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT); 140 pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT); 141 pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT); 142 pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT); 143 144 ich9_cc_update(lpc); 145 } 146 147 static void ich9_cc_addr_len(uint64_t *addr, unsigned *len) 148 { 149 *addr &= ICH9_CC_ADDR_MASK; 150 if (*addr + *len >= ICH9_CC_SIZE) { 151 *len = ICH9_CC_SIZE - *addr; 152 } 153 } 154 155 /* val: little endian */ 156 static void ich9_cc_write(void *opaque, hwaddr addr, 157 uint64_t val, unsigned len) 158 { 159 ICH9LPCState *lpc = (ICH9LPCState *)opaque; 160 161 ich9_cc_addr_len(&addr, &len); 162 memcpy(lpc->chip_config + addr, &val, len); 163 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 164 ich9_cc_update(lpc); 165 } 166 167 /* return value: little endian */ 168 static uint64_t ich9_cc_read(void *opaque, hwaddr addr, 169 unsigned len) 170 { 171 ICH9LPCState *lpc = (ICH9LPCState *)opaque; 172 173 uint32_t val = 0; 174 ich9_cc_addr_len(&addr, &len); 175 memcpy(&val, lpc->chip_config + addr, len); 176 return val; 177 } 178 179 /* IRQ routing */ 180 /* */ 181 static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis) 182 { 183 *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK; 184 *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN; 185 } 186 187 static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num, 188 int *pic_irq, int *pic_dis) 189 { 190 switch (pirq_num) { 191 case 0 ... 3: /* A-D */ 192 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num], 193 pic_irq, pic_dis); 194 return; 195 case 4 ... 7: /* E-H */ 196 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)], 197 pic_irq, pic_dis); 198 return; 199 default: 200 break; 201 } 202 abort(); 203 } 204 205 /* gsi: i8259+ioapic irq 0-15, otherwise assert */ 206 static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi) 207 { 208 int i, pic_level; 209 210 assert(gsi < ICH9_LPC_PIC_NUM_PINS); 211 212 /* The pic level is the logical OR of all the PCI irqs mapped to it */ 213 pic_level = 0; 214 for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) { 215 int tmp_irq; 216 int tmp_dis; 217 ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis); 218 if (!tmp_dis && tmp_irq == gsi) { 219 pic_level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), i); 220 } 221 } 222 if (gsi == lpc->sci_gsi) { 223 pic_level |= lpc->sci_level; 224 } 225 226 qemu_set_irq(lpc->gsi[gsi], pic_level); 227 } 228 229 /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */ 230 static int ich9_pirq_to_gsi(int pirq) 231 { 232 return pirq + ICH9_LPC_PIC_NUM_PINS; 233 } 234 235 static int ich9_gsi_to_pirq(int gsi) 236 { 237 return gsi - ICH9_LPC_PIC_NUM_PINS; 238 } 239 240 /* gsi: ioapic irq 16-23, otherwise assert */ 241 static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi) 242 { 243 int level = 0; 244 245 assert(gsi >= ICH9_LPC_PIC_NUM_PINS); 246 247 level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), ich9_gsi_to_pirq(gsi)); 248 if (gsi == lpc->sci_gsi) { 249 level |= lpc->sci_level; 250 } 251 252 qemu_set_irq(lpc->gsi[gsi], level); 253 } 254 255 void ich9_lpc_set_irq(void *opaque, int pirq, int level) 256 { 257 ICH9LPCState *lpc = opaque; 258 int pic_irq, pic_dis; 259 260 assert(0 <= pirq); 261 assert(pirq < ICH9_LPC_NB_PIRQS); 262 263 ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq)); 264 ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis); 265 ich9_lpc_update_pic(lpc, pic_irq); 266 } 267 268 /* return the pirq number (PIRQ[A-H]:0-7) corresponding to 269 * a given device irq pin. 270 */ 271 int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) 272 { 273 BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); 274 PCIBus *pci_bus = PCI_BUS(bus); 275 PCIDevice *lpc_pdev = 276 pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)]; 277 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev); 278 279 return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; 280 } 281 282 PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin) 283 { 284 ICH9LPCState *lpc = opaque; 285 PCIINTxRoute route; 286 int pic_irq; 287 int pic_dis; 288 289 assert(0 <= pirq_pin); 290 assert(pirq_pin < ICH9_LPC_NB_PIRQS); 291 292 route.mode = PCI_INTX_ENABLED; 293 ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis); 294 if (!pic_dis) { 295 if (pic_irq < ICH9_LPC_PIC_NUM_PINS) { 296 route.irq = pic_irq; 297 } else { 298 route.mode = PCI_INTX_DISABLED; 299 route.irq = -1; 300 } 301 } else { 302 route.irq = ich9_pirq_to_gsi(pirq_pin); 303 } 304 305 return route; 306 } 307 308 void ich9_generate_smi(void) 309 { 310 cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); 311 } 312 313 static int ich9_lpc_sci_irq(ICH9LPCState *lpc) 314 { 315 switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] & 316 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK) { 317 case ICH9_LPC_ACPI_CTRL_9: 318 return 9; 319 case ICH9_LPC_ACPI_CTRL_10: 320 return 10; 321 case ICH9_LPC_ACPI_CTRL_11: 322 return 11; 323 case ICH9_LPC_ACPI_CTRL_20: 324 return 20; 325 case ICH9_LPC_ACPI_CTRL_21: 326 return 21; 327 default: 328 /* reserved */ 329 break; 330 } 331 return -1; 332 } 333 334 static void ich9_set_sci(void *opaque, int irq_num, int level) 335 { 336 ICH9LPCState *lpc = opaque; 337 int irq; 338 339 assert(irq_num == 0); 340 level = !!level; 341 if (level == lpc->sci_level) { 342 return; 343 } 344 lpc->sci_level = level; 345 346 irq = lpc->sci_gsi; 347 if (irq < 0) { 348 return; 349 } 350 351 if (irq >= ICH9_LPC_PIC_NUM_PINS) { 352 ich9_lpc_update_apic(lpc, irq); 353 } else { 354 ich9_lpc_update_pic(lpc, irq); 355 } 356 } 357 358 static void smi_features_ok_callback(void *opaque) 359 { 360 ICH9LPCState *lpc = opaque; 361 uint64_t guest_features; 362 363 if (lpc->smi_features_ok) { 364 /* negotiation already complete, features locked */ 365 return; 366 } 367 368 memcpy(&guest_features, lpc->smi_guest_features_le, sizeof guest_features); 369 le64_to_cpus(&guest_features); 370 if (guest_features & ~lpc->smi_host_features) { 371 /* guest requests invalid features, leave @features_ok at zero */ 372 return; 373 } 374 375 /* valid feature subset requested, lock it down, report success */ 376 lpc->smi_negotiated_features = guest_features; 377 lpc->smi_features_ok = 1; 378 } 379 380 void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled) 381 { 382 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci); 383 qemu_irq sci_irq; 384 FWCfgState *fw_cfg = fw_cfg_find(); 385 386 sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0); 387 ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq); 388 389 if (lpc->smi_host_features && fw_cfg) { 390 uint64_t host_features_le; 391 392 host_features_le = cpu_to_le64(lpc->smi_host_features); 393 memcpy(lpc->smi_host_features_le, &host_features_le, 394 sizeof host_features_le); 395 fw_cfg_add_file(fw_cfg, "etc/smi/supported-features", 396 lpc->smi_host_features_le, 397 sizeof lpc->smi_host_features_le); 398 399 /* The other two guest-visible fields are cleared on device reset, we 400 * just link them into fw_cfg here. 401 */ 402 fw_cfg_add_file_callback(fw_cfg, "etc/smi/requested-features", 403 NULL, NULL, NULL, 404 lpc->smi_guest_features_le, 405 sizeof lpc->smi_guest_features_le, 406 false); 407 fw_cfg_add_file_callback(fw_cfg, "etc/smi/features-ok", 408 smi_features_ok_callback, NULL, lpc, 409 &lpc->smi_features_ok, 410 sizeof lpc->smi_features_ok, 411 true); 412 } 413 414 ich9_lpc_reset(DEVICE(lpc)); 415 } 416 417 /* APM */ 418 419 static void ich9_apm_ctrl_changed(uint32_t val, void *arg) 420 { 421 ICH9LPCState *lpc = arg; 422 423 /* ACPI specs 3.0, 4.7.2.5 */ 424 acpi_pm1_cnt_update(&lpc->pm.acpi_regs, 425 val == ICH9_APM_ACPI_ENABLE, 426 val == ICH9_APM_ACPI_DISABLE); 427 if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) { 428 return; 429 } 430 431 /* SMI_EN = PMBASE + 30. SMI control and enable register */ 432 if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { 433 if (lpc->smi_negotiated_features & 434 (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) { 435 CPUState *cs; 436 CPU_FOREACH(cs) { 437 cpu_interrupt(cs, CPU_INTERRUPT_SMI); 438 } 439 } else { 440 cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); 441 } 442 } 443 } 444 445 /* config:PMBASE */ 446 static void 447 ich9_lpc_pmbase_sci_update(ICH9LPCState *lpc) 448 { 449 uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE); 450 uint8_t acpi_cntl = pci_get_long(lpc->d.config + ICH9_LPC_ACPI_CTRL); 451 uint8_t new_gsi; 452 453 if (acpi_cntl & ICH9_LPC_ACPI_CTRL_ACPI_EN) { 454 pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK; 455 } else { 456 pm_io_base = 0; 457 } 458 459 ich9_pm_iospace_update(&lpc->pm, pm_io_base); 460 461 new_gsi = ich9_lpc_sci_irq(lpc); 462 if (lpc->sci_level && new_gsi != lpc->sci_gsi) { 463 qemu_set_irq(lpc->pm.irq, 0); 464 lpc->sci_gsi = new_gsi; 465 qemu_set_irq(lpc->pm.irq, 1); 466 } 467 lpc->sci_gsi = new_gsi; 468 } 469 470 /* config:RCBA */ 471 static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rcba_old) 472 { 473 uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA); 474 475 if (rcba_old & ICH9_LPC_RCBA_EN) { 476 memory_region_del_subregion(get_system_memory(), &lpc->rcrb_mem); 477 } 478 if (rcba & ICH9_LPC_RCBA_EN) { 479 memory_region_add_subregion_overlap(get_system_memory(), 480 rcba & ICH9_LPC_RCBA_BA_MASK, 481 &lpc->rcrb_mem, 1); 482 } 483 } 484 485 /* config:GEN_PMCON* */ 486 static void 487 ich9_lpc_pmcon_update(ICH9LPCState *lpc) 488 { 489 uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1); 490 uint16_t wmask; 491 492 if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) { 493 wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1); 494 wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK; 495 pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask); 496 lpc->pm.smi_en_wmask &= ~1; 497 } 498 } 499 500 static int ich9_lpc_post_load(void *opaque, int version_id) 501 { 502 ICH9LPCState *lpc = opaque; 503 504 ich9_lpc_pmbase_sci_update(lpc); 505 ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RCBA_EN */); 506 ich9_lpc_pmcon_update(lpc); 507 return 0; 508 } 509 510 static void ich9_lpc_config_write(PCIDevice *d, 511 uint32_t addr, uint32_t val, int len) 512 { 513 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 514 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); 515 516 pci_default_write_config(d, addr, val, len); 517 if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4) || 518 ranges_overlap(addr, len, ICH9_LPC_ACPI_CTRL, 1)) { 519 ich9_lpc_pmbase_sci_update(lpc); 520 } 521 if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) { 522 ich9_lpc_rcba_update(lpc, rcba_old); 523 } 524 if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) { 525 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 526 } 527 if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) { 528 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 529 } 530 if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) { 531 ich9_lpc_pmcon_update(lpc); 532 } 533 } 534 535 static void ich9_lpc_reset(DeviceState *qdev) 536 { 537 PCIDevice *d = PCI_DEVICE(qdev); 538 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 539 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); 540 int i; 541 542 for (i = 0; i < 4; i++) { 543 pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i, 544 ICH9_LPC_PIRQ_ROUT_DEFAULT); 545 } 546 for (i = 0; i < 4; i++) { 547 pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i, 548 ICH9_LPC_PIRQ_ROUT_DEFAULT); 549 } 550 pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT); 551 552 pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT); 553 pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT); 554 555 ich9_cc_reset(lpc); 556 557 ich9_lpc_pmbase_sci_update(lpc); 558 ich9_lpc_rcba_update(lpc, rcba_old); 559 560 lpc->sci_level = 0; 561 lpc->rst_cnt = 0; 562 563 memset(lpc->smi_guest_features_le, 0, sizeof lpc->smi_guest_features_le); 564 lpc->smi_features_ok = 0; 565 lpc->smi_negotiated_features = 0; 566 } 567 568 /* root complex register block is mapped into memory space */ 569 static const MemoryRegionOps rcrb_mmio_ops = { 570 .read = ich9_cc_read, 571 .write = ich9_cc_write, 572 .endianness = DEVICE_LITTLE_ENDIAN, 573 }; 574 575 static void ich9_lpc_machine_ready(Notifier *n, void *opaque) 576 { 577 ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready); 578 MemoryRegion *io_as = pci_address_space_io(&s->d); 579 uint8_t *pci_conf; 580 581 pci_conf = s->d.config; 582 if (memory_region_present(io_as, 0x3f8)) { 583 /* com1 */ 584 pci_conf[0x82] |= 0x01; 585 } 586 if (memory_region_present(io_as, 0x2f8)) { 587 /* com2 */ 588 pci_conf[0x82] |= 0x02; 589 } 590 if (memory_region_present(io_as, 0x378)) { 591 /* lpt */ 592 pci_conf[0x82] |= 0x04; 593 } 594 if (memory_region_present(io_as, 0x3f2)) { 595 /* floppy */ 596 pci_conf[0x82] |= 0x08; 597 } 598 } 599 600 /* reset control */ 601 static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val, 602 unsigned len) 603 { 604 ICH9LPCState *lpc = opaque; 605 606 if (val & 4) { 607 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 608 return; 609 } 610 lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */ 611 } 612 613 static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len) 614 { 615 ICH9LPCState *lpc = opaque; 616 617 return lpc->rst_cnt; 618 } 619 620 static const MemoryRegionOps ich9_rst_cnt_ops = { 621 .read = ich9_rst_cnt_read, 622 .write = ich9_rst_cnt_write, 623 .endianness = DEVICE_LITTLE_ENDIAN 624 }; 625 626 static void ich9_lpc_get_sci_int(Object *obj, Visitor *v, const char *name, 627 void *opaque, Error **errp) 628 { 629 ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj); 630 uint32_t value = lpc->sci_gsi; 631 632 visit_type_uint32(v, name, &value, errp); 633 } 634 635 static void ich9_lpc_add_properties(ICH9LPCState *lpc) 636 { 637 static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE; 638 static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE; 639 640 object_property_add(OBJECT(lpc), ACPI_PM_PROP_SCI_INT, "uint32", 641 ich9_lpc_get_sci_int, 642 NULL, NULL, NULL, NULL); 643 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD, 644 &acpi_enable_cmd, NULL); 645 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD, 646 &acpi_disable_cmd, NULL); 647 648 ich9_pm_add_properties(OBJECT(lpc), &lpc->pm, NULL); 649 } 650 651 static void ich9_lpc_initfn(Object *obj) 652 { 653 ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj); 654 655 ich9_lpc_add_properties(lpc); 656 } 657 658 static void ich9_lpc_realize(PCIDevice *d, Error **errp) 659 { 660 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 661 DeviceState *dev = DEVICE(d); 662 ISABus *isa_bus; 663 664 isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(), 665 errp); 666 if (!isa_bus) { 667 return; 668 } 669 670 pci_set_long(d->wmask + ICH9_LPC_PMBASE, 671 ICH9_LPC_PMBASE_BASE_ADDRESS_MASK); 672 pci_set_byte(d->wmask + ICH9_LPC_PMBASE, 673 ICH9_LPC_ACPI_CTRL_ACPI_EN | 674 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK); 675 676 memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc, 677 "lpc-rcrb-mmio", ICH9_CC_SIZE); 678 679 lpc->isa_bus = isa_bus; 680 681 ich9_cc_init(lpc); 682 apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc); 683 684 lpc->machine_ready.notify = ich9_lpc_machine_ready; 685 qemu_add_machine_init_done_notifier(&lpc->machine_ready); 686 687 memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc, 688 "lpc-reset-control", 1); 689 memory_region_add_subregion_overlap(pci_address_space_io(d), 690 ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem, 691 1); 692 693 qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS); 694 695 isa_bus_irqs(isa_bus, lpc->gsi); 696 } 697 698 static bool ich9_rst_cnt_needed(void *opaque) 699 { 700 ICH9LPCState *lpc = opaque; 701 702 return (lpc->rst_cnt != 0); 703 } 704 705 static const VMStateDescription vmstate_ich9_rst_cnt = { 706 .name = "ICH9LPC/rst_cnt", 707 .version_id = 1, 708 .minimum_version_id = 1, 709 .needed = ich9_rst_cnt_needed, 710 .fields = (VMStateField[]) { 711 VMSTATE_UINT8(rst_cnt, ICH9LPCState), 712 VMSTATE_END_OF_LIST() 713 } 714 }; 715 716 static bool ich9_smi_feat_needed(void *opaque) 717 { 718 ICH9LPCState *lpc = opaque; 719 720 return !buffer_is_zero(lpc->smi_guest_features_le, 721 sizeof lpc->smi_guest_features_le) || 722 lpc->smi_features_ok; 723 } 724 725 static const VMStateDescription vmstate_ich9_smi_feat = { 726 .name = "ICH9LPC/smi_feat", 727 .version_id = 1, 728 .minimum_version_id = 1, 729 .needed = ich9_smi_feat_needed, 730 .fields = (VMStateField[]) { 731 VMSTATE_UINT8_ARRAY(smi_guest_features_le, ICH9LPCState, 732 sizeof(uint64_t)), 733 VMSTATE_UINT8(smi_features_ok, ICH9LPCState), 734 VMSTATE_UINT64(smi_negotiated_features, ICH9LPCState), 735 VMSTATE_END_OF_LIST() 736 } 737 }; 738 739 static const VMStateDescription vmstate_ich9_lpc = { 740 .name = "ICH9LPC", 741 .version_id = 1, 742 .minimum_version_id = 1, 743 .post_load = ich9_lpc_post_load, 744 .fields = (VMStateField[]) { 745 VMSTATE_PCI_DEVICE(d, ICH9LPCState), 746 VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState), 747 VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs), 748 VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE), 749 VMSTATE_UINT32(sci_level, ICH9LPCState), 750 VMSTATE_END_OF_LIST() 751 }, 752 .subsections = (const VMStateDescription*[]) { 753 &vmstate_ich9_rst_cnt, 754 &vmstate_ich9_smi_feat, 755 NULL 756 } 757 }; 758 759 static Property ich9_lpc_properties[] = { 760 DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, true), 761 DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features, 762 ICH9_LPC_SMI_F_BROADCAST_BIT, true), 763 DEFINE_PROP_END_OF_LIST(), 764 }; 765 766 static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) 767 { 768 ICH9LPCState *s = ICH9_LPC_DEVICE(adev); 769 770 acpi_send_gpe_event(&s->pm.acpi_regs, s->pm.irq, ev); 771 } 772 773 static void ich9_lpc_class_init(ObjectClass *klass, void *data) 774 { 775 DeviceClass *dc = DEVICE_CLASS(klass); 776 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 777 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 778 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 779 780 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 781 dc->reset = ich9_lpc_reset; 782 k->realize = ich9_lpc_realize; 783 dc->vmsd = &vmstate_ich9_lpc; 784 dc->props = ich9_lpc_properties; 785 k->config_write = ich9_lpc_config_write; 786 dc->desc = "ICH9 LPC bridge"; 787 k->vendor_id = PCI_VENDOR_ID_INTEL; 788 k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8; 789 k->revision = ICH9_A2_LPC_REVISION; 790 k->class_id = PCI_CLASS_BRIDGE_ISA; 791 /* 792 * Reason: part of ICH9 southbridge, needs to be wired up by 793 * pc_q35_init() 794 */ 795 dc->user_creatable = false; 796 hc->pre_plug = ich9_pm_device_pre_plug_cb; 797 hc->plug = ich9_pm_device_plug_cb; 798 hc->unplug_request = ich9_pm_device_unplug_request_cb; 799 hc->unplug = ich9_pm_device_unplug_cb; 800 adevc->ospm_status = ich9_pm_ospm_status; 801 adevc->send_event = ich9_send_gpe; 802 adevc->madt_cpu = pc_madt_cpu_entry; 803 } 804 805 static const TypeInfo ich9_lpc_info = { 806 .name = TYPE_ICH9_LPC_DEVICE, 807 .parent = TYPE_PCI_DEVICE, 808 .instance_size = sizeof(struct ICH9LPCState), 809 .instance_init = ich9_lpc_initfn, 810 .class_init = ich9_lpc_class_init, 811 .interfaces = (InterfaceInfo[]) { 812 { TYPE_HOTPLUG_HANDLER }, 813 { TYPE_ACPI_DEVICE_IF }, 814 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 815 { } 816 } 817 }; 818 819 static void ich9_lpc_register(void) 820 { 821 type_register_static(&ich9_lpc_info); 822 } 823 824 type_init(ich9_lpc_register); 825