1 /* 2 * QEMU ICH9 Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "qemu/osdep.h" 31 #include "qemu-common.h" 32 #include "cpu.h" 33 #include "hw/hw.h" 34 #include "qapi/visitor.h" 35 #include "qemu/range.h" 36 #include "hw/isa/isa.h" 37 #include "hw/sysbus.h" 38 #include "hw/i386/pc.h" 39 #include "hw/isa/apm.h" 40 #include "hw/i386/ioapic.h" 41 #include "hw/pci/pci.h" 42 #include "hw/pci/pcie_host.h" 43 #include "hw/pci/pci_bridge.h" 44 #include "hw/i386/ich9.h" 45 #include "hw/acpi/acpi.h" 46 #include "hw/acpi/ich9.h" 47 #include "hw/pci/pci_bus.h" 48 #include "exec/address-spaces.h" 49 #include "sysemu/sysemu.h" 50 #include "qom/cpu.h" 51 #include "hw/nvram/fw_cfg.h" 52 #include "qemu/cutils.h" 53 54 /*****************************************************************************/ 55 /* ICH9 LPC PCI to ISA bridge */ 56 57 static void ich9_lpc_reset(DeviceState *qdev); 58 59 /* chipset configuration register 60 * to access chipset configuration registers, pci_[sg]et_{byte, word, long} 61 * are used. 62 * Although it's not pci configuration space, it's little endian as Intel. 63 */ 64 65 static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir) 66 { 67 int intx; 68 for (intx = 0; intx < PCI_NUM_PINS; intx++) { 69 irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK; 70 } 71 } 72 73 static void ich9_cc_update(ICH9LPCState *lpc) 74 { 75 int slot; 76 int pci_intx; 77 78 const int reg_offsets[] = { 79 ICH9_CC_D25IR, 80 ICH9_CC_D26IR, 81 ICH9_CC_D27IR, 82 ICH9_CC_D28IR, 83 ICH9_CC_D29IR, 84 ICH9_CC_D30IR, 85 ICH9_CC_D31IR, 86 }; 87 const int *offset; 88 89 /* D{25 - 31}IR, but D30IR is read only to 0. */ 90 for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) { 91 if (slot == 30) { 92 continue; 93 } 94 ich9_cc_update_ir(lpc->irr[slot], 95 pci_get_word(lpc->chip_config + *offset)); 96 } 97 98 /* 99 * D30: DMI2PCI bridge 100 * It is arbitrarily decided how INTx lines of PCI devices behind 101 * the bridge are connected to pirq lines. Our choice is PIRQ[E-H]. 102 * INT[A-D] are connected to PIRQ[E-H] 103 */ 104 for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) { 105 lpc->irr[30][pci_intx] = pci_intx + 4; 106 } 107 } 108 109 static void ich9_cc_init(ICH9LPCState *lpc) 110 { 111 int slot; 112 int intx; 113 114 /* the default irq routing is arbitrary as long as it matches with 115 * acpi irq routing table. 116 * The one that is incompatible with piix_pci(= bochs) one is 117 * intentionally chosen to let the users know that the different 118 * board is used. 119 * 120 * int[A-D] -> pirq[E-F] 121 * avoid pirq A-D because they are used for pci express port 122 */ 123 for (slot = 0; slot < PCI_SLOT_MAX; slot++) { 124 for (intx = 0; intx < PCI_NUM_PINS; intx++) { 125 lpc->irr[slot][intx] = (slot + intx) % 4 + 4; 126 } 127 } 128 ich9_cc_update(lpc); 129 } 130 131 static void ich9_cc_reset(ICH9LPCState *lpc) 132 { 133 uint8_t *c = lpc->chip_config; 134 135 memset(lpc->chip_config, 0, sizeof(lpc->chip_config)); 136 137 pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT); 138 pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT); 139 pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT); 140 pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT); 141 pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT); 142 pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT); 143 pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT); 144 pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT); 145 146 ich9_cc_update(lpc); 147 } 148 149 static void ich9_cc_addr_len(uint64_t *addr, unsigned *len) 150 { 151 *addr &= ICH9_CC_ADDR_MASK; 152 if (*addr + *len >= ICH9_CC_SIZE) { 153 *len = ICH9_CC_SIZE - *addr; 154 } 155 } 156 157 /* val: little endian */ 158 static void ich9_cc_write(void *opaque, hwaddr addr, 159 uint64_t val, unsigned len) 160 { 161 ICH9LPCState *lpc = (ICH9LPCState *)opaque; 162 163 ich9_cc_addr_len(&addr, &len); 164 memcpy(lpc->chip_config + addr, &val, len); 165 pci_bus_fire_intx_routing_notifier(lpc->d.bus); 166 ich9_cc_update(lpc); 167 } 168 169 /* return value: little endian */ 170 static uint64_t ich9_cc_read(void *opaque, hwaddr addr, 171 unsigned len) 172 { 173 ICH9LPCState *lpc = (ICH9LPCState *)opaque; 174 175 uint32_t val = 0; 176 ich9_cc_addr_len(&addr, &len); 177 memcpy(&val, lpc->chip_config + addr, len); 178 return val; 179 } 180 181 /* IRQ routing */ 182 /* */ 183 static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis) 184 { 185 *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK; 186 *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN; 187 } 188 189 static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num, 190 int *pic_irq, int *pic_dis) 191 { 192 switch (pirq_num) { 193 case 0 ... 3: /* A-D */ 194 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num], 195 pic_irq, pic_dis); 196 return; 197 case 4 ... 7: /* E-H */ 198 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)], 199 pic_irq, pic_dis); 200 return; 201 default: 202 break; 203 } 204 abort(); 205 } 206 207 /* gsi: i8259+ioapic irq 0-15, otherwise assert */ 208 static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi) 209 { 210 int i, pic_level; 211 212 assert(gsi < ICH9_LPC_PIC_NUM_PINS); 213 214 /* The pic level is the logical OR of all the PCI irqs mapped to it */ 215 pic_level = 0; 216 for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) { 217 int tmp_irq; 218 int tmp_dis; 219 ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis); 220 if (!tmp_dis && tmp_irq == gsi) { 221 pic_level |= pci_bus_get_irq_level(lpc->d.bus, i); 222 } 223 } 224 if (gsi == lpc->sci_gsi) { 225 pic_level |= lpc->sci_level; 226 } 227 228 qemu_set_irq(lpc->gsi[gsi], pic_level); 229 } 230 231 /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */ 232 static int ich9_pirq_to_gsi(int pirq) 233 { 234 return pirq + ICH9_LPC_PIC_NUM_PINS; 235 } 236 237 static int ich9_gsi_to_pirq(int gsi) 238 { 239 return gsi - ICH9_LPC_PIC_NUM_PINS; 240 } 241 242 /* gsi: ioapic irq 16-23, otherwise assert */ 243 static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi) 244 { 245 int level = 0; 246 247 assert(gsi >= ICH9_LPC_PIC_NUM_PINS); 248 249 level |= pci_bus_get_irq_level(lpc->d.bus, ich9_gsi_to_pirq(gsi)); 250 if (gsi == lpc->sci_gsi) { 251 level |= lpc->sci_level; 252 } 253 254 qemu_set_irq(lpc->gsi[gsi], level); 255 } 256 257 void ich9_lpc_set_irq(void *opaque, int pirq, int level) 258 { 259 ICH9LPCState *lpc = opaque; 260 int pic_irq, pic_dis; 261 262 assert(0 <= pirq); 263 assert(pirq < ICH9_LPC_NB_PIRQS); 264 265 ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq)); 266 ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis); 267 ich9_lpc_update_pic(lpc, pic_irq); 268 } 269 270 /* return the pirq number (PIRQ[A-H]:0-7) corresponding to 271 * a given device irq pin. 272 */ 273 int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) 274 { 275 BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); 276 PCIBus *pci_bus = PCI_BUS(bus); 277 PCIDevice *lpc_pdev = 278 pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)]; 279 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev); 280 281 return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; 282 } 283 284 PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin) 285 { 286 ICH9LPCState *lpc = opaque; 287 PCIINTxRoute route; 288 int pic_irq; 289 int pic_dis; 290 291 assert(0 <= pirq_pin); 292 assert(pirq_pin < ICH9_LPC_NB_PIRQS); 293 294 route.mode = PCI_INTX_ENABLED; 295 ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis); 296 if (!pic_dis) { 297 if (pic_irq < ICH9_LPC_PIC_NUM_PINS) { 298 route.irq = pic_irq; 299 } else { 300 route.mode = PCI_INTX_DISABLED; 301 route.irq = -1; 302 } 303 } else { 304 route.irq = ich9_pirq_to_gsi(pirq_pin); 305 } 306 307 return route; 308 } 309 310 void ich9_generate_smi(void) 311 { 312 cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); 313 } 314 315 void ich9_generate_nmi(void) 316 { 317 cpu_interrupt(first_cpu, CPU_INTERRUPT_NMI); 318 } 319 320 static int ich9_lpc_sci_irq(ICH9LPCState *lpc) 321 { 322 switch (lpc->d.config[ICH9_LPC_ACPI_CTRL] & 323 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK) { 324 case ICH9_LPC_ACPI_CTRL_9: 325 return 9; 326 case ICH9_LPC_ACPI_CTRL_10: 327 return 10; 328 case ICH9_LPC_ACPI_CTRL_11: 329 return 11; 330 case ICH9_LPC_ACPI_CTRL_20: 331 return 20; 332 case ICH9_LPC_ACPI_CTRL_21: 333 return 21; 334 default: 335 /* reserved */ 336 break; 337 } 338 return -1; 339 } 340 341 static void ich9_set_sci(void *opaque, int irq_num, int level) 342 { 343 ICH9LPCState *lpc = opaque; 344 int irq; 345 346 assert(irq_num == 0); 347 level = !!level; 348 if (level == lpc->sci_level) { 349 return; 350 } 351 lpc->sci_level = level; 352 353 irq = lpc->sci_gsi; 354 if (irq < 0) { 355 return; 356 } 357 358 if (irq >= ICH9_LPC_PIC_NUM_PINS) { 359 ich9_lpc_update_apic(lpc, irq); 360 } else { 361 ich9_lpc_update_pic(lpc, irq); 362 } 363 } 364 365 static void smi_features_ok_callback(void *opaque) 366 { 367 ICH9LPCState *lpc = opaque; 368 uint64_t guest_features; 369 370 if (lpc->smi_features_ok) { 371 /* negotiation already complete, features locked */ 372 return; 373 } 374 375 memcpy(&guest_features, lpc->smi_guest_features_le, sizeof guest_features); 376 le64_to_cpus(&guest_features); 377 if (guest_features & ~lpc->smi_host_features) { 378 /* guest requests invalid features, leave @features_ok at zero */ 379 return; 380 } 381 382 /* valid feature subset requested, lock it down, report success */ 383 lpc->smi_negotiated_features = guest_features; 384 lpc->smi_features_ok = 1; 385 } 386 387 void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled) 388 { 389 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci); 390 qemu_irq sci_irq; 391 FWCfgState *fw_cfg = fw_cfg_find(); 392 393 sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0); 394 ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq); 395 396 if (lpc->smi_host_features && fw_cfg) { 397 uint64_t host_features_le; 398 399 host_features_le = cpu_to_le64(lpc->smi_host_features); 400 memcpy(lpc->smi_host_features_le, &host_features_le, 401 sizeof host_features_le); 402 fw_cfg_add_file(fw_cfg, "etc/smi/supported-features", 403 lpc->smi_host_features_le, 404 sizeof lpc->smi_host_features_le); 405 406 /* The other two guest-visible fields are cleared on device reset, we 407 * just link them into fw_cfg here. 408 */ 409 fw_cfg_add_file_callback(fw_cfg, "etc/smi/requested-features", 410 NULL, NULL, 411 lpc->smi_guest_features_le, 412 sizeof lpc->smi_guest_features_le, 413 false); 414 fw_cfg_add_file_callback(fw_cfg, "etc/smi/features-ok", 415 smi_features_ok_callback, lpc, 416 &lpc->smi_features_ok, 417 sizeof lpc->smi_features_ok, 418 true); 419 } 420 421 ich9_lpc_reset(&lpc->d.qdev); 422 } 423 424 /* APM */ 425 426 static void ich9_apm_ctrl_changed(uint32_t val, void *arg) 427 { 428 ICH9LPCState *lpc = arg; 429 430 /* ACPI specs 3.0, 4.7.2.5 */ 431 acpi_pm1_cnt_update(&lpc->pm.acpi_regs, 432 val == ICH9_APM_ACPI_ENABLE, 433 val == ICH9_APM_ACPI_DISABLE); 434 if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) { 435 return; 436 } 437 438 /* SMI_EN = PMBASE + 30. SMI control and enable register */ 439 if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { 440 if (lpc->smi_negotiated_features & 441 (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) { 442 CPUState *cs; 443 CPU_FOREACH(cs) { 444 cpu_interrupt(cs, CPU_INTERRUPT_SMI); 445 } 446 } else { 447 cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); 448 } 449 } 450 } 451 452 /* config:PMBASE */ 453 static void 454 ich9_lpc_pmbase_sci_update(ICH9LPCState *lpc) 455 { 456 uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE); 457 uint8_t acpi_cntl = pci_get_long(lpc->d.config + ICH9_LPC_ACPI_CTRL); 458 uint8_t new_gsi; 459 460 if (acpi_cntl & ICH9_LPC_ACPI_CTRL_ACPI_EN) { 461 pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK; 462 } else { 463 pm_io_base = 0; 464 } 465 466 ich9_pm_iospace_update(&lpc->pm, pm_io_base); 467 468 new_gsi = ich9_lpc_sci_irq(lpc); 469 if (lpc->sci_level && new_gsi != lpc->sci_gsi) { 470 qemu_set_irq(lpc->pm.irq, 0); 471 lpc->sci_gsi = new_gsi; 472 qemu_set_irq(lpc->pm.irq, 1); 473 } 474 lpc->sci_gsi = new_gsi; 475 } 476 477 /* config:RCBA */ 478 static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rcba_old) 479 { 480 uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA); 481 482 if (rcba_old & ICH9_LPC_RCBA_EN) { 483 memory_region_del_subregion(get_system_memory(), &lpc->rcrb_mem); 484 } 485 if (rcba & ICH9_LPC_RCBA_EN) { 486 memory_region_add_subregion_overlap(get_system_memory(), 487 rcba & ICH9_LPC_RCBA_BA_MASK, 488 &lpc->rcrb_mem, 1); 489 } 490 } 491 492 /* config:GEN_PMCON* */ 493 static void 494 ich9_lpc_pmcon_update(ICH9LPCState *lpc) 495 { 496 uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1); 497 uint16_t wmask; 498 499 if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) { 500 wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1); 501 wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK; 502 pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask); 503 lpc->pm.smi_en_wmask &= ~1; 504 } 505 } 506 507 static int ich9_lpc_post_load(void *opaque, int version_id) 508 { 509 ICH9LPCState *lpc = opaque; 510 511 ich9_lpc_pmbase_sci_update(lpc); 512 ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RCBA_EN */); 513 ich9_lpc_pmcon_update(lpc); 514 return 0; 515 } 516 517 static void ich9_lpc_config_write(PCIDevice *d, 518 uint32_t addr, uint32_t val, int len) 519 { 520 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 521 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); 522 523 pci_default_write_config(d, addr, val, len); 524 if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4) || 525 ranges_overlap(addr, len, ICH9_LPC_ACPI_CTRL, 1)) { 526 ich9_lpc_pmbase_sci_update(lpc); 527 } 528 if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) { 529 ich9_lpc_rcba_update(lpc, rcba_old); 530 } 531 if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) { 532 pci_bus_fire_intx_routing_notifier(lpc->d.bus); 533 } 534 if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) { 535 pci_bus_fire_intx_routing_notifier(lpc->d.bus); 536 } 537 if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) { 538 ich9_lpc_pmcon_update(lpc); 539 } 540 } 541 542 static void ich9_lpc_reset(DeviceState *qdev) 543 { 544 PCIDevice *d = PCI_DEVICE(qdev); 545 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 546 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); 547 int i; 548 549 for (i = 0; i < 4; i++) { 550 pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i, 551 ICH9_LPC_PIRQ_ROUT_DEFAULT); 552 } 553 for (i = 0; i < 4; i++) { 554 pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i, 555 ICH9_LPC_PIRQ_ROUT_DEFAULT); 556 } 557 pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT); 558 559 pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT); 560 pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT); 561 562 ich9_cc_reset(lpc); 563 564 ich9_lpc_pmbase_sci_update(lpc); 565 ich9_lpc_rcba_update(lpc, rcba_old); 566 567 lpc->sci_level = 0; 568 lpc->rst_cnt = 0; 569 570 memset(lpc->smi_guest_features_le, 0, sizeof lpc->smi_guest_features_le); 571 lpc->smi_features_ok = 0; 572 lpc->smi_negotiated_features = 0; 573 } 574 575 /* root complex register block is mapped into memory space */ 576 static const MemoryRegionOps rcrb_mmio_ops = { 577 .read = ich9_cc_read, 578 .write = ich9_cc_write, 579 .endianness = DEVICE_LITTLE_ENDIAN, 580 }; 581 582 static void ich9_lpc_machine_ready(Notifier *n, void *opaque) 583 { 584 ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready); 585 MemoryRegion *io_as = pci_address_space_io(&s->d); 586 uint8_t *pci_conf; 587 588 pci_conf = s->d.config; 589 if (memory_region_present(io_as, 0x3f8)) { 590 /* com1 */ 591 pci_conf[0x82] |= 0x01; 592 } 593 if (memory_region_present(io_as, 0x2f8)) { 594 /* com2 */ 595 pci_conf[0x82] |= 0x02; 596 } 597 if (memory_region_present(io_as, 0x378)) { 598 /* lpt */ 599 pci_conf[0x82] |= 0x04; 600 } 601 if (memory_region_present(io_as, 0x3f2)) { 602 /* floppy */ 603 pci_conf[0x82] |= 0x08; 604 } 605 } 606 607 /* reset control */ 608 static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val, 609 unsigned len) 610 { 611 ICH9LPCState *lpc = opaque; 612 613 if (val & 4) { 614 qemu_system_reset_request(); 615 return; 616 } 617 lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */ 618 } 619 620 static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len) 621 { 622 ICH9LPCState *lpc = opaque; 623 624 return lpc->rst_cnt; 625 } 626 627 static const MemoryRegionOps ich9_rst_cnt_ops = { 628 .read = ich9_rst_cnt_read, 629 .write = ich9_rst_cnt_write, 630 .endianness = DEVICE_LITTLE_ENDIAN 631 }; 632 633 Object *ich9_lpc_find(void) 634 { 635 bool ambig; 636 Object *o = object_resolve_path_type("", TYPE_ICH9_LPC_DEVICE, &ambig); 637 638 if (ambig) { 639 return NULL; 640 } 641 return o; 642 } 643 644 static void ich9_lpc_get_sci_int(Object *obj, Visitor *v, const char *name, 645 void *opaque, Error **errp) 646 { 647 ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj); 648 uint32_t value = lpc->sci_gsi; 649 650 visit_type_uint32(v, name, &value, errp); 651 } 652 653 static void ich9_lpc_add_properties(ICH9LPCState *lpc) 654 { 655 static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE; 656 static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE; 657 658 object_property_add(OBJECT(lpc), ACPI_PM_PROP_SCI_INT, "uint32", 659 ich9_lpc_get_sci_int, 660 NULL, NULL, NULL, NULL); 661 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD, 662 &acpi_enable_cmd, NULL); 663 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD, 664 &acpi_disable_cmd, NULL); 665 666 ich9_pm_add_properties(OBJECT(lpc), &lpc->pm, NULL); 667 } 668 669 static void ich9_lpc_initfn(Object *obj) 670 { 671 ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj); 672 673 ich9_lpc_add_properties(lpc); 674 } 675 676 static void ich9_lpc_realize(PCIDevice *d, Error **errp) 677 { 678 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 679 DeviceState *dev = DEVICE(d); 680 ISABus *isa_bus; 681 682 isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(), 683 errp); 684 if (!isa_bus) { 685 return; 686 } 687 688 pci_set_long(d->wmask + ICH9_LPC_PMBASE, 689 ICH9_LPC_PMBASE_BASE_ADDRESS_MASK); 690 pci_set_byte(d->wmask + ICH9_LPC_PMBASE, 691 ICH9_LPC_ACPI_CTRL_ACPI_EN | 692 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK); 693 694 memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc, 695 "lpc-rcrb-mmio", ICH9_CC_SIZE); 696 697 lpc->isa_bus = isa_bus; 698 699 ich9_cc_init(lpc); 700 apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc); 701 702 lpc->machine_ready.notify = ich9_lpc_machine_ready; 703 qemu_add_machine_init_done_notifier(&lpc->machine_ready); 704 705 memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc, 706 "lpc-reset-control", 1); 707 memory_region_add_subregion_overlap(pci_address_space_io(d), 708 ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem, 709 1); 710 711 qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS); 712 713 isa_bus_irqs(isa_bus, lpc->gsi); 714 } 715 716 static bool ich9_rst_cnt_needed(void *opaque) 717 { 718 ICH9LPCState *lpc = opaque; 719 720 return (lpc->rst_cnt != 0); 721 } 722 723 static const VMStateDescription vmstate_ich9_rst_cnt = { 724 .name = "ICH9LPC/rst_cnt", 725 .version_id = 1, 726 .minimum_version_id = 1, 727 .needed = ich9_rst_cnt_needed, 728 .fields = (VMStateField[]) { 729 VMSTATE_UINT8(rst_cnt, ICH9LPCState), 730 VMSTATE_END_OF_LIST() 731 } 732 }; 733 734 static bool ich9_smi_feat_needed(void *opaque) 735 { 736 ICH9LPCState *lpc = opaque; 737 738 return !buffer_is_zero(lpc->smi_guest_features_le, 739 sizeof lpc->smi_guest_features_le) || 740 lpc->smi_features_ok; 741 } 742 743 static const VMStateDescription vmstate_ich9_smi_feat = { 744 .name = "ICH9LPC/smi_feat", 745 .version_id = 1, 746 .minimum_version_id = 1, 747 .needed = ich9_smi_feat_needed, 748 .fields = (VMStateField[]) { 749 VMSTATE_UINT8_ARRAY(smi_guest_features_le, ICH9LPCState, 750 sizeof(uint64_t)), 751 VMSTATE_UINT8(smi_features_ok, ICH9LPCState), 752 VMSTATE_UINT64(smi_negotiated_features, ICH9LPCState), 753 VMSTATE_END_OF_LIST() 754 } 755 }; 756 757 static const VMStateDescription vmstate_ich9_lpc = { 758 .name = "ICH9LPC", 759 .version_id = 1, 760 .minimum_version_id = 1, 761 .post_load = ich9_lpc_post_load, 762 .fields = (VMStateField[]) { 763 VMSTATE_PCI_DEVICE(d, ICH9LPCState), 764 VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState), 765 VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs), 766 VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE), 767 VMSTATE_UINT32(sci_level, ICH9LPCState), 768 VMSTATE_END_OF_LIST() 769 }, 770 .subsections = (const VMStateDescription*[]) { 771 &vmstate_ich9_rst_cnt, 772 &vmstate_ich9_smi_feat, 773 NULL 774 } 775 }; 776 777 static Property ich9_lpc_properties[] = { 778 DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, true), 779 DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features, 780 ICH9_LPC_SMI_F_BROADCAST_BIT, true), 781 DEFINE_PROP_END_OF_LIST(), 782 }; 783 784 static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) 785 { 786 ICH9LPCState *s = ICH9_LPC_DEVICE(adev); 787 788 acpi_send_gpe_event(&s->pm.acpi_regs, s->pm.irq, ev); 789 } 790 791 static void ich9_lpc_class_init(ObjectClass *klass, void *data) 792 { 793 DeviceClass *dc = DEVICE_CLASS(klass); 794 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 795 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 796 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 797 798 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 799 dc->reset = ich9_lpc_reset; 800 k->realize = ich9_lpc_realize; 801 dc->vmsd = &vmstate_ich9_lpc; 802 dc->props = ich9_lpc_properties; 803 k->config_write = ich9_lpc_config_write; 804 dc->desc = "ICH9 LPC bridge"; 805 k->vendor_id = PCI_VENDOR_ID_INTEL; 806 k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8; 807 k->revision = ICH9_A2_LPC_REVISION; 808 k->class_id = PCI_CLASS_BRIDGE_ISA; 809 /* 810 * Reason: part of ICH9 southbridge, needs to be wired up by 811 * pc_q35_init() 812 */ 813 dc->cannot_instantiate_with_device_add_yet = true; 814 hc->plug = ich9_pm_device_plug_cb; 815 hc->unplug_request = ich9_pm_device_unplug_request_cb; 816 hc->unplug = ich9_pm_device_unplug_cb; 817 adevc->ospm_status = ich9_pm_ospm_status; 818 adevc->send_event = ich9_send_gpe; 819 adevc->madt_cpu = pc_madt_cpu_entry; 820 } 821 822 static const TypeInfo ich9_lpc_info = { 823 .name = TYPE_ICH9_LPC_DEVICE, 824 .parent = TYPE_PCI_DEVICE, 825 .instance_size = sizeof(struct ICH9LPCState), 826 .instance_init = ich9_lpc_initfn, 827 .class_init = ich9_lpc_class_init, 828 .interfaces = (InterfaceInfo[]) { 829 { TYPE_HOTPLUG_HANDLER }, 830 { TYPE_ACPI_DEVICE_IF }, 831 { } 832 } 833 }; 834 835 static void ich9_lpc_register(void) 836 { 837 type_register_static(&ich9_lpc_info); 838 } 839 840 type_init(ich9_lpc_register); 841