1 /* 2 * QEMU ICH9 Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/log.h" 33 #include "cpu.h" 34 #include "qapi/visitor.h" 35 #include "qemu/range.h" 36 #include "hw/isa/isa.h" 37 #include "migration/vmstate.h" 38 #include "hw/irq.h" 39 #include "hw/isa/apm.h" 40 #include "hw/pci/pci.h" 41 #include "hw/pci/pci_bridge.h" 42 #include "hw/i386/ich9.h" 43 #include "hw/acpi/acpi.h" 44 #include "hw/acpi/ich9.h" 45 #include "hw/pci/pci_bus.h" 46 #include "hw/qdev-properties.h" 47 #include "sysemu/runstate.h" 48 #include "sysemu/sysemu.h" 49 #include "hw/core/cpu.h" 50 #include "hw/nvram/fw_cfg.h" 51 #include "qemu/cutils.h" 52 53 /*****************************************************************************/ 54 /* ICH9 LPC PCI to ISA bridge */ 55 56 static void ich9_lpc_reset(DeviceState *qdev); 57 58 /* chipset configuration register 59 * to access chipset configuration registers, pci_[sg]et_{byte, word, long} 60 * are used. 61 * Although it's not pci configuration space, it's little endian as Intel. 62 */ 63 64 static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir) 65 { 66 int intx; 67 for (intx = 0; intx < PCI_NUM_PINS; intx++) { 68 irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK; 69 } 70 } 71 72 static void ich9_cc_update(ICH9LPCState *lpc) 73 { 74 int slot; 75 int pci_intx; 76 77 const int reg_offsets[] = { 78 ICH9_CC_D25IR, 79 ICH9_CC_D26IR, 80 ICH9_CC_D27IR, 81 ICH9_CC_D28IR, 82 ICH9_CC_D29IR, 83 ICH9_CC_D30IR, 84 ICH9_CC_D31IR, 85 }; 86 const int *offset; 87 88 /* D{25 - 31}IR, but D30IR is read only to 0. */ 89 for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) { 90 if (slot == 30) { 91 continue; 92 } 93 ich9_cc_update_ir(lpc->irr[slot], 94 pci_get_word(lpc->chip_config + *offset)); 95 } 96 97 /* 98 * D30: DMI2PCI bridge 99 * It is arbitrarily decided how INTx lines of PCI devices behind 100 * the bridge are connected to pirq lines. Our choice is PIRQ[E-H]. 101 * INT[A-D] are connected to PIRQ[E-H] 102 */ 103 for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) { 104 lpc->irr[30][pci_intx] = pci_intx + 4; 105 } 106 } 107 108 static void ich9_cc_init(ICH9LPCState *lpc) 109 { 110 int slot; 111 int intx; 112 113 /* the default irq routing is arbitrary as long as it matches with 114 * acpi irq routing table. 115 * The one that is incompatible with piix_pci(= bochs) one is 116 * intentionally chosen to let the users know that the different 117 * board is used. 118 * 119 * int[A-D] -> pirq[E-F] 120 * avoid pirq A-D because they are used for pci express port 121 */ 122 for (slot = 0; slot < PCI_SLOT_MAX; slot++) { 123 for (intx = 0; intx < PCI_NUM_PINS; intx++) { 124 lpc->irr[slot][intx] = (slot + intx) % 4 + 4; 125 } 126 } 127 ich9_cc_update(lpc); 128 } 129 130 static void ich9_cc_reset(ICH9LPCState *lpc) 131 { 132 uint8_t *c = lpc->chip_config; 133 134 memset(lpc->chip_config, 0, sizeof(lpc->chip_config)); 135 136 pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT); 137 pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT); 138 pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT); 139 pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT); 140 pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT); 141 pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT); 142 pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT); 143 pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT); 144 145 ich9_cc_update(lpc); 146 } 147 148 static void ich9_cc_addr_len(uint64_t *addr, unsigned *len) 149 { 150 *addr &= ICH9_CC_ADDR_MASK; 151 if (*addr + *len >= ICH9_CC_SIZE) { 152 *len = ICH9_CC_SIZE - *addr; 153 } 154 } 155 156 /* val: little endian */ 157 static void ich9_cc_write(void *opaque, hwaddr addr, 158 uint64_t val, unsigned len) 159 { 160 ICH9LPCState *lpc = (ICH9LPCState *)opaque; 161 162 ich9_cc_addr_len(&addr, &len); 163 memcpy(lpc->chip_config + addr, &val, len); 164 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 165 ich9_cc_update(lpc); 166 } 167 168 /* return value: little endian */ 169 static uint64_t ich9_cc_read(void *opaque, hwaddr addr, 170 unsigned len) 171 { 172 ICH9LPCState *lpc = (ICH9LPCState *)opaque; 173 174 uint32_t val = 0; 175 ich9_cc_addr_len(&addr, &len); 176 memcpy(&val, lpc->chip_config + addr, len); 177 return val; 178 } 179 180 /* IRQ routing */ 181 /* */ 182 static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis) 183 { 184 *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK; 185 *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN; 186 } 187 188 static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num, 189 int *pic_irq, int *pic_dis) 190 { 191 switch (pirq_num) { 192 case 0 ... 3: /* A-D */ 193 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num], 194 pic_irq, pic_dis); 195 return; 196 case 4 ... 7: /* E-H */ 197 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)], 198 pic_irq, pic_dis); 199 return; 200 default: 201 break; 202 } 203 abort(); 204 } 205 206 /* gsi: i8259+ioapic irq 0-15, otherwise assert */ 207 static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi) 208 { 209 int i, pic_level; 210 211 assert(gsi < ICH9_LPC_PIC_NUM_PINS); 212 213 /* The pic level is the logical OR of all the PCI irqs mapped to it */ 214 pic_level = 0; 215 for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) { 216 int tmp_irq; 217 int tmp_dis; 218 ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis); 219 if (!tmp_dis && tmp_irq == gsi) { 220 pic_level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), i); 221 } 222 } 223 if (gsi == lpc->sci_gsi) { 224 pic_level |= lpc->sci_level; 225 } 226 227 qemu_set_irq(lpc->gsi[gsi], pic_level); 228 } 229 230 /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */ 231 static int ich9_pirq_to_gsi(int pirq) 232 { 233 return pirq + ICH9_LPC_PIC_NUM_PINS; 234 } 235 236 static int ich9_gsi_to_pirq(int gsi) 237 { 238 return gsi - ICH9_LPC_PIC_NUM_PINS; 239 } 240 241 /* gsi: ioapic irq 16-23, otherwise assert */ 242 static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi) 243 { 244 int level = 0; 245 246 assert(gsi >= ICH9_LPC_PIC_NUM_PINS); 247 248 level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), ich9_gsi_to_pirq(gsi)); 249 if (gsi == lpc->sci_gsi) { 250 level |= lpc->sci_level; 251 } 252 253 qemu_set_irq(lpc->gsi[gsi], level); 254 } 255 256 void ich9_lpc_set_irq(void *opaque, int pirq, int level) 257 { 258 ICH9LPCState *lpc = opaque; 259 int pic_irq, pic_dis; 260 261 assert(0 <= pirq); 262 assert(pirq < ICH9_LPC_NB_PIRQS); 263 264 ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq)); 265 ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis); 266 ich9_lpc_update_pic(lpc, pic_irq); 267 } 268 269 /* return the pirq number (PIRQ[A-H]:0-7) corresponding to 270 * a given device irq pin. 271 */ 272 int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) 273 { 274 BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); 275 PCIBus *pci_bus = PCI_BUS(bus); 276 PCIDevice *lpc_pdev = 277 pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)]; 278 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev); 279 280 return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; 281 } 282 283 PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin) 284 { 285 ICH9LPCState *lpc = opaque; 286 PCIINTxRoute route; 287 int pic_irq; 288 int pic_dis; 289 290 assert(0 <= pirq_pin); 291 assert(pirq_pin < ICH9_LPC_NB_PIRQS); 292 293 route.mode = PCI_INTX_ENABLED; 294 ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis); 295 if (!pic_dis) { 296 if (pic_irq < ICH9_LPC_PIC_NUM_PINS) { 297 route.irq = pic_irq; 298 } else { 299 route.mode = PCI_INTX_DISABLED; 300 route.irq = -1; 301 } 302 } else { 303 route.irq = ich9_pirq_to_gsi(pirq_pin); 304 } 305 306 return route; 307 } 308 309 void ich9_generate_smi(void) 310 { 311 cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); 312 } 313 314 /* Returns -1 on error, IRQ number on success */ 315 static int ich9_lpc_sci_irq(ICH9LPCState *lpc) 316 { 317 uint8_t sel = lpc->d.config[ICH9_LPC_ACPI_CTRL] & 318 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK; 319 switch (sel) { 320 case ICH9_LPC_ACPI_CTRL_9: 321 return 9; 322 case ICH9_LPC_ACPI_CTRL_10: 323 return 10; 324 case ICH9_LPC_ACPI_CTRL_11: 325 return 11; 326 case ICH9_LPC_ACPI_CTRL_20: 327 return 20; 328 case ICH9_LPC_ACPI_CTRL_21: 329 return 21; 330 default: 331 /* reserved */ 332 qemu_log_mask(LOG_GUEST_ERROR, 333 "ICH9 LPC: SCI IRQ SEL #%u is reserved\n", sel); 334 break; 335 } 336 return -1; 337 } 338 339 static void ich9_set_sci(void *opaque, int irq_num, int level) 340 { 341 ICH9LPCState *lpc = opaque; 342 int irq; 343 344 assert(irq_num == 0); 345 level = !!level; 346 if (level == lpc->sci_level) { 347 return; 348 } 349 lpc->sci_level = level; 350 351 irq = lpc->sci_gsi; 352 if (irq < 0) { 353 return; 354 } 355 356 if (irq >= ICH9_LPC_PIC_NUM_PINS) { 357 ich9_lpc_update_apic(lpc, irq); 358 } else { 359 ich9_lpc_update_pic(lpc, irq); 360 } 361 } 362 363 static void smi_features_ok_callback(void *opaque) 364 { 365 ICH9LPCState *lpc = opaque; 366 uint64_t guest_features; 367 uint64_t guest_cpu_hotplug_features; 368 369 if (lpc->smi_features_ok) { 370 /* negotiation already complete, features locked */ 371 return; 372 } 373 374 memcpy(&guest_features, lpc->smi_guest_features_le, sizeof guest_features); 375 le64_to_cpus(&guest_features); 376 if (guest_features & ~lpc->smi_host_features) { 377 /* guest requests invalid features, leave @features_ok at zero */ 378 return; 379 } 380 381 guest_cpu_hotplug_features = guest_features & 382 (BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT) | 383 BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 384 if (!(guest_features & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT)) && 385 guest_cpu_hotplug_features) { 386 /* 387 * cpu hot-[un]plug with SMI requires SMI broadcast, 388 * leave @features_ok at zero 389 */ 390 return; 391 } 392 393 if (guest_cpu_hotplug_features == 394 BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) { 395 /* cpu hot-unplug is unsupported without cpu-hotplug */ 396 return; 397 } 398 399 /* valid feature subset requested, lock it down, report success */ 400 lpc->smi_negotiated_features = guest_features; 401 lpc->smi_features_ok = 1; 402 } 403 404 void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled) 405 { 406 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci); 407 qemu_irq sci_irq; 408 FWCfgState *fw_cfg = fw_cfg_find(); 409 410 sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0); 411 ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq); 412 413 if (lpc->smi_host_features && fw_cfg) { 414 uint64_t host_features_le; 415 416 host_features_le = cpu_to_le64(lpc->smi_host_features); 417 memcpy(lpc->smi_host_features_le, &host_features_le, 418 sizeof host_features_le); 419 fw_cfg_add_file(fw_cfg, "etc/smi/supported-features", 420 lpc->smi_host_features_le, 421 sizeof lpc->smi_host_features_le); 422 423 /* The other two guest-visible fields are cleared on device reset, we 424 * just link them into fw_cfg here. 425 */ 426 fw_cfg_add_file_callback(fw_cfg, "etc/smi/requested-features", 427 NULL, NULL, NULL, 428 lpc->smi_guest_features_le, 429 sizeof lpc->smi_guest_features_le, 430 false); 431 fw_cfg_add_file_callback(fw_cfg, "etc/smi/features-ok", 432 smi_features_ok_callback, NULL, lpc, 433 &lpc->smi_features_ok, 434 sizeof lpc->smi_features_ok, 435 true); 436 } 437 438 ich9_lpc_reset(DEVICE(lpc)); 439 } 440 441 /* APM */ 442 443 static void ich9_apm_ctrl_changed(uint32_t val, void *arg) 444 { 445 ICH9LPCState *lpc = arg; 446 447 /* ACPI specs 3.0, 4.7.2.5 */ 448 acpi_pm1_cnt_update(&lpc->pm.acpi_regs, 449 val == ICH9_APM_ACPI_ENABLE, 450 val == ICH9_APM_ACPI_DISABLE); 451 if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) { 452 return; 453 } 454 455 /* SMI_EN = PMBASE + 30. SMI control and enable register */ 456 if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { 457 if (lpc->smi_negotiated_features & 458 (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) { 459 CPUState *cs; 460 CPU_FOREACH(cs) { 461 cpu_interrupt(cs, CPU_INTERRUPT_SMI); 462 } 463 } else { 464 cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); 465 } 466 } 467 } 468 469 /* config:PMBASE */ 470 static void 471 ich9_lpc_pmbase_sci_update(ICH9LPCState *lpc) 472 { 473 uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE); 474 uint8_t acpi_cntl = pci_get_long(lpc->d.config + ICH9_LPC_ACPI_CTRL); 475 int new_gsi; 476 477 if (acpi_cntl & ICH9_LPC_ACPI_CTRL_ACPI_EN) { 478 pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK; 479 } else { 480 pm_io_base = 0; 481 } 482 483 ich9_pm_iospace_update(&lpc->pm, pm_io_base); 484 485 new_gsi = ich9_lpc_sci_irq(lpc); 486 if (new_gsi == -1) { 487 return; 488 } 489 if (lpc->sci_level && new_gsi != lpc->sci_gsi) { 490 qemu_set_irq(lpc->pm.irq, 0); 491 lpc->sci_gsi = new_gsi; 492 qemu_set_irq(lpc->pm.irq, 1); 493 } 494 lpc->sci_gsi = new_gsi; 495 } 496 497 /* config:RCBA */ 498 static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rcba_old) 499 { 500 uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA); 501 502 if (rcba_old & ICH9_LPC_RCBA_EN) { 503 memory_region_del_subregion(get_system_memory(), &lpc->rcrb_mem); 504 } 505 if (rcba & ICH9_LPC_RCBA_EN) { 506 memory_region_add_subregion_overlap(get_system_memory(), 507 rcba & ICH9_LPC_RCBA_BA_MASK, 508 &lpc->rcrb_mem, 1); 509 } 510 } 511 512 /* config:GEN_PMCON* */ 513 static void 514 ich9_lpc_pmcon_update(ICH9LPCState *lpc) 515 { 516 uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1); 517 uint16_t wmask; 518 519 if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) { 520 wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1); 521 wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK; 522 pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask); 523 lpc->pm.smi_en_wmask &= ~1; 524 } 525 } 526 527 static int ich9_lpc_post_load(void *opaque, int version_id) 528 { 529 ICH9LPCState *lpc = opaque; 530 531 ich9_lpc_pmbase_sci_update(lpc); 532 ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RCBA_EN */); 533 ich9_lpc_pmcon_update(lpc); 534 return 0; 535 } 536 537 static void ich9_lpc_config_write(PCIDevice *d, 538 uint32_t addr, uint32_t val, int len) 539 { 540 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 541 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); 542 543 pci_default_write_config(d, addr, val, len); 544 if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4) || 545 ranges_overlap(addr, len, ICH9_LPC_ACPI_CTRL, 1)) { 546 ich9_lpc_pmbase_sci_update(lpc); 547 } 548 if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) { 549 ich9_lpc_rcba_update(lpc, rcba_old); 550 } 551 if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) { 552 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 553 } 554 if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) { 555 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 556 } 557 if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) { 558 ich9_lpc_pmcon_update(lpc); 559 } 560 } 561 562 static void ich9_lpc_reset(DeviceState *qdev) 563 { 564 PCIDevice *d = PCI_DEVICE(qdev); 565 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 566 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); 567 int i; 568 569 for (i = 0; i < 4; i++) { 570 pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i, 571 ICH9_LPC_PIRQ_ROUT_DEFAULT); 572 } 573 for (i = 0; i < 4; i++) { 574 pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i, 575 ICH9_LPC_PIRQ_ROUT_DEFAULT); 576 } 577 pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT); 578 579 pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT); 580 pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT); 581 582 ich9_cc_reset(lpc); 583 584 ich9_lpc_pmbase_sci_update(lpc); 585 ich9_lpc_rcba_update(lpc, rcba_old); 586 587 lpc->sci_level = 0; 588 lpc->rst_cnt = 0; 589 590 memset(lpc->smi_guest_features_le, 0, sizeof lpc->smi_guest_features_le); 591 lpc->smi_features_ok = 0; 592 lpc->smi_negotiated_features = 0; 593 } 594 595 /* root complex register block is mapped into memory space */ 596 static const MemoryRegionOps rcrb_mmio_ops = { 597 .read = ich9_cc_read, 598 .write = ich9_cc_write, 599 .endianness = DEVICE_LITTLE_ENDIAN, 600 }; 601 602 static void ich9_lpc_machine_ready(Notifier *n, void *opaque) 603 { 604 ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready); 605 MemoryRegion *io_as = pci_address_space_io(&s->d); 606 uint8_t *pci_conf; 607 608 pci_conf = s->d.config; 609 if (memory_region_present(io_as, 0x3f8)) { 610 /* com1 */ 611 pci_conf[0x82] |= 0x01; 612 } 613 if (memory_region_present(io_as, 0x2f8)) { 614 /* com2 */ 615 pci_conf[0x82] |= 0x02; 616 } 617 if (memory_region_present(io_as, 0x378)) { 618 /* lpt */ 619 pci_conf[0x82] |= 0x04; 620 } 621 if (memory_region_present(io_as, 0x3f2)) { 622 /* floppy */ 623 pci_conf[0x82] |= 0x08; 624 } 625 } 626 627 /* reset control */ 628 static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val, 629 unsigned len) 630 { 631 ICH9LPCState *lpc = opaque; 632 633 if (val & 4) { 634 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 635 return; 636 } 637 lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */ 638 } 639 640 static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len) 641 { 642 ICH9LPCState *lpc = opaque; 643 644 return lpc->rst_cnt; 645 } 646 647 static const MemoryRegionOps ich9_rst_cnt_ops = { 648 .read = ich9_rst_cnt_read, 649 .write = ich9_rst_cnt_write, 650 .endianness = DEVICE_LITTLE_ENDIAN 651 }; 652 653 static void ich9_lpc_initfn(Object *obj) 654 { 655 ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj); 656 657 static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE; 658 static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE; 659 660 object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT, 661 &lpc->sci_gsi, OBJ_PROP_FLAG_READ); 662 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD, 663 &acpi_enable_cmd, OBJ_PROP_FLAG_READ); 664 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD, 665 &acpi_disable_cmd, OBJ_PROP_FLAG_READ); 666 object_property_add_uint64_ptr(obj, ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, 667 &lpc->smi_negotiated_features, 668 OBJ_PROP_FLAG_READ); 669 670 ich9_pm_add_properties(obj, &lpc->pm); 671 } 672 673 static void ich9_lpc_realize(PCIDevice *d, Error **errp) 674 { 675 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 676 DeviceState *dev = DEVICE(d); 677 ISABus *isa_bus; 678 679 isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(), 680 errp); 681 if (!isa_bus) { 682 return; 683 } 684 685 pci_set_long(d->wmask + ICH9_LPC_PMBASE, 686 ICH9_LPC_PMBASE_BASE_ADDRESS_MASK); 687 pci_set_byte(d->wmask + ICH9_LPC_PMBASE, 688 ICH9_LPC_ACPI_CTRL_ACPI_EN | 689 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK); 690 691 memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc, 692 "lpc-rcrb-mmio", ICH9_CC_SIZE); 693 694 lpc->isa_bus = isa_bus; 695 696 ich9_cc_init(lpc); 697 apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc); 698 699 lpc->machine_ready.notify = ich9_lpc_machine_ready; 700 qemu_add_machine_init_done_notifier(&lpc->machine_ready); 701 702 memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc, 703 "lpc-reset-control", 1); 704 memory_region_add_subregion_overlap(pci_address_space_io(d), 705 ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem, 706 1); 707 708 qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS); 709 710 isa_bus_irqs(isa_bus, lpc->gsi); 711 } 712 713 static bool ich9_rst_cnt_needed(void *opaque) 714 { 715 ICH9LPCState *lpc = opaque; 716 717 return (lpc->rst_cnt != 0); 718 } 719 720 static const VMStateDescription vmstate_ich9_rst_cnt = { 721 .name = "ICH9LPC/rst_cnt", 722 .version_id = 1, 723 .minimum_version_id = 1, 724 .needed = ich9_rst_cnt_needed, 725 .fields = (VMStateField[]) { 726 VMSTATE_UINT8(rst_cnt, ICH9LPCState), 727 VMSTATE_END_OF_LIST() 728 } 729 }; 730 731 static bool ich9_smi_feat_needed(void *opaque) 732 { 733 ICH9LPCState *lpc = opaque; 734 735 return !buffer_is_zero(lpc->smi_guest_features_le, 736 sizeof lpc->smi_guest_features_le) || 737 lpc->smi_features_ok; 738 } 739 740 static const VMStateDescription vmstate_ich9_smi_feat = { 741 .name = "ICH9LPC/smi_feat", 742 .version_id = 1, 743 .minimum_version_id = 1, 744 .needed = ich9_smi_feat_needed, 745 .fields = (VMStateField[]) { 746 VMSTATE_UINT8_ARRAY(smi_guest_features_le, ICH9LPCState, 747 sizeof(uint64_t)), 748 VMSTATE_UINT8(smi_features_ok, ICH9LPCState), 749 VMSTATE_UINT64(smi_negotiated_features, ICH9LPCState), 750 VMSTATE_END_OF_LIST() 751 } 752 }; 753 754 static const VMStateDescription vmstate_ich9_lpc = { 755 .name = "ICH9LPC", 756 .version_id = 1, 757 .minimum_version_id = 1, 758 .post_load = ich9_lpc_post_load, 759 .fields = (VMStateField[]) { 760 VMSTATE_PCI_DEVICE(d, ICH9LPCState), 761 VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState), 762 VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs), 763 VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE), 764 VMSTATE_UINT32(sci_level, ICH9LPCState), 765 VMSTATE_END_OF_LIST() 766 }, 767 .subsections = (const VMStateDescription*[]) { 768 &vmstate_ich9_rst_cnt, 769 &vmstate_ich9_smi_feat, 770 NULL 771 } 772 }; 773 774 static Property ich9_lpc_properties[] = { 775 DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, true), 776 DEFINE_PROP_BOOL("smm-compat", ICH9LPCState, pm.smm_compat, false), 777 DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features, 778 ICH9_LPC_SMI_F_BROADCAST_BIT, true), 779 DEFINE_PROP_BIT64("x-smi-cpu-hotplug", ICH9LPCState, smi_host_features, 780 ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT, true), 781 DEFINE_PROP_BIT64("x-smi-cpu-hotunplug", ICH9LPCState, smi_host_features, 782 ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT, true), 783 DEFINE_PROP_END_OF_LIST(), 784 }; 785 786 static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) 787 { 788 ICH9LPCState *s = ICH9_LPC_DEVICE(adev); 789 790 acpi_send_gpe_event(&s->pm.acpi_regs, s->pm.irq, ev); 791 } 792 793 static void ich9_lpc_class_init(ObjectClass *klass, void *data) 794 { 795 DeviceClass *dc = DEVICE_CLASS(klass); 796 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 797 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 798 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 799 800 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 801 dc->reset = ich9_lpc_reset; 802 k->realize = ich9_lpc_realize; 803 dc->vmsd = &vmstate_ich9_lpc; 804 device_class_set_props(dc, ich9_lpc_properties); 805 k->config_write = ich9_lpc_config_write; 806 dc->desc = "ICH9 LPC bridge"; 807 k->vendor_id = PCI_VENDOR_ID_INTEL; 808 k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8; 809 k->revision = ICH9_A2_LPC_REVISION; 810 k->class_id = PCI_CLASS_BRIDGE_ISA; 811 /* 812 * Reason: part of ICH9 southbridge, needs to be wired up by 813 * pc_q35_init() 814 */ 815 dc->user_creatable = false; 816 hc->pre_plug = ich9_pm_device_pre_plug_cb; 817 hc->plug = ich9_pm_device_plug_cb; 818 hc->unplug_request = ich9_pm_device_unplug_request_cb; 819 hc->unplug = ich9_pm_device_unplug_cb; 820 adevc->ospm_status = ich9_pm_ospm_status; 821 adevc->send_event = ich9_send_gpe; 822 adevc->madt_cpu = pc_madt_cpu_entry; 823 } 824 825 static const TypeInfo ich9_lpc_info = { 826 .name = TYPE_ICH9_LPC_DEVICE, 827 .parent = TYPE_PCI_DEVICE, 828 .instance_size = sizeof(ICH9LPCState), 829 .instance_init = ich9_lpc_initfn, 830 .class_init = ich9_lpc_class_init, 831 .interfaces = (InterfaceInfo[]) { 832 { TYPE_HOTPLUG_HANDLER }, 833 { TYPE_ACPI_DEVICE_IF }, 834 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 835 { } 836 } 837 }; 838 839 static void ich9_lpc_register(void) 840 { 841 type_register_static(&ich9_lpc_info); 842 } 843 844 type_init(ich9_lpc_register); 845