1 /* 2 * QEMU ICH9 Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/log.h" 33 #include "cpu.h" 34 #include "qapi/error.h" 35 #include "qapi/visitor.h" 36 #include "qemu/range.h" 37 #include "hw/dma/i8257.h" 38 #include "hw/isa/isa.h" 39 #include "migration/vmstate.h" 40 #include "hw/irq.h" 41 #include "hw/isa/apm.h" 42 #include "hw/pci/pci.h" 43 #include "hw/southbridge/ich9.h" 44 #include "hw/i386/pc.h" 45 #include "hw/acpi/acpi.h" 46 #include "hw/acpi/ich9.h" 47 #include "hw/pci/pci_bus.h" 48 #include "hw/qdev-properties.h" 49 #include "sysemu/runstate.h" 50 #include "sysemu/sysemu.h" 51 #include "hw/core/cpu.h" 52 #include "hw/nvram/fw_cfg.h" 53 #include "qemu/cutils.h" 54 #include "hw/acpi/acpi_aml_interface.h" 55 #include "trace.h" 56 57 /*****************************************************************************/ 58 /* ICH9 LPC PCI to ISA bridge */ 59 60 /* chipset configuration register 61 * to access chipset configuration registers, pci_[sg]et_{byte, word, long} 62 * are used. 63 * Although it's not pci configuration space, it's little endian as Intel. 64 */ 65 66 static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir) 67 { 68 int intx; 69 for (intx = 0; intx < PCI_NUM_PINS; intx++) { 70 irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK; 71 } 72 } 73 74 static void ich9_cc_update(ICH9LPCState *lpc) 75 { 76 int slot; 77 int pci_intx; 78 79 const int reg_offsets[] = { 80 ICH9_CC_D25IR, 81 ICH9_CC_D26IR, 82 ICH9_CC_D27IR, 83 ICH9_CC_D28IR, 84 ICH9_CC_D29IR, 85 ICH9_CC_D30IR, 86 ICH9_CC_D31IR, 87 }; 88 const int *offset; 89 90 /* D{25 - 31}IR, but D30IR is read only to 0. */ 91 for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) { 92 if (slot == 30) { 93 continue; 94 } 95 ich9_cc_update_ir(lpc->irr[slot], 96 pci_get_word(lpc->chip_config + *offset)); 97 } 98 99 /* 100 * D30: DMI2PCI bridge 101 * It is arbitrarily decided how INTx lines of PCI devices behind 102 * the bridge are connected to pirq lines. Our choice is PIRQ[E-H]. 103 * INT[A-D] are connected to PIRQ[E-H] 104 */ 105 for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) { 106 lpc->irr[30][pci_intx] = pci_intx + 4; 107 } 108 } 109 110 static void ich9_cc_init(ICH9LPCState *lpc) 111 { 112 int slot; 113 int intx; 114 115 /* the default irq routing is arbitrary as long as it matches with 116 * acpi irq routing table. 117 * The one that is incompatible with piix_pci(= bochs) one is 118 * intentionally chosen to let the users know that the different 119 * board is used. 120 * 121 * int[A-D] -> pirq[E-F] 122 * avoid pirq A-D because they are used for pci express port 123 */ 124 for (slot = 0; slot < PCI_SLOT_MAX; slot++) { 125 for (intx = 0; intx < PCI_NUM_PINS; intx++) { 126 lpc->irr[slot][intx] = (slot + intx) % 4 + 4; 127 } 128 } 129 ich9_cc_update(lpc); 130 } 131 132 static void ich9_cc_reset(ICH9LPCState *lpc) 133 { 134 uint8_t *c = lpc->chip_config; 135 136 memset(lpc->chip_config, 0, sizeof(lpc->chip_config)); 137 138 pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT); 139 pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT); 140 pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT); 141 pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT); 142 pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT); 143 pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT); 144 pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT); 145 pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT); 146 147 ich9_cc_update(lpc); 148 } 149 150 static void ich9_cc_addr_len(uint64_t *addr, unsigned *len) 151 { 152 *addr &= ICH9_CC_ADDR_MASK; 153 if (*addr + *len >= ICH9_CC_SIZE) { 154 *len = ICH9_CC_SIZE - *addr; 155 } 156 } 157 158 /* val: little endian */ 159 static void ich9_cc_write(void *opaque, hwaddr addr, 160 uint64_t val, unsigned len) 161 { 162 ICH9LPCState *lpc = (ICH9LPCState *)opaque; 163 164 trace_ich9_cc_write(addr, val, len); 165 ich9_cc_addr_len(&addr, &len); 166 memcpy(lpc->chip_config + addr, &val, len); 167 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 168 ich9_cc_update(lpc); 169 } 170 171 /* return value: little endian */ 172 static uint64_t ich9_cc_read(void *opaque, hwaddr addr, 173 unsigned len) 174 { 175 ICH9LPCState *lpc = (ICH9LPCState *)opaque; 176 177 uint32_t val = 0; 178 ich9_cc_addr_len(&addr, &len); 179 memcpy(&val, lpc->chip_config + addr, len); 180 trace_ich9_cc_read(addr, val, len); 181 return val; 182 } 183 184 /* IRQ routing */ 185 /* */ 186 static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis) 187 { 188 *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK; 189 *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN; 190 } 191 192 static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num, 193 int *pic_irq, int *pic_dis) 194 { 195 switch (pirq_num) { 196 case 0 ... 3: /* A-D */ 197 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num], 198 pic_irq, pic_dis); 199 return; 200 case 4 ... 7: /* E-H */ 201 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)], 202 pic_irq, pic_dis); 203 return; 204 default: 205 break; 206 } 207 abort(); 208 } 209 210 /* gsi: i8259+ioapic irq 0-15, otherwise assert */ 211 static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi) 212 { 213 int i, pic_level; 214 215 assert(gsi < ICH9_LPC_PIC_NUM_PINS); 216 217 /* The pic level is the logical OR of all the PCI irqs mapped to it */ 218 pic_level = 0; 219 for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) { 220 int tmp_irq; 221 int tmp_dis; 222 ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis); 223 if (!tmp_dis && tmp_irq == gsi) { 224 pic_level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), i); 225 } 226 } 227 if (gsi == lpc->sci_gsi) { 228 pic_level |= lpc->sci_level; 229 } 230 231 qemu_set_irq(lpc->gsi[gsi], pic_level); 232 } 233 234 /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */ 235 static int ich9_pirq_to_gsi(int pirq) 236 { 237 return pirq + ICH9_LPC_PIC_NUM_PINS; 238 } 239 240 static int ich9_gsi_to_pirq(int gsi) 241 { 242 return gsi - ICH9_LPC_PIC_NUM_PINS; 243 } 244 245 /* gsi: ioapic irq 16-23, otherwise assert */ 246 static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi) 247 { 248 int level = 0; 249 250 assert(gsi >= ICH9_LPC_PIC_NUM_PINS); 251 252 level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), ich9_gsi_to_pirq(gsi)); 253 if (gsi == lpc->sci_gsi) { 254 level |= lpc->sci_level; 255 } 256 257 qemu_set_irq(lpc->gsi[gsi], level); 258 } 259 260 static void ich9_lpc_set_irq(void *opaque, int pirq, int level) 261 { 262 ICH9LPCState *lpc = opaque; 263 int pic_irq, pic_dis; 264 265 assert(0 <= pirq); 266 assert(pirq < ICH9_LPC_NB_PIRQS); 267 268 ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq)); 269 ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis); 270 ich9_lpc_update_pic(lpc, pic_irq); 271 } 272 273 /* return the pirq number (PIRQ[A-H]:0-7) corresponding to 274 * a given device irq pin. 275 */ 276 static int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) 277 { 278 BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); 279 PCIBus *pci_bus = PCI_BUS(bus); 280 PCIDevice *lpc_pdev = 281 pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)]; 282 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev); 283 284 return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; 285 } 286 287 static PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin) 288 { 289 ICH9LPCState *lpc = opaque; 290 PCIINTxRoute route; 291 int pic_irq; 292 int pic_dis; 293 294 assert(0 <= pirq_pin); 295 assert(pirq_pin < ICH9_LPC_NB_PIRQS); 296 297 route.mode = PCI_INTX_ENABLED; 298 ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis); 299 if (!pic_dis) { 300 if (pic_irq < ICH9_LPC_PIC_NUM_PINS) { 301 route.irq = pic_irq; 302 } else { 303 route.mode = PCI_INTX_DISABLED; 304 route.irq = -1; 305 } 306 } else { 307 route.irq = ich9_pirq_to_gsi(pirq_pin); 308 } 309 310 return route; 311 } 312 313 void ich9_generate_smi(void) 314 { 315 cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); 316 } 317 318 /* Returns -1 on error, IRQ number on success */ 319 static int ich9_lpc_sci_irq(ICH9LPCState *lpc) 320 { 321 uint8_t sel = lpc->d.config[ICH9_LPC_ACPI_CTRL] & 322 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK; 323 switch (sel) { 324 case ICH9_LPC_ACPI_CTRL_9: 325 return 9; 326 case ICH9_LPC_ACPI_CTRL_10: 327 return 10; 328 case ICH9_LPC_ACPI_CTRL_11: 329 return 11; 330 case ICH9_LPC_ACPI_CTRL_20: 331 return 20; 332 case ICH9_LPC_ACPI_CTRL_21: 333 return 21; 334 default: 335 /* reserved */ 336 qemu_log_mask(LOG_GUEST_ERROR, 337 "ICH9 LPC: SCI IRQ SEL #%u is reserved\n", sel); 338 break; 339 } 340 return -1; 341 } 342 343 static void ich9_set_sci(void *opaque, int irq_num, int level) 344 { 345 ICH9LPCState *lpc = opaque; 346 int irq; 347 348 assert(irq_num == 0); 349 level = !!level; 350 if (level == lpc->sci_level) { 351 return; 352 } 353 lpc->sci_level = level; 354 355 irq = lpc->sci_gsi; 356 if (irq < 0) { 357 return; 358 } 359 360 if (irq >= ICH9_LPC_PIC_NUM_PINS) { 361 ich9_lpc_update_apic(lpc, irq); 362 } else { 363 ich9_lpc_update_pic(lpc, irq); 364 } 365 } 366 367 static void smi_features_ok_callback(void *opaque) 368 { 369 ICH9LPCState *lpc = opaque; 370 uint64_t guest_features; 371 uint64_t guest_cpu_hotplug_features; 372 373 if (lpc->smi_features_ok) { 374 /* negotiation already complete, features locked */ 375 return; 376 } 377 378 memcpy(&guest_features, lpc->smi_guest_features_le, sizeof guest_features); 379 le64_to_cpus(&guest_features); 380 if (guest_features & ~lpc->smi_host_features) { 381 /* guest requests invalid features, leave @features_ok at zero */ 382 return; 383 } 384 385 guest_cpu_hotplug_features = guest_features & 386 (BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT) | 387 BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 388 if (!(guest_features & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT)) && 389 guest_cpu_hotplug_features) { 390 /* 391 * cpu hot-[un]plug with SMI requires SMI broadcast, 392 * leave @features_ok at zero 393 */ 394 return; 395 } 396 397 if (guest_cpu_hotplug_features == 398 BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) { 399 /* cpu hot-unplug is unsupported without cpu-hotplug */ 400 return; 401 } 402 403 /* valid feature subset requested, lock it down, report success */ 404 lpc->smi_negotiated_features = guest_features; 405 lpc->smi_features_ok = 1; 406 } 407 408 static void ich9_lpc_pm_init(ICH9LPCState *lpc) 409 { 410 qemu_irq sci_irq; 411 FWCfgState *fw_cfg = fw_cfg_find(); 412 413 sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0); 414 ich9_pm_init(PCI_DEVICE(lpc), &lpc->pm, sci_irq); 415 416 if (lpc->smi_host_features && fw_cfg) { 417 uint64_t host_features_le; 418 419 host_features_le = cpu_to_le64(lpc->smi_host_features); 420 memcpy(lpc->smi_host_features_le, &host_features_le, 421 sizeof host_features_le); 422 fw_cfg_add_file(fw_cfg, "etc/smi/supported-features", 423 lpc->smi_host_features_le, 424 sizeof lpc->smi_host_features_le); 425 426 /* The other two guest-visible fields are cleared on device reset, we 427 * just link them into fw_cfg here. 428 */ 429 fw_cfg_add_file_callback(fw_cfg, "etc/smi/requested-features", 430 NULL, NULL, NULL, 431 lpc->smi_guest_features_le, 432 sizeof lpc->smi_guest_features_le, 433 false); 434 fw_cfg_add_file_callback(fw_cfg, "etc/smi/features-ok", 435 smi_features_ok_callback, NULL, lpc, 436 &lpc->smi_features_ok, 437 sizeof lpc->smi_features_ok, 438 true); 439 } 440 } 441 442 /* APM */ 443 444 static void ich9_apm_ctrl_changed(uint32_t val, void *arg) 445 { 446 ICH9LPCState *lpc = arg; 447 448 /* ACPI specs 3.0, 4.7.2.5 */ 449 acpi_pm1_cnt_update(&lpc->pm.acpi_regs, 450 val == ICH9_APM_ACPI_ENABLE, 451 val == ICH9_APM_ACPI_DISABLE); 452 if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) { 453 return; 454 } 455 456 /* SMI_EN = PMBASE + 30. SMI control and enable register */ 457 if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { 458 if (lpc->smi_negotiated_features & 459 (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) { 460 CPUState *cs; 461 CPU_FOREACH(cs) { 462 cpu_interrupt(cs, CPU_INTERRUPT_SMI); 463 } 464 } else { 465 cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); 466 } 467 } 468 } 469 470 /* config:PMBASE */ 471 static void 472 ich9_lpc_pmbase_sci_update(ICH9LPCState *lpc) 473 { 474 uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE); 475 uint8_t acpi_cntl = pci_get_long(lpc->d.config + ICH9_LPC_ACPI_CTRL); 476 int new_gsi; 477 478 if (acpi_cntl & ICH9_LPC_ACPI_CTRL_ACPI_EN) { 479 pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK; 480 } else { 481 pm_io_base = 0; 482 } 483 484 ich9_pm_iospace_update(&lpc->pm, pm_io_base); 485 486 new_gsi = ich9_lpc_sci_irq(lpc); 487 if (new_gsi == -1) { 488 return; 489 } 490 if (lpc->sci_level && new_gsi != lpc->sci_gsi) { 491 qemu_set_irq(lpc->pm.irq, 0); 492 lpc->sci_gsi = new_gsi; 493 qemu_set_irq(lpc->pm.irq, 1); 494 } 495 lpc->sci_gsi = new_gsi; 496 } 497 498 /* config:RCBA */ 499 static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rcba_old) 500 { 501 uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA); 502 503 if (rcba_old & ICH9_LPC_RCBA_EN) { 504 memory_region_del_subregion(get_system_memory(), &lpc->rcrb_mem); 505 } 506 if (rcba & ICH9_LPC_RCBA_EN) { 507 memory_region_add_subregion_overlap(get_system_memory(), 508 rcba & ICH9_LPC_RCBA_BA_MASK, 509 &lpc->rcrb_mem, 1); 510 } 511 } 512 513 /* config:GEN_PMCON* */ 514 static void 515 ich9_lpc_pmcon_update(ICH9LPCState *lpc) 516 { 517 uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1); 518 uint16_t wmask; 519 520 if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) { 521 wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1); 522 wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK; 523 pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask); 524 lpc->pm.smi_en_wmask &= ~1; 525 } 526 } 527 528 static int ich9_lpc_post_load(void *opaque, int version_id) 529 { 530 ICH9LPCState *lpc = opaque; 531 532 ich9_lpc_pmbase_sci_update(lpc); 533 ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RCBA_EN */); 534 ich9_lpc_pmcon_update(lpc); 535 return 0; 536 } 537 538 static void ich9_lpc_config_write(PCIDevice *d, 539 uint32_t addr, uint32_t val, int len) 540 { 541 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 542 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); 543 544 pci_default_write_config(d, addr, val, len); 545 if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4) || 546 ranges_overlap(addr, len, ICH9_LPC_ACPI_CTRL, 1)) { 547 ich9_lpc_pmbase_sci_update(lpc); 548 } 549 if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) { 550 ich9_lpc_rcba_update(lpc, rcba_old); 551 } 552 if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) { 553 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 554 } 555 if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) { 556 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 557 } 558 if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) { 559 ich9_lpc_pmcon_update(lpc); 560 } 561 } 562 563 static void ich9_lpc_reset(DeviceState *qdev) 564 { 565 PCIDevice *d = PCI_DEVICE(qdev); 566 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 567 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); 568 int i; 569 570 for (i = 0; i < 4; i++) { 571 pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i, 572 ICH9_LPC_PIRQ_ROUT_DEFAULT); 573 } 574 for (i = 0; i < 4; i++) { 575 pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i, 576 ICH9_LPC_PIRQ_ROUT_DEFAULT); 577 } 578 pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT); 579 580 pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT); 581 pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT); 582 583 ich9_cc_reset(lpc); 584 585 ich9_lpc_pmbase_sci_update(lpc); 586 ich9_lpc_rcba_update(lpc, rcba_old); 587 588 lpc->sci_level = 0; 589 lpc->rst_cnt = 0; 590 591 memset(lpc->smi_guest_features_le, 0, sizeof lpc->smi_guest_features_le); 592 lpc->smi_features_ok = 0; 593 lpc->smi_negotiated_features = 0; 594 } 595 596 /* root complex register block is mapped into memory space */ 597 static const MemoryRegionOps rcrb_mmio_ops = { 598 .read = ich9_cc_read, 599 .write = ich9_cc_write, 600 .endianness = DEVICE_LITTLE_ENDIAN, 601 }; 602 603 static void ich9_lpc_machine_ready(Notifier *n, void *opaque) 604 { 605 ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready); 606 MemoryRegion *io_as = pci_address_space_io(&s->d); 607 uint8_t *pci_conf; 608 609 pci_conf = s->d.config; 610 if (memory_region_present(io_as, 0x3f8)) { 611 /* com1 */ 612 pci_conf[0x82] |= 0x01; 613 } 614 if (memory_region_present(io_as, 0x2f8)) { 615 /* com2 */ 616 pci_conf[0x82] |= 0x02; 617 } 618 if (memory_region_present(io_as, 0x378)) { 619 /* lpt */ 620 pci_conf[0x82] |= 0x04; 621 } 622 if (memory_region_present(io_as, 0x3f2)) { 623 /* floppy */ 624 pci_conf[0x82] |= 0x08; 625 } 626 } 627 628 /* reset control */ 629 static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val, 630 unsigned len) 631 { 632 ICH9LPCState *lpc = opaque; 633 634 if (val & 4) { 635 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 636 return; 637 } 638 lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */ 639 } 640 641 static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len) 642 { 643 ICH9LPCState *lpc = opaque; 644 645 return lpc->rst_cnt; 646 } 647 648 static const MemoryRegionOps ich9_rst_cnt_ops = { 649 .read = ich9_rst_cnt_read, 650 .write = ich9_rst_cnt_write, 651 .endianness = DEVICE_LITTLE_ENDIAN 652 }; 653 654 static void ich9_lpc_initfn(Object *obj) 655 { 656 ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj); 657 658 static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE; 659 static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE; 660 661 object_initialize_child(obj, "rtc", &lpc->rtc, TYPE_MC146818_RTC); 662 663 object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT, 664 &lpc->sci_gsi, OBJ_PROP_FLAG_READ); 665 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD, 666 &acpi_enable_cmd, OBJ_PROP_FLAG_READ); 667 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD, 668 &acpi_disable_cmd, OBJ_PROP_FLAG_READ); 669 object_property_add_uint64_ptr(obj, ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, 670 &lpc->smi_negotiated_features, 671 OBJ_PROP_FLAG_READ); 672 673 ich9_pm_add_properties(obj, &lpc->pm); 674 } 675 676 static void ich9_lpc_realize(PCIDevice *d, Error **errp) 677 { 678 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 679 DeviceState *dev = DEVICE(d); 680 PCIBus *pci_bus = pci_get_bus(d); 681 ISABus *isa_bus; 682 683 if ((lpc->smi_host_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) && 684 !(lpc->smi_host_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT))) { 685 /* 686 * smi_features_ok_callback() throws an error on this. 687 * 688 * So bail out here instead of advertizing the invalid 689 * configuration and get obscure firmware failures from that. 690 */ 691 error_setg(errp, "cpu hot-unplug requires cpu hot-plug"); 692 return; 693 } 694 695 isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(), 696 errp); 697 if (!isa_bus) { 698 return; 699 } 700 701 pci_set_long(d->wmask + ICH9_LPC_PMBASE, 702 ICH9_LPC_PMBASE_BASE_ADDRESS_MASK); 703 pci_set_byte(d->wmask + ICH9_LPC_PMBASE, 704 ICH9_LPC_ACPI_CTRL_ACPI_EN | 705 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK); 706 707 memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc, 708 "lpc-rcrb-mmio", ICH9_CC_SIZE); 709 710 ich9_cc_init(lpc); 711 apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc); 712 713 lpc->machine_ready.notify = ich9_lpc_machine_ready; 714 qemu_add_machine_init_done_notifier(&lpc->machine_ready); 715 716 memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc, 717 "lpc-reset-control", 1); 718 memory_region_add_subregion_overlap(pci_address_space_io(d), 719 ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem, 720 1); 721 722 qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, IOAPIC_NUM_PINS); 723 724 isa_bus_register_input_irqs(isa_bus, lpc->gsi); 725 726 i8257_dma_init(isa_bus, 0); 727 728 /* RTC */ 729 qdev_prop_set_int32(DEVICE(&lpc->rtc), "base_year", 2000); 730 if (!qdev_realize(DEVICE(&lpc->rtc), BUS(isa_bus), errp)) { 731 return; 732 } 733 734 pci_bus_irqs(pci_bus, ich9_lpc_set_irq, d, ICH9_LPC_NB_PIRQS); 735 pci_bus_map_irqs(pci_bus, ich9_lpc_map_irq); 736 pci_bus_set_route_irq_fn(pci_bus, ich9_route_intx_pin_to_irq); 737 738 ich9_lpc_pm_init(lpc); 739 } 740 741 static bool ich9_rst_cnt_needed(void *opaque) 742 { 743 ICH9LPCState *lpc = opaque; 744 745 return (lpc->rst_cnt != 0); 746 } 747 748 static const VMStateDescription vmstate_ich9_rst_cnt = { 749 .name = "ICH9LPC/rst_cnt", 750 .version_id = 1, 751 .minimum_version_id = 1, 752 .needed = ich9_rst_cnt_needed, 753 .fields = (VMStateField[]) { 754 VMSTATE_UINT8(rst_cnt, ICH9LPCState), 755 VMSTATE_END_OF_LIST() 756 } 757 }; 758 759 static bool ich9_smi_feat_needed(void *opaque) 760 { 761 ICH9LPCState *lpc = opaque; 762 763 return !buffer_is_zero(lpc->smi_guest_features_le, 764 sizeof lpc->smi_guest_features_le) || 765 lpc->smi_features_ok; 766 } 767 768 static const VMStateDescription vmstate_ich9_smi_feat = { 769 .name = "ICH9LPC/smi_feat", 770 .version_id = 1, 771 .minimum_version_id = 1, 772 .needed = ich9_smi_feat_needed, 773 .fields = (VMStateField[]) { 774 VMSTATE_UINT8_ARRAY(smi_guest_features_le, ICH9LPCState, 775 sizeof(uint64_t)), 776 VMSTATE_UINT8(smi_features_ok, ICH9LPCState), 777 VMSTATE_UINT64(smi_negotiated_features, ICH9LPCState), 778 VMSTATE_END_OF_LIST() 779 } 780 }; 781 782 static const VMStateDescription vmstate_ich9_lpc = { 783 .name = "ICH9LPC", 784 .version_id = 1, 785 .minimum_version_id = 1, 786 .post_load = ich9_lpc_post_load, 787 .fields = (VMStateField[]) { 788 VMSTATE_PCI_DEVICE(d, ICH9LPCState), 789 VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState), 790 VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs), 791 VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE), 792 VMSTATE_UINT32(sci_level, ICH9LPCState), 793 VMSTATE_END_OF_LIST() 794 }, 795 .subsections = (const VMStateDescription*[]) { 796 &vmstate_ich9_rst_cnt, 797 &vmstate_ich9_smi_feat, 798 NULL 799 } 800 }; 801 802 static Property ich9_lpc_properties[] = { 803 DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, false), 804 DEFINE_PROP_BOOL("smm-compat", ICH9LPCState, pm.smm_compat, false), 805 DEFINE_PROP_BOOL("smm-enabled", ICH9LPCState, pm.smm_enabled, false), 806 DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features, 807 ICH9_LPC_SMI_F_BROADCAST_BIT, true), 808 DEFINE_PROP_BIT64("x-smi-cpu-hotplug", ICH9LPCState, smi_host_features, 809 ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT, true), 810 DEFINE_PROP_BIT64("x-smi-cpu-hotunplug", ICH9LPCState, smi_host_features, 811 ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT, true), 812 DEFINE_PROP_END_OF_LIST(), 813 }; 814 815 static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) 816 { 817 ICH9LPCState *s = ICH9_LPC_DEVICE(adev); 818 819 acpi_send_gpe_event(&s->pm.acpi_regs, s->pm.irq, ev); 820 } 821 822 static void build_ich9_isa_aml(AcpiDevAmlIf *adev, Aml *scope) 823 { 824 Aml *field; 825 BusState *bus = qdev_get_child_bus(DEVICE(adev), "isa.0"); 826 Aml *sb_scope = aml_scope("\\_SB"); 827 828 /* ICH9 PCI to ISA irq remapping */ 829 aml_append(scope, aml_operation_region("PIRQ", AML_PCI_CONFIG, 830 aml_int(0x60), 0x0C)); 831 /* Fields declarion has to happen *after* operation region */ 832 field = aml_field("PCI0.SF8.PIRQ", AML_BYTE_ACC, AML_NOLOCK, AML_PRESERVE); 833 aml_append(field, aml_named_field("PRQA", 8)); 834 aml_append(field, aml_named_field("PRQB", 8)); 835 aml_append(field, aml_named_field("PRQC", 8)); 836 aml_append(field, aml_named_field("PRQD", 8)); 837 aml_append(field, aml_reserved_field(0x20)); 838 aml_append(field, aml_named_field("PRQE", 8)); 839 aml_append(field, aml_named_field("PRQF", 8)); 840 aml_append(field, aml_named_field("PRQG", 8)); 841 aml_append(field, aml_named_field("PRQH", 8)); 842 aml_append(sb_scope, field); 843 aml_append(scope, sb_scope); 844 845 qbus_build_aml(bus, scope); 846 } 847 848 static void ich9_lpc_class_init(ObjectClass *klass, void *data) 849 { 850 DeviceClass *dc = DEVICE_CLASS(klass); 851 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 852 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 853 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 854 AcpiDevAmlIfClass *amldevc = ACPI_DEV_AML_IF_CLASS(klass); 855 856 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 857 dc->reset = ich9_lpc_reset; 858 k->realize = ich9_lpc_realize; 859 dc->vmsd = &vmstate_ich9_lpc; 860 device_class_set_props(dc, ich9_lpc_properties); 861 k->config_write = ich9_lpc_config_write; 862 dc->desc = "ICH9 LPC bridge"; 863 k->vendor_id = PCI_VENDOR_ID_INTEL; 864 k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8; 865 k->revision = ICH9_A2_LPC_REVISION; 866 k->class_id = PCI_CLASS_BRIDGE_ISA; 867 /* 868 * Reason: part of ICH9 southbridge, needs to be wired up by 869 * pc_q35_init() 870 */ 871 dc->user_creatable = false; 872 hc->pre_plug = ich9_pm_device_pre_plug_cb; 873 hc->plug = ich9_pm_device_plug_cb; 874 hc->unplug_request = ich9_pm_device_unplug_request_cb; 875 hc->unplug = ich9_pm_device_unplug_cb; 876 hc->is_hotpluggable_bus = ich9_pm_is_hotpluggable_bus; 877 adevc->ospm_status = ich9_pm_ospm_status; 878 adevc->send_event = ich9_send_gpe; 879 adevc->madt_cpu = pc_madt_cpu_entry; 880 amldevc->build_dev_aml = build_ich9_isa_aml; 881 } 882 883 static const TypeInfo ich9_lpc_info = { 884 .name = TYPE_ICH9_LPC_DEVICE, 885 .parent = TYPE_PCI_DEVICE, 886 .instance_size = sizeof(ICH9LPCState), 887 .instance_init = ich9_lpc_initfn, 888 .class_init = ich9_lpc_class_init, 889 .interfaces = (InterfaceInfo[]) { 890 { TYPE_HOTPLUG_HANDLER }, 891 { TYPE_ACPI_DEVICE_IF }, 892 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 893 { TYPE_ACPI_DEV_AML_IF }, 894 { } 895 } 896 }; 897 898 static void ich9_lpc_register(void) 899 { 900 type_register_static(&ich9_lpc_info); 901 } 902 903 type_init(ich9_lpc_register); 904