1 /* 2 * QEMU ICH9 Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/log.h" 33 #include "cpu.h" 34 #include "qapi/visitor.h" 35 #include "qemu/range.h" 36 #include "hw/isa/isa.h" 37 #include "hw/sysbus.h" 38 #include "migration/vmstate.h" 39 #include "hw/irq.h" 40 #include "hw/isa/apm.h" 41 #include "hw/pci/pci.h" 42 #include "hw/pci/pci_bridge.h" 43 #include "hw/i386/ich9.h" 44 #include "hw/acpi/acpi.h" 45 #include "hw/acpi/ich9.h" 46 #include "hw/pci/pci_bus.h" 47 #include "hw/qdev-properties.h" 48 #include "exec/address-spaces.h" 49 #include "sysemu/runstate.h" 50 #include "sysemu/sysemu.h" 51 #include "hw/core/cpu.h" 52 #include "hw/nvram/fw_cfg.h" 53 #include "qemu/cutils.h" 54 55 /*****************************************************************************/ 56 /* ICH9 LPC PCI to ISA bridge */ 57 58 static void ich9_lpc_reset(DeviceState *qdev); 59 60 /* chipset configuration register 61 * to access chipset configuration registers, pci_[sg]et_{byte, word, long} 62 * are used. 63 * Although it's not pci configuration space, it's little endian as Intel. 64 */ 65 66 static void ich9_cc_update_ir(uint8_t irr[PCI_NUM_PINS], uint16_t ir) 67 { 68 int intx; 69 for (intx = 0; intx < PCI_NUM_PINS; intx++) { 70 irr[intx] = (ir >> (intx * ICH9_CC_DIR_SHIFT)) & ICH9_CC_DIR_MASK; 71 } 72 } 73 74 static void ich9_cc_update(ICH9LPCState *lpc) 75 { 76 int slot; 77 int pci_intx; 78 79 const int reg_offsets[] = { 80 ICH9_CC_D25IR, 81 ICH9_CC_D26IR, 82 ICH9_CC_D27IR, 83 ICH9_CC_D28IR, 84 ICH9_CC_D29IR, 85 ICH9_CC_D30IR, 86 ICH9_CC_D31IR, 87 }; 88 const int *offset; 89 90 /* D{25 - 31}IR, but D30IR is read only to 0. */ 91 for (slot = 25, offset = reg_offsets; slot < 32; slot++, offset++) { 92 if (slot == 30) { 93 continue; 94 } 95 ich9_cc_update_ir(lpc->irr[slot], 96 pci_get_word(lpc->chip_config + *offset)); 97 } 98 99 /* 100 * D30: DMI2PCI bridge 101 * It is arbitrarily decided how INTx lines of PCI devices behind 102 * the bridge are connected to pirq lines. Our choice is PIRQ[E-H]. 103 * INT[A-D] are connected to PIRQ[E-H] 104 */ 105 for (pci_intx = 0; pci_intx < PCI_NUM_PINS; pci_intx++) { 106 lpc->irr[30][pci_intx] = pci_intx + 4; 107 } 108 } 109 110 static void ich9_cc_init(ICH9LPCState *lpc) 111 { 112 int slot; 113 int intx; 114 115 /* the default irq routing is arbitrary as long as it matches with 116 * acpi irq routing table. 117 * The one that is incompatible with piix_pci(= bochs) one is 118 * intentionally chosen to let the users know that the different 119 * board is used. 120 * 121 * int[A-D] -> pirq[E-F] 122 * avoid pirq A-D because they are used for pci express port 123 */ 124 for (slot = 0; slot < PCI_SLOT_MAX; slot++) { 125 for (intx = 0; intx < PCI_NUM_PINS; intx++) { 126 lpc->irr[slot][intx] = (slot + intx) % 4 + 4; 127 } 128 } 129 ich9_cc_update(lpc); 130 } 131 132 static void ich9_cc_reset(ICH9LPCState *lpc) 133 { 134 uint8_t *c = lpc->chip_config; 135 136 memset(lpc->chip_config, 0, sizeof(lpc->chip_config)); 137 138 pci_set_long(c + ICH9_CC_D31IR, ICH9_CC_DIR_DEFAULT); 139 pci_set_long(c + ICH9_CC_D30IR, ICH9_CC_D30IR_DEFAULT); 140 pci_set_long(c + ICH9_CC_D29IR, ICH9_CC_DIR_DEFAULT); 141 pci_set_long(c + ICH9_CC_D28IR, ICH9_CC_DIR_DEFAULT); 142 pci_set_long(c + ICH9_CC_D27IR, ICH9_CC_DIR_DEFAULT); 143 pci_set_long(c + ICH9_CC_D26IR, ICH9_CC_DIR_DEFAULT); 144 pci_set_long(c + ICH9_CC_D25IR, ICH9_CC_DIR_DEFAULT); 145 pci_set_long(c + ICH9_CC_GCS, ICH9_CC_GCS_DEFAULT); 146 147 ich9_cc_update(lpc); 148 } 149 150 static void ich9_cc_addr_len(uint64_t *addr, unsigned *len) 151 { 152 *addr &= ICH9_CC_ADDR_MASK; 153 if (*addr + *len >= ICH9_CC_SIZE) { 154 *len = ICH9_CC_SIZE - *addr; 155 } 156 } 157 158 /* val: little endian */ 159 static void ich9_cc_write(void *opaque, hwaddr addr, 160 uint64_t val, unsigned len) 161 { 162 ICH9LPCState *lpc = (ICH9LPCState *)opaque; 163 164 ich9_cc_addr_len(&addr, &len); 165 memcpy(lpc->chip_config + addr, &val, len); 166 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 167 ich9_cc_update(lpc); 168 } 169 170 /* return value: little endian */ 171 static uint64_t ich9_cc_read(void *opaque, hwaddr addr, 172 unsigned len) 173 { 174 ICH9LPCState *lpc = (ICH9LPCState *)opaque; 175 176 uint32_t val = 0; 177 ich9_cc_addr_len(&addr, &len); 178 memcpy(&val, lpc->chip_config + addr, len); 179 return val; 180 } 181 182 /* IRQ routing */ 183 /* */ 184 static void ich9_lpc_rout(uint8_t pirq_rout, int *pic_irq, int *pic_dis) 185 { 186 *pic_irq = pirq_rout & ICH9_LPC_PIRQ_ROUT_MASK; 187 *pic_dis = pirq_rout & ICH9_LPC_PIRQ_ROUT_IRQEN; 188 } 189 190 static void ich9_lpc_pic_irq(ICH9LPCState *lpc, int pirq_num, 191 int *pic_irq, int *pic_dis) 192 { 193 switch (pirq_num) { 194 case 0 ... 3: /* A-D */ 195 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQA_ROUT + pirq_num], 196 pic_irq, pic_dis); 197 return; 198 case 4 ... 7: /* E-H */ 199 ich9_lpc_rout(lpc->d.config[ICH9_LPC_PIRQE_ROUT + (pirq_num - 4)], 200 pic_irq, pic_dis); 201 return; 202 default: 203 break; 204 } 205 abort(); 206 } 207 208 /* gsi: i8259+ioapic irq 0-15, otherwise assert */ 209 static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi) 210 { 211 int i, pic_level; 212 213 assert(gsi < ICH9_LPC_PIC_NUM_PINS); 214 215 /* The pic level is the logical OR of all the PCI irqs mapped to it */ 216 pic_level = 0; 217 for (i = 0; i < ICH9_LPC_NB_PIRQS; i++) { 218 int tmp_irq; 219 int tmp_dis; 220 ich9_lpc_pic_irq(lpc, i, &tmp_irq, &tmp_dis); 221 if (!tmp_dis && tmp_irq == gsi) { 222 pic_level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), i); 223 } 224 } 225 if (gsi == lpc->sci_gsi) { 226 pic_level |= lpc->sci_level; 227 } 228 229 qemu_set_irq(lpc->gsi[gsi], pic_level); 230 } 231 232 /* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */ 233 static int ich9_pirq_to_gsi(int pirq) 234 { 235 return pirq + ICH9_LPC_PIC_NUM_PINS; 236 } 237 238 static int ich9_gsi_to_pirq(int gsi) 239 { 240 return gsi - ICH9_LPC_PIC_NUM_PINS; 241 } 242 243 /* gsi: ioapic irq 16-23, otherwise assert */ 244 static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi) 245 { 246 int level = 0; 247 248 assert(gsi >= ICH9_LPC_PIC_NUM_PINS); 249 250 level |= pci_bus_get_irq_level(pci_get_bus(&lpc->d), ich9_gsi_to_pirq(gsi)); 251 if (gsi == lpc->sci_gsi) { 252 level |= lpc->sci_level; 253 } 254 255 qemu_set_irq(lpc->gsi[gsi], level); 256 } 257 258 void ich9_lpc_set_irq(void *opaque, int pirq, int level) 259 { 260 ICH9LPCState *lpc = opaque; 261 int pic_irq, pic_dis; 262 263 assert(0 <= pirq); 264 assert(pirq < ICH9_LPC_NB_PIRQS); 265 266 ich9_lpc_update_apic(lpc, ich9_pirq_to_gsi(pirq)); 267 ich9_lpc_pic_irq(lpc, pirq, &pic_irq, &pic_dis); 268 ich9_lpc_update_pic(lpc, pic_irq); 269 } 270 271 /* return the pirq number (PIRQ[A-H]:0-7) corresponding to 272 * a given device irq pin. 273 */ 274 int ich9_lpc_map_irq(PCIDevice *pci_dev, int intx) 275 { 276 BusState *bus = qdev_get_parent_bus(&pci_dev->qdev); 277 PCIBus *pci_bus = PCI_BUS(bus); 278 PCIDevice *lpc_pdev = 279 pci_bus->devices[PCI_DEVFN(ICH9_LPC_DEV, ICH9_LPC_FUNC)]; 280 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pdev); 281 282 return lpc->irr[PCI_SLOT(pci_dev->devfn)][intx]; 283 } 284 285 PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin) 286 { 287 ICH9LPCState *lpc = opaque; 288 PCIINTxRoute route; 289 int pic_irq; 290 int pic_dis; 291 292 assert(0 <= pirq_pin); 293 assert(pirq_pin < ICH9_LPC_NB_PIRQS); 294 295 route.mode = PCI_INTX_ENABLED; 296 ich9_lpc_pic_irq(lpc, pirq_pin, &pic_irq, &pic_dis); 297 if (!pic_dis) { 298 if (pic_irq < ICH9_LPC_PIC_NUM_PINS) { 299 route.irq = pic_irq; 300 } else { 301 route.mode = PCI_INTX_DISABLED; 302 route.irq = -1; 303 } 304 } else { 305 route.irq = ich9_pirq_to_gsi(pirq_pin); 306 } 307 308 return route; 309 } 310 311 void ich9_generate_smi(void) 312 { 313 cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); 314 } 315 316 /* Returns -1 on error, IRQ number on success */ 317 static int ich9_lpc_sci_irq(ICH9LPCState *lpc) 318 { 319 uint8_t sel = lpc->d.config[ICH9_LPC_ACPI_CTRL] & 320 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK; 321 switch (sel) { 322 case ICH9_LPC_ACPI_CTRL_9: 323 return 9; 324 case ICH9_LPC_ACPI_CTRL_10: 325 return 10; 326 case ICH9_LPC_ACPI_CTRL_11: 327 return 11; 328 case ICH9_LPC_ACPI_CTRL_20: 329 return 20; 330 case ICH9_LPC_ACPI_CTRL_21: 331 return 21; 332 default: 333 /* reserved */ 334 qemu_log_mask(LOG_GUEST_ERROR, 335 "ICH9 LPC: SCI IRQ SEL #%u is reserved\n", sel); 336 break; 337 } 338 return -1; 339 } 340 341 static void ich9_set_sci(void *opaque, int irq_num, int level) 342 { 343 ICH9LPCState *lpc = opaque; 344 int irq; 345 346 assert(irq_num == 0); 347 level = !!level; 348 if (level == lpc->sci_level) { 349 return; 350 } 351 lpc->sci_level = level; 352 353 irq = lpc->sci_gsi; 354 if (irq < 0) { 355 return; 356 } 357 358 if (irq >= ICH9_LPC_PIC_NUM_PINS) { 359 ich9_lpc_update_apic(lpc, irq); 360 } else { 361 ich9_lpc_update_pic(lpc, irq); 362 } 363 } 364 365 static void smi_features_ok_callback(void *opaque) 366 { 367 ICH9LPCState *lpc = opaque; 368 uint64_t guest_features; 369 uint64_t guest_cpu_hotplug_features; 370 371 if (lpc->smi_features_ok) { 372 /* negotiation already complete, features locked */ 373 return; 374 } 375 376 memcpy(&guest_features, lpc->smi_guest_features_le, sizeof guest_features); 377 le64_to_cpus(&guest_features); 378 if (guest_features & ~lpc->smi_host_features) { 379 /* guest requests invalid features, leave @features_ok at zero */ 380 return; 381 } 382 383 guest_cpu_hotplug_features = guest_features & 384 (BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT) | 385 BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)); 386 if (!(guest_features & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT)) && 387 guest_cpu_hotplug_features) { 388 /* 389 * cpu hot-[un]plug with SMI requires SMI broadcast, 390 * leave @features_ok at zero 391 */ 392 return; 393 } 394 395 if (guest_cpu_hotplug_features == 396 BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT)) { 397 /* cpu hot-unplug is unsupported without cpu-hotplug */ 398 return; 399 } 400 401 /* valid feature subset requested, lock it down, report success */ 402 lpc->smi_negotiated_features = guest_features; 403 lpc->smi_features_ok = 1; 404 } 405 406 void ich9_lpc_pm_init(PCIDevice *lpc_pci, bool smm_enabled) 407 { 408 ICH9LPCState *lpc = ICH9_LPC_DEVICE(lpc_pci); 409 qemu_irq sci_irq; 410 FWCfgState *fw_cfg = fw_cfg_find(); 411 412 sci_irq = qemu_allocate_irq(ich9_set_sci, lpc, 0); 413 ich9_pm_init(lpc_pci, &lpc->pm, smm_enabled, sci_irq); 414 415 if (lpc->smi_host_features && fw_cfg) { 416 uint64_t host_features_le; 417 418 host_features_le = cpu_to_le64(lpc->smi_host_features); 419 memcpy(lpc->smi_host_features_le, &host_features_le, 420 sizeof host_features_le); 421 fw_cfg_add_file(fw_cfg, "etc/smi/supported-features", 422 lpc->smi_host_features_le, 423 sizeof lpc->smi_host_features_le); 424 425 /* The other two guest-visible fields are cleared on device reset, we 426 * just link them into fw_cfg here. 427 */ 428 fw_cfg_add_file_callback(fw_cfg, "etc/smi/requested-features", 429 NULL, NULL, NULL, 430 lpc->smi_guest_features_le, 431 sizeof lpc->smi_guest_features_le, 432 false); 433 fw_cfg_add_file_callback(fw_cfg, "etc/smi/features-ok", 434 smi_features_ok_callback, NULL, lpc, 435 &lpc->smi_features_ok, 436 sizeof lpc->smi_features_ok, 437 true); 438 } 439 440 ich9_lpc_reset(DEVICE(lpc)); 441 } 442 443 /* APM */ 444 445 static void ich9_apm_ctrl_changed(uint32_t val, void *arg) 446 { 447 ICH9LPCState *lpc = arg; 448 449 /* ACPI specs 3.0, 4.7.2.5 */ 450 acpi_pm1_cnt_update(&lpc->pm.acpi_regs, 451 val == ICH9_APM_ACPI_ENABLE, 452 val == ICH9_APM_ACPI_DISABLE); 453 if (val == ICH9_APM_ACPI_ENABLE || val == ICH9_APM_ACPI_DISABLE) { 454 return; 455 } 456 457 /* SMI_EN = PMBASE + 30. SMI control and enable register */ 458 if (lpc->pm.smi_en & ICH9_PMIO_SMI_EN_APMC_EN) { 459 if (lpc->smi_negotiated_features & 460 (UINT64_C(1) << ICH9_LPC_SMI_F_BROADCAST_BIT)) { 461 CPUState *cs; 462 CPU_FOREACH(cs) { 463 cpu_interrupt(cs, CPU_INTERRUPT_SMI); 464 } 465 } else { 466 cpu_interrupt(current_cpu, CPU_INTERRUPT_SMI); 467 } 468 } 469 } 470 471 /* config:PMBASE */ 472 static void 473 ich9_lpc_pmbase_sci_update(ICH9LPCState *lpc) 474 { 475 uint32_t pm_io_base = pci_get_long(lpc->d.config + ICH9_LPC_PMBASE); 476 uint8_t acpi_cntl = pci_get_long(lpc->d.config + ICH9_LPC_ACPI_CTRL); 477 int new_gsi; 478 479 if (acpi_cntl & ICH9_LPC_ACPI_CTRL_ACPI_EN) { 480 pm_io_base &= ICH9_LPC_PMBASE_BASE_ADDRESS_MASK; 481 } else { 482 pm_io_base = 0; 483 } 484 485 ich9_pm_iospace_update(&lpc->pm, pm_io_base); 486 487 new_gsi = ich9_lpc_sci_irq(lpc); 488 if (new_gsi == -1) { 489 return; 490 } 491 if (lpc->sci_level && new_gsi != lpc->sci_gsi) { 492 qemu_set_irq(lpc->pm.irq, 0); 493 lpc->sci_gsi = new_gsi; 494 qemu_set_irq(lpc->pm.irq, 1); 495 } 496 lpc->sci_gsi = new_gsi; 497 } 498 499 /* config:RCBA */ 500 static void ich9_lpc_rcba_update(ICH9LPCState *lpc, uint32_t rcba_old) 501 { 502 uint32_t rcba = pci_get_long(lpc->d.config + ICH9_LPC_RCBA); 503 504 if (rcba_old & ICH9_LPC_RCBA_EN) { 505 memory_region_del_subregion(get_system_memory(), &lpc->rcrb_mem); 506 } 507 if (rcba & ICH9_LPC_RCBA_EN) { 508 memory_region_add_subregion_overlap(get_system_memory(), 509 rcba & ICH9_LPC_RCBA_BA_MASK, 510 &lpc->rcrb_mem, 1); 511 } 512 } 513 514 /* config:GEN_PMCON* */ 515 static void 516 ich9_lpc_pmcon_update(ICH9LPCState *lpc) 517 { 518 uint16_t gen_pmcon_1 = pci_get_word(lpc->d.config + ICH9_LPC_GEN_PMCON_1); 519 uint16_t wmask; 520 521 if (gen_pmcon_1 & ICH9_LPC_GEN_PMCON_1_SMI_LOCK) { 522 wmask = pci_get_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1); 523 wmask &= ~ICH9_LPC_GEN_PMCON_1_SMI_LOCK; 524 pci_set_word(lpc->d.wmask + ICH9_LPC_GEN_PMCON_1, wmask); 525 lpc->pm.smi_en_wmask &= ~1; 526 } 527 } 528 529 static int ich9_lpc_post_load(void *opaque, int version_id) 530 { 531 ICH9LPCState *lpc = opaque; 532 533 ich9_lpc_pmbase_sci_update(lpc); 534 ich9_lpc_rcba_update(lpc, 0 /* disabled ICH9_LPC_RCBA_EN */); 535 ich9_lpc_pmcon_update(lpc); 536 return 0; 537 } 538 539 static void ich9_lpc_config_write(PCIDevice *d, 540 uint32_t addr, uint32_t val, int len) 541 { 542 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 543 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); 544 545 pci_default_write_config(d, addr, val, len); 546 if (ranges_overlap(addr, len, ICH9_LPC_PMBASE, 4) || 547 ranges_overlap(addr, len, ICH9_LPC_ACPI_CTRL, 1)) { 548 ich9_lpc_pmbase_sci_update(lpc); 549 } 550 if (ranges_overlap(addr, len, ICH9_LPC_RCBA, 4)) { 551 ich9_lpc_rcba_update(lpc, rcba_old); 552 } 553 if (ranges_overlap(addr, len, ICH9_LPC_PIRQA_ROUT, 4)) { 554 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 555 } 556 if (ranges_overlap(addr, len, ICH9_LPC_PIRQE_ROUT, 4)) { 557 pci_bus_fire_intx_routing_notifier(pci_get_bus(&lpc->d)); 558 } 559 if (ranges_overlap(addr, len, ICH9_LPC_GEN_PMCON_1, 8)) { 560 ich9_lpc_pmcon_update(lpc); 561 } 562 } 563 564 static void ich9_lpc_reset(DeviceState *qdev) 565 { 566 PCIDevice *d = PCI_DEVICE(qdev); 567 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 568 uint32_t rcba_old = pci_get_long(d->config + ICH9_LPC_RCBA); 569 int i; 570 571 for (i = 0; i < 4; i++) { 572 pci_set_byte(d->config + ICH9_LPC_PIRQA_ROUT + i, 573 ICH9_LPC_PIRQ_ROUT_DEFAULT); 574 } 575 for (i = 0; i < 4; i++) { 576 pci_set_byte(d->config + ICH9_LPC_PIRQE_ROUT + i, 577 ICH9_LPC_PIRQ_ROUT_DEFAULT); 578 } 579 pci_set_byte(d->config + ICH9_LPC_ACPI_CTRL, ICH9_LPC_ACPI_CTRL_DEFAULT); 580 581 pci_set_long(d->config + ICH9_LPC_PMBASE, ICH9_LPC_PMBASE_DEFAULT); 582 pci_set_long(d->config + ICH9_LPC_RCBA, ICH9_LPC_RCBA_DEFAULT); 583 584 ich9_cc_reset(lpc); 585 586 ich9_lpc_pmbase_sci_update(lpc); 587 ich9_lpc_rcba_update(lpc, rcba_old); 588 589 lpc->sci_level = 0; 590 lpc->rst_cnt = 0; 591 592 memset(lpc->smi_guest_features_le, 0, sizeof lpc->smi_guest_features_le); 593 lpc->smi_features_ok = 0; 594 lpc->smi_negotiated_features = 0; 595 } 596 597 /* root complex register block is mapped into memory space */ 598 static const MemoryRegionOps rcrb_mmio_ops = { 599 .read = ich9_cc_read, 600 .write = ich9_cc_write, 601 .endianness = DEVICE_LITTLE_ENDIAN, 602 }; 603 604 static void ich9_lpc_machine_ready(Notifier *n, void *opaque) 605 { 606 ICH9LPCState *s = container_of(n, ICH9LPCState, machine_ready); 607 MemoryRegion *io_as = pci_address_space_io(&s->d); 608 uint8_t *pci_conf; 609 610 pci_conf = s->d.config; 611 if (memory_region_present(io_as, 0x3f8)) { 612 /* com1 */ 613 pci_conf[0x82] |= 0x01; 614 } 615 if (memory_region_present(io_as, 0x2f8)) { 616 /* com2 */ 617 pci_conf[0x82] |= 0x02; 618 } 619 if (memory_region_present(io_as, 0x378)) { 620 /* lpt */ 621 pci_conf[0x82] |= 0x04; 622 } 623 if (memory_region_present(io_as, 0x3f2)) { 624 /* floppy */ 625 pci_conf[0x82] |= 0x08; 626 } 627 } 628 629 /* reset control */ 630 static void ich9_rst_cnt_write(void *opaque, hwaddr addr, uint64_t val, 631 unsigned len) 632 { 633 ICH9LPCState *lpc = opaque; 634 635 if (val & 4) { 636 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 637 return; 638 } 639 lpc->rst_cnt = val & 0xA; /* keep FULL_RST (bit 3) and SYS_RST (bit 1) */ 640 } 641 642 static uint64_t ich9_rst_cnt_read(void *opaque, hwaddr addr, unsigned len) 643 { 644 ICH9LPCState *lpc = opaque; 645 646 return lpc->rst_cnt; 647 } 648 649 static const MemoryRegionOps ich9_rst_cnt_ops = { 650 .read = ich9_rst_cnt_read, 651 .write = ich9_rst_cnt_write, 652 .endianness = DEVICE_LITTLE_ENDIAN 653 }; 654 655 static void ich9_lpc_initfn(Object *obj) 656 { 657 ICH9LPCState *lpc = ICH9_LPC_DEVICE(obj); 658 659 static const uint8_t acpi_enable_cmd = ICH9_APM_ACPI_ENABLE; 660 static const uint8_t acpi_disable_cmd = ICH9_APM_ACPI_DISABLE; 661 662 object_property_add_uint8_ptr(obj, ACPI_PM_PROP_SCI_INT, 663 &lpc->sci_gsi, OBJ_PROP_FLAG_READ); 664 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_ENABLE_CMD, 665 &acpi_enable_cmd, OBJ_PROP_FLAG_READ); 666 object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD, 667 &acpi_disable_cmd, OBJ_PROP_FLAG_READ); 668 object_property_add_uint64_ptr(obj, ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, 669 &lpc->smi_negotiated_features, 670 OBJ_PROP_FLAG_READ); 671 672 ich9_pm_add_properties(obj, &lpc->pm); 673 } 674 675 static void ich9_lpc_realize(PCIDevice *d, Error **errp) 676 { 677 ICH9LPCState *lpc = ICH9_LPC_DEVICE(d); 678 DeviceState *dev = DEVICE(d); 679 ISABus *isa_bus; 680 681 isa_bus = isa_bus_new(DEVICE(d), get_system_memory(), get_system_io(), 682 errp); 683 if (!isa_bus) { 684 return; 685 } 686 687 pci_set_long(d->wmask + ICH9_LPC_PMBASE, 688 ICH9_LPC_PMBASE_BASE_ADDRESS_MASK); 689 pci_set_byte(d->wmask + ICH9_LPC_PMBASE, 690 ICH9_LPC_ACPI_CTRL_ACPI_EN | 691 ICH9_LPC_ACPI_CTRL_SCI_IRQ_SEL_MASK); 692 693 memory_region_init_io(&lpc->rcrb_mem, OBJECT(d), &rcrb_mmio_ops, lpc, 694 "lpc-rcrb-mmio", ICH9_CC_SIZE); 695 696 lpc->isa_bus = isa_bus; 697 698 ich9_cc_init(lpc); 699 apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc); 700 701 lpc->machine_ready.notify = ich9_lpc_machine_ready; 702 qemu_add_machine_init_done_notifier(&lpc->machine_ready); 703 704 memory_region_init_io(&lpc->rst_cnt_mem, OBJECT(d), &ich9_rst_cnt_ops, lpc, 705 "lpc-reset-control", 1); 706 memory_region_add_subregion_overlap(pci_address_space_io(d), 707 ICH9_RST_CNT_IOPORT, &lpc->rst_cnt_mem, 708 1); 709 710 qdev_init_gpio_out_named(dev, lpc->gsi, ICH9_GPIO_GSI, GSI_NUM_PINS); 711 712 isa_bus_irqs(isa_bus, lpc->gsi); 713 } 714 715 static bool ich9_rst_cnt_needed(void *opaque) 716 { 717 ICH9LPCState *lpc = opaque; 718 719 return (lpc->rst_cnt != 0); 720 } 721 722 static const VMStateDescription vmstate_ich9_rst_cnt = { 723 .name = "ICH9LPC/rst_cnt", 724 .version_id = 1, 725 .minimum_version_id = 1, 726 .needed = ich9_rst_cnt_needed, 727 .fields = (VMStateField[]) { 728 VMSTATE_UINT8(rst_cnt, ICH9LPCState), 729 VMSTATE_END_OF_LIST() 730 } 731 }; 732 733 static bool ich9_smi_feat_needed(void *opaque) 734 { 735 ICH9LPCState *lpc = opaque; 736 737 return !buffer_is_zero(lpc->smi_guest_features_le, 738 sizeof lpc->smi_guest_features_le) || 739 lpc->smi_features_ok; 740 } 741 742 static const VMStateDescription vmstate_ich9_smi_feat = { 743 .name = "ICH9LPC/smi_feat", 744 .version_id = 1, 745 .minimum_version_id = 1, 746 .needed = ich9_smi_feat_needed, 747 .fields = (VMStateField[]) { 748 VMSTATE_UINT8_ARRAY(smi_guest_features_le, ICH9LPCState, 749 sizeof(uint64_t)), 750 VMSTATE_UINT8(smi_features_ok, ICH9LPCState), 751 VMSTATE_UINT64(smi_negotiated_features, ICH9LPCState), 752 VMSTATE_END_OF_LIST() 753 } 754 }; 755 756 static const VMStateDescription vmstate_ich9_lpc = { 757 .name = "ICH9LPC", 758 .version_id = 1, 759 .minimum_version_id = 1, 760 .post_load = ich9_lpc_post_load, 761 .fields = (VMStateField[]) { 762 VMSTATE_PCI_DEVICE(d, ICH9LPCState), 763 VMSTATE_STRUCT(apm, ICH9LPCState, 0, vmstate_apm, APMState), 764 VMSTATE_STRUCT(pm, ICH9LPCState, 0, vmstate_ich9_pm, ICH9LPCPMRegs), 765 VMSTATE_UINT8_ARRAY(chip_config, ICH9LPCState, ICH9_CC_SIZE), 766 VMSTATE_UINT32(sci_level, ICH9LPCState), 767 VMSTATE_END_OF_LIST() 768 }, 769 .subsections = (const VMStateDescription*[]) { 770 &vmstate_ich9_rst_cnt, 771 &vmstate_ich9_smi_feat, 772 NULL 773 } 774 }; 775 776 static Property ich9_lpc_properties[] = { 777 DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, true), 778 DEFINE_PROP_BOOL("smm-compat", ICH9LPCState, pm.smm_compat, false), 779 DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features, 780 ICH9_LPC_SMI_F_BROADCAST_BIT, true), 781 DEFINE_PROP_BIT64("x-smi-cpu-hotplug", ICH9LPCState, smi_host_features, 782 ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT, true), 783 DEFINE_PROP_BIT64("x-smi-cpu-hotunplug", ICH9LPCState, smi_host_features, 784 ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT, true), 785 DEFINE_PROP_END_OF_LIST(), 786 }; 787 788 static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) 789 { 790 ICH9LPCState *s = ICH9_LPC_DEVICE(adev); 791 792 acpi_send_gpe_event(&s->pm.acpi_regs, s->pm.irq, ev); 793 } 794 795 static void ich9_lpc_class_init(ObjectClass *klass, void *data) 796 { 797 DeviceClass *dc = DEVICE_CLASS(klass); 798 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 799 HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass); 800 AcpiDeviceIfClass *adevc = ACPI_DEVICE_IF_CLASS(klass); 801 802 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 803 dc->reset = ich9_lpc_reset; 804 k->realize = ich9_lpc_realize; 805 dc->vmsd = &vmstate_ich9_lpc; 806 device_class_set_props(dc, ich9_lpc_properties); 807 k->config_write = ich9_lpc_config_write; 808 dc->desc = "ICH9 LPC bridge"; 809 k->vendor_id = PCI_VENDOR_ID_INTEL; 810 k->device_id = PCI_DEVICE_ID_INTEL_ICH9_8; 811 k->revision = ICH9_A2_LPC_REVISION; 812 k->class_id = PCI_CLASS_BRIDGE_ISA; 813 /* 814 * Reason: part of ICH9 southbridge, needs to be wired up by 815 * pc_q35_init() 816 */ 817 dc->user_creatable = false; 818 hc->pre_plug = ich9_pm_device_pre_plug_cb; 819 hc->plug = ich9_pm_device_plug_cb; 820 hc->unplug_request = ich9_pm_device_unplug_request_cb; 821 hc->unplug = ich9_pm_device_unplug_cb; 822 adevc->ospm_status = ich9_pm_ospm_status; 823 adevc->send_event = ich9_send_gpe; 824 adevc->madt_cpu = pc_madt_cpu_entry; 825 } 826 827 static const TypeInfo ich9_lpc_info = { 828 .name = TYPE_ICH9_LPC_DEVICE, 829 .parent = TYPE_PCI_DEVICE, 830 .instance_size = sizeof(ICH9LPCState), 831 .instance_init = ich9_lpc_initfn, 832 .class_init = ich9_lpc_class_init, 833 .interfaces = (InterfaceInfo[]) { 834 { TYPE_HOTPLUG_HANDLER }, 835 { TYPE_ACPI_DEVICE_IF }, 836 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 837 { } 838 } 839 }; 840 841 static void ich9_lpc_register(void) 842 { 843 type_register_static(&ich9_lpc_info); 844 } 845 846 type_init(ich9_lpc_register); 847