1 /* 2 * QEMU ISA IPMI BT emulation 3 * 4 * Copyright (c) 2015 Corey Minyard, MontaVista Software, LLC 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #include "qemu/osdep.h" 25 #include "hw/hw.h" 26 #include "hw/ipmi/ipmi.h" 27 #include "hw/isa/isa.h" 28 #include "hw/i386/pc.h" 29 30 /* Control register */ 31 #define IPMI_BT_CLR_WR_BIT 0 32 #define IPMI_BT_CLR_RD_BIT 1 33 #define IPMI_BT_H2B_ATN_BIT 2 34 #define IPMI_BT_B2H_ATN_BIT 3 35 #define IPMI_BT_SMS_ATN_BIT 4 36 #define IPMI_BT_HBUSY_BIT 6 37 #define IPMI_BT_BBUSY_BIT 7 38 39 #define IPMI_BT_CLR_WR_MASK (1 << IPMI_BT_CLR_WR_BIT) 40 #define IPMI_BT_GET_CLR_WR(d) (((d) >> IPMI_BT_CLR_WR_BIT) & 0x1) 41 #define IPMI_BT_SET_CLR_WR(d, v) (d) = (((d) & ~IPMI_BT_CLR_WR_MASK) | \ 42 (((v & 1) << IPMI_BT_CLR_WR_BIT))) 43 44 #define IPMI_BT_CLR_RD_MASK (1 << IPMI_BT_CLR_RD_BIT) 45 #define IPMI_BT_GET_CLR_RD(d) (((d) >> IPMI_BT_CLR_RD_BIT) & 0x1) 46 #define IPMI_BT_SET_CLR_RD(d, v) (d) = (((d) & ~IPMI_BT_CLR_RD_MASK) | \ 47 (((v & 1) << IPMI_BT_CLR_RD_BIT))) 48 49 #define IPMI_BT_H2B_ATN_MASK (1 << IPMI_BT_H2B_ATN_BIT) 50 #define IPMI_BT_GET_H2B_ATN(d) (((d) >> IPMI_BT_H2B_ATN_BIT) & 0x1) 51 #define IPMI_BT_SET_H2B_ATN(d, v) (d) = (((d) & ~IPMI_BT_H2B_ATN_MASK) | \ 52 (((v & 1) << IPMI_BT_H2B_ATN_BIT))) 53 54 #define IPMI_BT_B2H_ATN_MASK (1 << IPMI_BT_B2H_ATN_BIT) 55 #define IPMI_BT_GET_B2H_ATN(d) (((d) >> IPMI_BT_B2H_ATN_BIT) & 0x1) 56 #define IPMI_BT_SET_B2H_ATN(d, v) (d) = (((d) & ~IPMI_BT_B2H_ATN_MASK) | \ 57 (((v & 1) << IPMI_BT_B2H_ATN_BIT))) 58 59 #define IPMI_BT_SMS_ATN_MASK (1 << IPMI_BT_SMS_ATN_BIT) 60 #define IPMI_BT_GET_SMS_ATN(d) (((d) >> IPMI_BT_SMS_ATN_BIT) & 0x1) 61 #define IPMI_BT_SET_SMS_ATN(d, v) (d) = (((d) & ~IPMI_BT_SMS_ATN_MASK) | \ 62 (((v & 1) << IPMI_BT_SMS_ATN_BIT))) 63 64 #define IPMI_BT_HBUSY_MASK (1 << IPMI_BT_HBUSY_BIT) 65 #define IPMI_BT_GET_HBUSY(d) (((d) >> IPMI_BT_HBUSY_BIT) & 0x1) 66 #define IPMI_BT_SET_HBUSY(d, v) (d) = (((d) & ~IPMI_BT_HBUSY_MASK) | \ 67 (((v & 1) << IPMI_BT_HBUSY_BIT))) 68 69 #define IPMI_BT_BBUSY_MASK (1 << IPMI_BT_BBUSY_BIT) 70 #define IPMI_BT_GET_BBUSY(d) (((d) >> IPMI_BT_BBUSY_BIT) & 0x1) 71 #define IPMI_BT_SET_BBUSY(d, v) (d) = (((d) & ~IPMI_BT_BBUSY_MASK) | \ 72 (((v & 1) << IPMI_BT_BBUSY_BIT))) 73 74 75 /* Mask register */ 76 #define IPMI_BT_B2H_IRQ_EN_BIT 0 77 #define IPMI_BT_B2H_IRQ_BIT 1 78 79 #define IPMI_BT_B2H_IRQ_EN_MASK (1 << IPMI_BT_B2H_IRQ_EN_BIT) 80 #define IPMI_BT_GET_B2H_IRQ_EN(d) (((d) >> IPMI_BT_B2H_IRQ_EN_BIT) & 0x1) 81 #define IPMI_BT_SET_B2H_IRQ_EN(d, v) (d) = (((d) & ~IPMI_BT_B2H_IRQ_EN_MASK) | \ 82 (((v & 1) << IPMI_BT_B2H_IRQ_EN_BIT))) 83 84 #define IPMI_BT_B2H_IRQ_MASK (1 << IPMI_BT_B2H_IRQ_BIT) 85 #define IPMI_BT_GET_B2H_IRQ(d) (((d) >> IPMI_BT_B2H_IRQ_BIT) & 0x1) 86 #define IPMI_BT_SET_B2H_IRQ(d, v) (d) = (((d) & ~IPMI_BT_B2H_IRQ_MASK) | \ 87 (((v & 1) << IPMI_BT_B2H_IRQ_BIT))) 88 89 typedef struct IPMIBT { 90 IPMIBmc *bmc; 91 92 bool do_wake; 93 94 qemu_irq irq; 95 96 uint32_t io_base; 97 unsigned long io_length; 98 MemoryRegion io; 99 100 bool obf_irq_set; 101 bool atn_irq_set; 102 bool use_irq; 103 bool irqs_enabled; 104 105 uint8_t outmsg[MAX_IPMI_MSG_SIZE]; 106 uint32_t outpos; 107 uint32_t outlen; 108 109 uint8_t inmsg[MAX_IPMI_MSG_SIZE]; 110 uint32_t inlen; 111 112 uint8_t control_reg; 113 uint8_t mask_reg; 114 115 /* 116 * This is a response number that we send with the command to make 117 * sure that the response matches the command. 118 */ 119 uint8_t waiting_rsp; 120 uint8_t waiting_seq; 121 } IPMIBT; 122 123 #define IPMI_CMD_GET_BT_INTF_CAP 0x36 124 125 static void ipmi_bt_handle_event(IPMIInterface *ii) 126 { 127 IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii); 128 IPMIBT *ib = iic->get_backend_data(ii); 129 130 if (ib->inlen < 4) { 131 goto out; 132 } 133 /* Note that overruns are handled by handle_command */ 134 if (ib->inmsg[0] != (ib->inlen - 1)) { 135 /* Length mismatch, just ignore. */ 136 IPMI_BT_SET_BBUSY(ib->control_reg, 1); 137 ib->inlen = 0; 138 goto out; 139 } 140 if ((ib->inmsg[1] == (IPMI_NETFN_APP << 2)) && 141 (ib->inmsg[3] == IPMI_CMD_GET_BT_INTF_CAP)) { 142 /* We handle this one ourselves. */ 143 ib->outmsg[0] = 9; 144 ib->outmsg[1] = ib->inmsg[1] | 0x04; 145 ib->outmsg[2] = ib->inmsg[2]; 146 ib->outmsg[3] = ib->inmsg[3]; 147 ib->outmsg[4] = 0; 148 ib->outmsg[5] = 1; /* Only support 1 outstanding request. */ 149 if (sizeof(ib->inmsg) > 0xff) { /* Input buffer size */ 150 ib->outmsg[6] = 0xff; 151 } else { 152 ib->outmsg[6] = (unsigned char) sizeof(ib->inmsg); 153 } 154 if (sizeof(ib->outmsg) > 0xff) { /* Output buffer size */ 155 ib->outmsg[7] = 0xff; 156 } else { 157 ib->outmsg[7] = (unsigned char) sizeof(ib->outmsg); 158 } 159 ib->outmsg[8] = 10; /* Max request to response time */ 160 ib->outmsg[9] = 0; /* Don't recommend retries */ 161 ib->outlen = 10; 162 IPMI_BT_SET_BBUSY(ib->control_reg, 0); 163 IPMI_BT_SET_B2H_ATN(ib->control_reg, 1); 164 if (ib->use_irq && ib->irqs_enabled && 165 !IPMI_BT_GET_B2H_IRQ(ib->mask_reg) && 166 IPMI_BT_GET_B2H_IRQ_EN(ib->mask_reg)) { 167 IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 1); 168 qemu_irq_raise(ib->irq); 169 } 170 goto out; 171 } 172 ib->waiting_seq = ib->inmsg[2]; 173 ib->inmsg[2] = ib->inmsg[1]; 174 { 175 IPMIBmcClass *bk = IPMI_BMC_GET_CLASS(ib->bmc); 176 bk->handle_command(ib->bmc, ib->inmsg + 2, ib->inlen - 2, 177 sizeof(ib->inmsg), ib->waiting_rsp); 178 } 179 out: 180 return; 181 } 182 183 static void ipmi_bt_handle_rsp(IPMIInterface *ii, uint8_t msg_id, 184 unsigned char *rsp, unsigned int rsp_len) 185 { 186 IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii); 187 IPMIBT *ib = iic->get_backend_data(ii); 188 189 if (ib->waiting_rsp == msg_id) { 190 ib->waiting_rsp++; 191 if (rsp_len > (sizeof(ib->outmsg) - 2)) { 192 ib->outmsg[0] = 4; 193 ib->outmsg[1] = rsp[0]; 194 ib->outmsg[2] = ib->waiting_seq; 195 ib->outmsg[3] = rsp[1]; 196 ib->outmsg[4] = IPMI_CC_CANNOT_RETURN_REQ_NUM_BYTES; 197 ib->outlen = 5; 198 } else { 199 ib->outmsg[0] = rsp_len + 1; 200 ib->outmsg[1] = rsp[0]; 201 ib->outmsg[2] = ib->waiting_seq; 202 memcpy(ib->outmsg + 3, rsp + 1, rsp_len - 1); 203 ib->outlen = rsp_len + 2; 204 } 205 IPMI_BT_SET_BBUSY(ib->control_reg, 0); 206 IPMI_BT_SET_B2H_ATN(ib->control_reg, 1); 207 if (ib->use_irq && ib->irqs_enabled && 208 !IPMI_BT_GET_B2H_IRQ(ib->mask_reg) && 209 IPMI_BT_GET_B2H_IRQ_EN(ib->mask_reg)) { 210 IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 1); 211 qemu_irq_raise(ib->irq); 212 } 213 } 214 } 215 216 217 static uint64_t ipmi_bt_ioport_read(void *opaque, hwaddr addr, unsigned size) 218 { 219 IPMIInterface *ii = opaque; 220 IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii); 221 IPMIBT *ib = iic->get_backend_data(ii); 222 uint32_t ret = 0xff; 223 224 switch (addr & 3) { 225 case 0: 226 ret = ib->control_reg; 227 break; 228 case 1: 229 if (ib->outpos < ib->outlen) { 230 ret = ib->outmsg[ib->outpos]; 231 ib->outpos++; 232 if (ib->outpos == ib->outlen) { 233 ib->outpos = 0; 234 ib->outlen = 0; 235 } 236 } else { 237 ret = 0xff; 238 } 239 break; 240 case 2: 241 ret = ib->mask_reg; 242 break; 243 } 244 return ret; 245 } 246 247 static void ipmi_bt_signal(IPMIBT *ib, IPMIInterface *ii) 248 { 249 IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii); 250 251 ib->do_wake = 1; 252 while (ib->do_wake) { 253 ib->do_wake = 0; 254 iic->handle_if_event(ii); 255 } 256 } 257 258 static void ipmi_bt_ioport_write(void *opaque, hwaddr addr, uint64_t val, 259 unsigned size) 260 { 261 IPMIInterface *ii = opaque; 262 IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii); 263 IPMIBT *ib = iic->get_backend_data(ii); 264 265 switch (addr & 3) { 266 case 0: 267 if (IPMI_BT_GET_CLR_WR(val)) { 268 ib->inlen = 0; 269 } 270 if (IPMI_BT_GET_CLR_RD(val)) { 271 ib->outpos = 0; 272 } 273 if (IPMI_BT_GET_B2H_ATN(val)) { 274 IPMI_BT_SET_B2H_ATN(ib->control_reg, 0); 275 } 276 if (IPMI_BT_GET_SMS_ATN(val)) { 277 IPMI_BT_SET_SMS_ATN(ib->control_reg, 0); 278 } 279 if (IPMI_BT_GET_HBUSY(val)) { 280 /* Toggle */ 281 IPMI_BT_SET_HBUSY(ib->control_reg, 282 !IPMI_BT_GET_HBUSY(ib->control_reg)); 283 } 284 if (IPMI_BT_GET_H2B_ATN(val)) { 285 IPMI_BT_SET_BBUSY(ib->control_reg, 1); 286 ipmi_bt_signal(ib, ii); 287 } 288 break; 289 290 case 1: 291 if (ib->inlen < sizeof(ib->inmsg)) { 292 ib->inmsg[ib->inlen] = val; 293 } 294 ib->inlen++; 295 break; 296 297 case 2: 298 if (IPMI_BT_GET_B2H_IRQ_EN(val) != 299 IPMI_BT_GET_B2H_IRQ_EN(ib->mask_reg)) { 300 if (IPMI_BT_GET_B2H_IRQ_EN(val)) { 301 if (IPMI_BT_GET_B2H_ATN(ib->control_reg) || 302 IPMI_BT_GET_SMS_ATN(ib->control_reg)) { 303 IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 1); 304 qemu_irq_raise(ib->irq); 305 } 306 IPMI_BT_SET_B2H_IRQ_EN(ib->mask_reg, 1); 307 } else { 308 if (IPMI_BT_GET_B2H_IRQ(ib->mask_reg)) { 309 IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 0); 310 qemu_irq_lower(ib->irq); 311 } 312 IPMI_BT_SET_B2H_IRQ_EN(ib->mask_reg, 0); 313 } 314 } 315 if (IPMI_BT_GET_B2H_IRQ(val) && IPMI_BT_GET_B2H_IRQ(ib->mask_reg)) { 316 IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 0); 317 qemu_irq_lower(ib->irq); 318 } 319 break; 320 } 321 } 322 323 static const MemoryRegionOps ipmi_bt_io_ops = { 324 .read = ipmi_bt_ioport_read, 325 .write = ipmi_bt_ioport_write, 326 .impl = { 327 .min_access_size = 1, 328 .max_access_size = 1, 329 }, 330 .endianness = DEVICE_LITTLE_ENDIAN, 331 }; 332 333 static void ipmi_bt_set_atn(IPMIInterface *ii, int val, int irq) 334 { 335 IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii); 336 IPMIBT *ib = iic->get_backend_data(ii); 337 338 if (!!val == IPMI_BT_GET_SMS_ATN(ib->control_reg)) { 339 return; 340 } 341 342 IPMI_BT_SET_SMS_ATN(ib->control_reg, val); 343 if (val) { 344 if (irq && ib->use_irq && ib->irqs_enabled && 345 !IPMI_BT_GET_B2H_ATN(ib->control_reg) && 346 IPMI_BT_GET_B2H_IRQ_EN(ib->mask_reg)) { 347 IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 1); 348 qemu_irq_raise(ib->irq); 349 } 350 } else { 351 if (!IPMI_BT_GET_B2H_ATN(ib->control_reg) && 352 IPMI_BT_GET_B2H_IRQ(ib->mask_reg)) { 353 IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 0); 354 qemu_irq_lower(ib->irq); 355 } 356 } 357 } 358 359 static void ipmi_bt_handle_reset(IPMIInterface *ii, bool is_cold) 360 { 361 IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii); 362 IPMIBT *ib = iic->get_backend_data(ii); 363 364 if (is_cold) { 365 /* Disable the BT interrupt on reset */ 366 if (IPMI_BT_GET_B2H_IRQ(ib->mask_reg)) { 367 IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 0); 368 qemu_irq_lower(ib->irq); 369 } 370 IPMI_BT_SET_B2H_IRQ_EN(ib->mask_reg, 0); 371 } 372 } 373 374 static void ipmi_bt_set_irq_enable(IPMIInterface *ii, int val) 375 { 376 IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii); 377 IPMIBT *ib = iic->get_backend_data(ii); 378 379 ib->irqs_enabled = val; 380 } 381 382 static void ipmi_bt_init(IPMIInterface *ii, Error **errp) 383 { 384 IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii); 385 IPMIBT *ib = iic->get_backend_data(ii); 386 387 ib->io_length = 3; 388 389 memory_region_init_io(&ib->io, NULL, &ipmi_bt_io_ops, ii, "ipmi-bt", 3); 390 } 391 392 static void ipmi_bt_class_init(IPMIInterfaceClass *iic) 393 { 394 iic->init = ipmi_bt_init; 395 iic->set_atn = ipmi_bt_set_atn; 396 iic->handle_rsp = ipmi_bt_handle_rsp; 397 iic->handle_if_event = ipmi_bt_handle_event; 398 iic->set_irq_enable = ipmi_bt_set_irq_enable; 399 iic->reset = ipmi_bt_handle_reset; 400 } 401 402 403 #define TYPE_ISA_IPMI_BT "isa-ipmi-bt" 404 #define ISA_IPMI_BT(obj) OBJECT_CHECK(ISAIPMIBTDevice, (obj), \ 405 TYPE_ISA_IPMI_BT) 406 407 typedef struct ISAIPMIBTDevice { 408 ISADevice dev; 409 int32_t isairq; 410 IPMIBT bt; 411 IPMIFwInfo fwinfo; 412 } ISAIPMIBTDevice; 413 414 static void isa_ipmi_bt_realize(DeviceState *dev, Error **errp) 415 { 416 ISADevice *isadev = ISA_DEVICE(dev); 417 ISAIPMIBTDevice *iib = ISA_IPMI_BT(dev); 418 IPMIInterface *ii = IPMI_INTERFACE(dev); 419 IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii); 420 421 if (!iib->bt.bmc) { 422 error_setg(errp, "IPMI device requires a bmc attribute to be set"); 423 return; 424 } 425 426 iib->bt.bmc->intf = ii; 427 428 iic->init(ii, errp); 429 if (*errp) 430 return; 431 432 if (iib->isairq > 0) { 433 isa_init_irq(isadev, &iib->bt.irq, iib->isairq); 434 iib->bt.use_irq = 1; 435 } 436 437 qdev_set_legacy_instance_id(dev, iib->bt.io_base, iib->bt.io_length); 438 439 isa_register_ioport(isadev, &iib->bt.io, iib->bt.io_base); 440 441 iib->fwinfo.interface_name = "bt"; 442 iib->fwinfo.interface_type = IPMI_SMBIOS_BT; 443 iib->fwinfo.ipmi_spec_major_revision = 2; 444 iib->fwinfo.ipmi_spec_minor_revision = 0; 445 iib->fwinfo.base_address = iib->bt.io_base; 446 iib->fwinfo.register_length = iib->bt.io_length; 447 iib->fwinfo.register_spacing = 1; 448 iib->fwinfo.memspace = IPMI_MEMSPACE_IO; 449 iib->fwinfo.irq_type = IPMI_LEVEL_IRQ; 450 iib->fwinfo.interrupt_number = iib->isairq; 451 iib->fwinfo.acpi_parent = "\\_SB.PCI0.ISA"; 452 iib->fwinfo.i2c_slave_address = iib->bt.bmc->slave_addr; 453 ipmi_add_fwinfo(&iib->fwinfo, errp); 454 } 455 456 static const VMStateDescription vmstate_ISAIPMIBTDevice = { 457 .name = TYPE_IPMI_INTERFACE, 458 .version_id = 1, 459 .minimum_version_id = 1, 460 .fields = (VMStateField[]) { 461 VMSTATE_BOOL(bt.obf_irq_set, ISAIPMIBTDevice), 462 VMSTATE_BOOL(bt.atn_irq_set, ISAIPMIBTDevice), 463 VMSTATE_BOOL(bt.use_irq, ISAIPMIBTDevice), 464 VMSTATE_BOOL(bt.irqs_enabled, ISAIPMIBTDevice), 465 VMSTATE_UINT32(bt.outpos, ISAIPMIBTDevice), 466 VMSTATE_VBUFFER_UINT32(bt.outmsg, ISAIPMIBTDevice, 1, NULL, 0, 467 bt.outlen), 468 VMSTATE_VBUFFER_UINT32(bt.inmsg, ISAIPMIBTDevice, 1, NULL, 0, 469 bt.inlen), 470 VMSTATE_UINT8(bt.control_reg, ISAIPMIBTDevice), 471 VMSTATE_UINT8(bt.mask_reg, ISAIPMIBTDevice), 472 VMSTATE_UINT8(bt.waiting_rsp, ISAIPMIBTDevice), 473 VMSTATE_UINT8(bt.waiting_seq, ISAIPMIBTDevice), 474 VMSTATE_END_OF_LIST() 475 } 476 }; 477 478 static void isa_ipmi_bt_init(Object *obj) 479 { 480 ISAIPMIBTDevice *iib = ISA_IPMI_BT(obj); 481 482 ipmi_bmc_find_and_link(obj, (Object **) &iib->bt.bmc); 483 484 vmstate_register(NULL, 0, &vmstate_ISAIPMIBTDevice, iib); 485 } 486 487 static void *isa_ipmi_bt_get_backend_data(IPMIInterface *ii) 488 { 489 ISAIPMIBTDevice *iib = ISA_IPMI_BT(ii); 490 491 return &iib->bt; 492 } 493 494 static Property ipmi_isa_properties[] = { 495 DEFINE_PROP_UINT32("ioport", ISAIPMIBTDevice, bt.io_base, 0xe4), 496 DEFINE_PROP_INT32("irq", ISAIPMIBTDevice, isairq, 5), 497 DEFINE_PROP_END_OF_LIST(), 498 }; 499 500 static void isa_ipmi_bt_class_init(ObjectClass *oc, void *data) 501 { 502 DeviceClass *dc = DEVICE_CLASS(oc); 503 IPMIInterfaceClass *iic = IPMI_INTERFACE_CLASS(oc); 504 505 dc->realize = isa_ipmi_bt_realize; 506 dc->props = ipmi_isa_properties; 507 508 iic->get_backend_data = isa_ipmi_bt_get_backend_data; 509 ipmi_bt_class_init(iic); 510 } 511 512 static const TypeInfo isa_ipmi_bt_info = { 513 .name = TYPE_ISA_IPMI_BT, 514 .parent = TYPE_ISA_DEVICE, 515 .instance_size = sizeof(ISAIPMIBTDevice), 516 .instance_init = isa_ipmi_bt_init, 517 .class_init = isa_ipmi_bt_class_init, 518 .interfaces = (InterfaceInfo[]) { 519 { TYPE_IPMI_INTERFACE }, 520 { } 521 } 522 }; 523 524 static void ipmi_register_types(void) 525 { 526 type_register_static(&isa_ipmi_bt_info); 527 } 528 529 type_init(ipmi_register_types) 530