1 /* 2 * QEMU ISA IPMI BT emulation 3 * 4 * Copyright (c) 2015 Corey Minyard, MontaVista Software, LLC 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/log.h" 27 #include "qemu/module.h" 28 #include "qapi/error.h" 29 #include "hw/hw.h" 30 #include "hw/ipmi/ipmi.h" 31 #include "hw/irq.h" 32 #include "hw/isa/isa.h" 33 34 /* Control register */ 35 #define IPMI_BT_CLR_WR_BIT 0 36 #define IPMI_BT_CLR_RD_BIT 1 37 #define IPMI_BT_H2B_ATN_BIT 2 38 #define IPMI_BT_B2H_ATN_BIT 3 39 #define IPMI_BT_SMS_ATN_BIT 4 40 #define IPMI_BT_HBUSY_BIT 6 41 #define IPMI_BT_BBUSY_BIT 7 42 43 #define IPMI_BT_GET_CLR_WR(d) (((d) >> IPMI_BT_CLR_WR_BIT) & 0x1) 44 45 #define IPMI_BT_GET_CLR_RD(d) (((d) >> IPMI_BT_CLR_RD_BIT) & 0x1) 46 47 #define IPMI_BT_GET_H2B_ATN(d) (((d) >> IPMI_BT_H2B_ATN_BIT) & 0x1) 48 49 #define IPMI_BT_B2H_ATN_MASK (1 << IPMI_BT_B2H_ATN_BIT) 50 #define IPMI_BT_GET_B2H_ATN(d) (((d) >> IPMI_BT_B2H_ATN_BIT) & 0x1) 51 #define IPMI_BT_SET_B2H_ATN(d, v) ((d) = (((d) & ~IPMI_BT_B2H_ATN_MASK) | \ 52 (!!(v) << IPMI_BT_B2H_ATN_BIT))) 53 54 #define IPMI_BT_SMS_ATN_MASK (1 << IPMI_BT_SMS_ATN_BIT) 55 #define IPMI_BT_GET_SMS_ATN(d) (((d) >> IPMI_BT_SMS_ATN_BIT) & 0x1) 56 #define IPMI_BT_SET_SMS_ATN(d, v) ((d) = (((d) & ~IPMI_BT_SMS_ATN_MASK) | \ 57 (!!(v) << IPMI_BT_SMS_ATN_BIT))) 58 59 #define IPMI_BT_HBUSY_MASK (1 << IPMI_BT_HBUSY_BIT) 60 #define IPMI_BT_GET_HBUSY(d) (((d) >> IPMI_BT_HBUSY_BIT) & 0x1) 61 #define IPMI_BT_SET_HBUSY(d, v) ((d) = (((d) & ~IPMI_BT_HBUSY_MASK) | \ 62 (!!(v) << IPMI_BT_HBUSY_BIT))) 63 64 #define IPMI_BT_BBUSY_MASK (1 << IPMI_BT_BBUSY_BIT) 65 #define IPMI_BT_SET_BBUSY(d, v) ((d) = (((d) & ~IPMI_BT_BBUSY_MASK) | \ 66 (!!(v) << IPMI_BT_BBUSY_BIT))) 67 68 69 /* Mask register */ 70 #define IPMI_BT_B2H_IRQ_EN_BIT 0 71 #define IPMI_BT_B2H_IRQ_BIT 1 72 73 #define IPMI_BT_B2H_IRQ_EN_MASK (1 << IPMI_BT_B2H_IRQ_EN_BIT) 74 #define IPMI_BT_GET_B2H_IRQ_EN(d) (((d) >> IPMI_BT_B2H_IRQ_EN_BIT) & 0x1) 75 #define IPMI_BT_SET_B2H_IRQ_EN(d, v) ((d) = (((d) & ~IPMI_BT_B2H_IRQ_EN_MASK) |\ 76 (!!(v) << IPMI_BT_B2H_IRQ_EN_BIT))) 77 78 #define IPMI_BT_B2H_IRQ_MASK (1 << IPMI_BT_B2H_IRQ_BIT) 79 #define IPMI_BT_GET_B2H_IRQ(d) (((d) >> IPMI_BT_B2H_IRQ_BIT) & 0x1) 80 #define IPMI_BT_SET_B2H_IRQ(d, v) ((d) = (((d) & ~IPMI_BT_B2H_IRQ_MASK) | \ 81 (!!(v) << IPMI_BT_B2H_IRQ_BIT))) 82 83 typedef struct IPMIBT { 84 IPMIBmc *bmc; 85 86 bool do_wake; 87 88 qemu_irq irq; 89 90 uint32_t io_base; 91 unsigned long io_length; 92 MemoryRegion io; 93 94 bool obf_irq_set; 95 bool atn_irq_set; 96 bool use_irq; 97 bool irqs_enabled; 98 99 uint8_t outmsg[MAX_IPMI_MSG_SIZE]; 100 uint32_t outpos; 101 uint32_t outlen; 102 103 uint8_t inmsg[MAX_IPMI_MSG_SIZE]; 104 uint32_t inlen; 105 106 uint8_t control_reg; 107 uint8_t mask_reg; 108 109 /* 110 * This is a response number that we send with the command to make 111 * sure that the response matches the command. 112 */ 113 uint8_t waiting_rsp; 114 uint8_t waiting_seq; 115 } IPMIBT; 116 117 #define IPMI_CMD_GET_BT_INTF_CAP 0x36 118 119 static void ipmi_bt_handle_event(IPMIInterface *ii) 120 { 121 IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii); 122 IPMIBT *ib = iic->get_backend_data(ii); 123 124 if (ib->inlen < 4) { 125 goto out; 126 } 127 /* Note that overruns are handled by handle_command */ 128 if (ib->inmsg[0] != (ib->inlen - 1)) { 129 /* Length mismatch, just ignore. */ 130 IPMI_BT_SET_BBUSY(ib->control_reg, 1); 131 ib->inlen = 0; 132 goto out; 133 } 134 if ((ib->inmsg[1] == (IPMI_NETFN_APP << 2)) && 135 (ib->inmsg[3] == IPMI_CMD_GET_BT_INTF_CAP)) { 136 /* We handle this one ourselves. */ 137 ib->outmsg[0] = 9; 138 ib->outmsg[1] = ib->inmsg[1] | 0x04; 139 ib->outmsg[2] = ib->inmsg[2]; 140 ib->outmsg[3] = ib->inmsg[3]; 141 ib->outmsg[4] = 0; 142 ib->outmsg[5] = 1; /* Only support 1 outstanding request. */ 143 if (sizeof(ib->inmsg) > 0xff) { /* Input buffer size */ 144 ib->outmsg[6] = 0xff; 145 } else { 146 ib->outmsg[6] = (unsigned char) sizeof(ib->inmsg); 147 } 148 if (sizeof(ib->outmsg) > 0xff) { /* Output buffer size */ 149 ib->outmsg[7] = 0xff; 150 } else { 151 ib->outmsg[7] = (unsigned char) sizeof(ib->outmsg); 152 } 153 ib->outmsg[8] = 10; /* Max request to response time */ 154 ib->outmsg[9] = 0; /* Don't recommend retries */ 155 ib->outlen = 10; 156 IPMI_BT_SET_BBUSY(ib->control_reg, 0); 157 IPMI_BT_SET_B2H_ATN(ib->control_reg, 1); 158 if (ib->use_irq && ib->irqs_enabled && 159 !IPMI_BT_GET_B2H_IRQ(ib->mask_reg) && 160 IPMI_BT_GET_B2H_IRQ_EN(ib->mask_reg)) { 161 IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 1); 162 qemu_irq_raise(ib->irq); 163 } 164 goto out; 165 } 166 ib->waiting_seq = ib->inmsg[2]; 167 ib->inmsg[2] = ib->inmsg[1]; 168 { 169 IPMIBmcClass *bk = IPMI_BMC_GET_CLASS(ib->bmc); 170 bk->handle_command(ib->bmc, ib->inmsg + 2, ib->inlen - 2, 171 sizeof(ib->inmsg), ib->waiting_rsp); 172 } 173 out: 174 return; 175 } 176 177 static void ipmi_bt_handle_rsp(IPMIInterface *ii, uint8_t msg_id, 178 unsigned char *rsp, unsigned int rsp_len) 179 { 180 IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii); 181 IPMIBT *ib = iic->get_backend_data(ii); 182 183 if (ib->waiting_rsp == msg_id) { 184 ib->waiting_rsp++; 185 if (rsp_len > (sizeof(ib->outmsg) - 2)) { 186 ib->outmsg[0] = 4; 187 ib->outmsg[1] = rsp[0]; 188 ib->outmsg[2] = ib->waiting_seq; 189 ib->outmsg[3] = rsp[1]; 190 ib->outmsg[4] = IPMI_CC_CANNOT_RETURN_REQ_NUM_BYTES; 191 ib->outlen = 5; 192 } else { 193 ib->outmsg[0] = rsp_len + 1; 194 ib->outmsg[1] = rsp[0]; 195 ib->outmsg[2] = ib->waiting_seq; 196 memcpy(ib->outmsg + 3, rsp + 1, rsp_len - 1); 197 ib->outlen = rsp_len + 2; 198 } 199 IPMI_BT_SET_BBUSY(ib->control_reg, 0); 200 IPMI_BT_SET_B2H_ATN(ib->control_reg, 1); 201 if (ib->use_irq && ib->irqs_enabled && 202 !IPMI_BT_GET_B2H_IRQ(ib->mask_reg) && 203 IPMI_BT_GET_B2H_IRQ_EN(ib->mask_reg)) { 204 IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 1); 205 qemu_irq_raise(ib->irq); 206 } 207 } 208 } 209 210 211 static uint64_t ipmi_bt_ioport_read(void *opaque, hwaddr addr, unsigned size) 212 { 213 IPMIInterface *ii = opaque; 214 IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii); 215 IPMIBT *ib = iic->get_backend_data(ii); 216 uint32_t ret = 0xff; 217 218 switch (addr & 3) { 219 case 0: 220 ret = ib->control_reg; 221 break; 222 case 1: 223 if (ib->outpos < ib->outlen) { 224 ret = ib->outmsg[ib->outpos]; 225 ib->outpos++; 226 if (ib->outpos == ib->outlen) { 227 ib->outpos = 0; 228 ib->outlen = 0; 229 } 230 } else { 231 ret = 0xff; 232 } 233 break; 234 case 2: 235 ret = ib->mask_reg; 236 break; 237 } 238 return ret; 239 } 240 241 static void ipmi_bt_signal(IPMIBT *ib, IPMIInterface *ii) 242 { 243 IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii); 244 245 ib->do_wake = 1; 246 while (ib->do_wake) { 247 ib->do_wake = 0; 248 iic->handle_if_event(ii); 249 } 250 } 251 252 static void ipmi_bt_ioport_write(void *opaque, hwaddr addr, uint64_t val, 253 unsigned size) 254 { 255 IPMIInterface *ii = opaque; 256 IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii); 257 IPMIBT *ib = iic->get_backend_data(ii); 258 259 switch (addr & 3) { 260 case 0: 261 if (IPMI_BT_GET_CLR_WR(val)) { 262 ib->inlen = 0; 263 } 264 if (IPMI_BT_GET_CLR_RD(val)) { 265 ib->outpos = 0; 266 } 267 if (IPMI_BT_GET_B2H_ATN(val)) { 268 IPMI_BT_SET_B2H_ATN(ib->control_reg, 0); 269 } 270 if (IPMI_BT_GET_SMS_ATN(val)) { 271 IPMI_BT_SET_SMS_ATN(ib->control_reg, 0); 272 } 273 if (IPMI_BT_GET_HBUSY(val)) { 274 /* Toggle */ 275 IPMI_BT_SET_HBUSY(ib->control_reg, 276 !IPMI_BT_GET_HBUSY(ib->control_reg)); 277 } 278 if (IPMI_BT_GET_H2B_ATN(val)) { 279 IPMI_BT_SET_BBUSY(ib->control_reg, 1); 280 ipmi_bt_signal(ib, ii); 281 } 282 break; 283 284 case 1: 285 if (ib->inlen < sizeof(ib->inmsg)) { 286 ib->inmsg[ib->inlen] = val; 287 } 288 ib->inlen++; 289 break; 290 291 case 2: 292 if (IPMI_BT_GET_B2H_IRQ_EN(val) != 293 IPMI_BT_GET_B2H_IRQ_EN(ib->mask_reg)) { 294 if (IPMI_BT_GET_B2H_IRQ_EN(val)) { 295 if (IPMI_BT_GET_B2H_ATN(ib->control_reg) || 296 IPMI_BT_GET_SMS_ATN(ib->control_reg)) { 297 IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 1); 298 qemu_irq_raise(ib->irq); 299 } 300 IPMI_BT_SET_B2H_IRQ_EN(ib->mask_reg, 1); 301 } else { 302 if (IPMI_BT_GET_B2H_IRQ(ib->mask_reg)) { 303 IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 0); 304 qemu_irq_lower(ib->irq); 305 } 306 IPMI_BT_SET_B2H_IRQ_EN(ib->mask_reg, 0); 307 } 308 } 309 if (IPMI_BT_GET_B2H_IRQ(val) && IPMI_BT_GET_B2H_IRQ(ib->mask_reg)) { 310 IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 0); 311 qemu_irq_lower(ib->irq); 312 } 313 break; 314 } 315 } 316 317 static const MemoryRegionOps ipmi_bt_io_ops = { 318 .read = ipmi_bt_ioport_read, 319 .write = ipmi_bt_ioport_write, 320 .impl = { 321 .min_access_size = 1, 322 .max_access_size = 1, 323 }, 324 .endianness = DEVICE_LITTLE_ENDIAN, 325 }; 326 327 static void ipmi_bt_set_atn(IPMIInterface *ii, int val, int irq) 328 { 329 IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii); 330 IPMIBT *ib = iic->get_backend_data(ii); 331 332 if (!!val == IPMI_BT_GET_SMS_ATN(ib->control_reg)) { 333 return; 334 } 335 336 IPMI_BT_SET_SMS_ATN(ib->control_reg, val); 337 if (val) { 338 if (irq && ib->use_irq && ib->irqs_enabled && 339 !IPMI_BT_GET_B2H_ATN(ib->control_reg) && 340 IPMI_BT_GET_B2H_IRQ_EN(ib->mask_reg)) { 341 IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 1); 342 qemu_irq_raise(ib->irq); 343 } 344 } else { 345 if (!IPMI_BT_GET_B2H_ATN(ib->control_reg) && 346 IPMI_BT_GET_B2H_IRQ(ib->mask_reg)) { 347 IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 0); 348 qemu_irq_lower(ib->irq); 349 } 350 } 351 } 352 353 static void ipmi_bt_handle_reset(IPMIInterface *ii, bool is_cold) 354 { 355 IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii); 356 IPMIBT *ib = iic->get_backend_data(ii); 357 358 if (is_cold) { 359 /* Disable the BT interrupt on reset */ 360 if (IPMI_BT_GET_B2H_IRQ(ib->mask_reg)) { 361 IPMI_BT_SET_B2H_IRQ(ib->mask_reg, 0); 362 qemu_irq_lower(ib->irq); 363 } 364 IPMI_BT_SET_B2H_IRQ_EN(ib->mask_reg, 0); 365 } 366 } 367 368 static void ipmi_bt_set_irq_enable(IPMIInterface *ii, int val) 369 { 370 IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii); 371 IPMIBT *ib = iic->get_backend_data(ii); 372 373 ib->irqs_enabled = val; 374 } 375 376 static void ipmi_bt_init(IPMIInterface *ii, Error **errp) 377 { 378 IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii); 379 IPMIBT *ib = iic->get_backend_data(ii); 380 381 ib->io_length = 3; 382 383 memory_region_init_io(&ib->io, NULL, &ipmi_bt_io_ops, ii, "ipmi-bt", 3); 384 } 385 386 387 #define TYPE_ISA_IPMI_BT "isa-ipmi-bt" 388 #define ISA_IPMI_BT(obj) OBJECT_CHECK(ISAIPMIBTDevice, (obj), \ 389 TYPE_ISA_IPMI_BT) 390 391 typedef struct ISAIPMIBTDevice { 392 ISADevice dev; 393 int32_t isairq; 394 IPMIBT bt; 395 uint32_t uuid; 396 } ISAIPMIBTDevice; 397 398 static void ipmi_bt_get_fwinfo(struct IPMIInterface *ii, IPMIFwInfo *info) 399 { 400 ISAIPMIBTDevice *iib = ISA_IPMI_BT(ii); 401 402 info->interface_name = "bt"; 403 info->interface_type = IPMI_SMBIOS_BT; 404 info->ipmi_spec_major_revision = 2; 405 info->ipmi_spec_minor_revision = 0; 406 info->base_address = iib->bt.io_base; 407 info->register_length = iib->bt.io_length; 408 info->register_spacing = 1; 409 info->memspace = IPMI_MEMSPACE_IO; 410 info->irq_type = IPMI_LEVEL_IRQ; 411 info->interrupt_number = iib->isairq; 412 info->i2c_slave_address = iib->bt.bmc->slave_addr; 413 info->uuid = iib->uuid; 414 } 415 416 static void ipmi_bt_class_init(IPMIInterfaceClass *iic) 417 { 418 iic->init = ipmi_bt_init; 419 iic->set_atn = ipmi_bt_set_atn; 420 iic->handle_rsp = ipmi_bt_handle_rsp; 421 iic->handle_if_event = ipmi_bt_handle_event; 422 iic->set_irq_enable = ipmi_bt_set_irq_enable; 423 iic->reset = ipmi_bt_handle_reset; 424 iic->get_fwinfo = ipmi_bt_get_fwinfo; 425 } 426 427 static void isa_ipmi_bt_realize(DeviceState *dev, Error **errp) 428 { 429 ISADevice *isadev = ISA_DEVICE(dev); 430 ISAIPMIBTDevice *iib = ISA_IPMI_BT(dev); 431 IPMIInterface *ii = IPMI_INTERFACE(dev); 432 IPMIInterfaceClass *iic = IPMI_INTERFACE_GET_CLASS(ii); 433 434 if (!iib->bt.bmc) { 435 error_setg(errp, "IPMI device requires a bmc attribute to be set"); 436 return; 437 } 438 439 iib->uuid = ipmi_next_uuid(); 440 441 iib->bt.bmc->intf = ii; 442 443 iic->init(ii, errp); 444 if (*errp) 445 return; 446 447 if (iib->isairq > 0) { 448 isa_init_irq(isadev, &iib->bt.irq, iib->isairq); 449 iib->bt.use_irq = 1; 450 } 451 452 qdev_set_legacy_instance_id(dev, iib->bt.io_base, iib->bt.io_length); 453 454 isa_register_ioport(isadev, &iib->bt.io, iib->bt.io_base); 455 } 456 457 static int ipmi_bt_vmstate_post_load(void *opaque, int version) 458 { 459 IPMIBT *ib = opaque; 460 461 /* Make sure all the values are sane. */ 462 if (ib->outpos >= MAX_IPMI_MSG_SIZE || ib->outlen >= MAX_IPMI_MSG_SIZE || 463 ib->outpos >= ib->outlen) { 464 qemu_log_mask(LOG_GUEST_ERROR, 465 "ipmi:bt: vmstate transfer received bad out values: %d %d\n", 466 ib->outpos, ib->outlen); 467 ib->outpos = 0; 468 ib->outlen = 0; 469 } 470 471 if (ib->inlen >= MAX_IPMI_MSG_SIZE) { 472 qemu_log_mask(LOG_GUEST_ERROR, 473 "ipmi:bt: vmstate transfer received bad in value: %d\n", 474 ib->inlen); 475 ib->inlen = 0; 476 } 477 478 return 0; 479 } 480 481 const VMStateDescription vmstate_IPMIBT = { 482 .name = TYPE_IPMI_INTERFACE_PREFIX "bt", 483 .version_id = 1, 484 .minimum_version_id = 1, 485 .post_load = ipmi_bt_vmstate_post_load, 486 .fields = (VMStateField[]) { 487 VMSTATE_BOOL(obf_irq_set, IPMIBT), 488 VMSTATE_BOOL(atn_irq_set, IPMIBT), 489 VMSTATE_BOOL(irqs_enabled, IPMIBT), 490 VMSTATE_UINT32(outpos, IPMIBT), 491 VMSTATE_UINT32(outlen, IPMIBT), 492 VMSTATE_UINT8_ARRAY(outmsg, IPMIBT, MAX_IPMI_MSG_SIZE), 493 VMSTATE_UINT32(inlen, IPMIBT), 494 VMSTATE_UINT8_ARRAY(inmsg, IPMIBT, MAX_IPMI_MSG_SIZE), 495 VMSTATE_UINT8(control_reg, IPMIBT), 496 VMSTATE_UINT8(mask_reg, IPMIBT), 497 VMSTATE_UINT8(waiting_rsp, IPMIBT), 498 VMSTATE_UINT8(waiting_seq, IPMIBT), 499 VMSTATE_END_OF_LIST() 500 } 501 }; 502 503 static const VMStateDescription vmstate_ISAIPMIBTDevice = { 504 .name = TYPE_IPMI_INTERFACE_PREFIX "isa-bt", 505 .version_id = 2, 506 .minimum_version_id = 2, 507 /* 508 * Version 1 had messed up the array transfer, it's not even usable 509 * because it used VMSTATE_VBUFFER_UINT32, but it did not transfer 510 * the buffer length, so random things would happen. 511 */ 512 .fields = (VMStateField[]) { 513 VMSTATE_STRUCT(bt, ISAIPMIBTDevice, 1, vmstate_IPMIBT, IPMIBT), 514 VMSTATE_END_OF_LIST() 515 } 516 }; 517 518 static void isa_ipmi_bt_init(Object *obj) 519 { 520 ISAIPMIBTDevice *iib = ISA_IPMI_BT(obj); 521 522 ipmi_bmc_find_and_link(obj, (Object **) &iib->bt.bmc); 523 524 vmstate_register(NULL, 0, &vmstate_ISAIPMIBTDevice, iib); 525 } 526 527 static void *isa_ipmi_bt_get_backend_data(IPMIInterface *ii) 528 { 529 ISAIPMIBTDevice *iib = ISA_IPMI_BT(ii); 530 531 return &iib->bt; 532 } 533 534 static Property ipmi_isa_properties[] = { 535 DEFINE_PROP_UINT32("ioport", ISAIPMIBTDevice, bt.io_base, 0xe4), 536 DEFINE_PROP_INT32("irq", ISAIPMIBTDevice, isairq, 5), 537 DEFINE_PROP_END_OF_LIST(), 538 }; 539 540 static void isa_ipmi_bt_class_init(ObjectClass *oc, void *data) 541 { 542 DeviceClass *dc = DEVICE_CLASS(oc); 543 IPMIInterfaceClass *iic = IPMI_INTERFACE_CLASS(oc); 544 545 dc->realize = isa_ipmi_bt_realize; 546 dc->props = ipmi_isa_properties; 547 548 iic->get_backend_data = isa_ipmi_bt_get_backend_data; 549 ipmi_bt_class_init(iic); 550 } 551 552 static const TypeInfo isa_ipmi_bt_info = { 553 .name = TYPE_ISA_IPMI_BT, 554 .parent = TYPE_ISA_DEVICE, 555 .instance_size = sizeof(ISAIPMIBTDevice), 556 .instance_init = isa_ipmi_bt_init, 557 .class_init = isa_ipmi_bt_class_init, 558 .interfaces = (InterfaceInfo[]) { 559 { TYPE_IPMI_INTERFACE }, 560 { } 561 } 562 }; 563 564 static void ipmi_register_types(void) 565 { 566 type_register_static(&isa_ipmi_bt_info); 567 } 568 569 type_init(ipmi_register_types) 570