1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2022, IBM Corporation.. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "qapi/type-helpers.h" 15 #include "target/ppc/cpu.h" 16 #include "sysemu/cpus.h" 17 #include "sysemu/dma.h" 18 #include "hw/qdev-properties.h" 19 #include "monitor/monitor.h" 20 #include "hw/ppc/xive.h" 21 #include "hw/ppc/xive2.h" 22 #include "hw/ppc/xive2_regs.h" 23 24 uint32_t xive2_router_get_config(Xive2Router *xrtr) 25 { 26 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 27 28 return xrc->get_config(xrtr); 29 } 30 31 void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf) 32 { 33 if (!xive2_eas_is_valid(eas)) { 34 return; 35 } 36 37 g_string_append_printf(buf, " %08x %s end:%02x/%04x data:%08x\n", 38 lisn, xive2_eas_is_masked(eas) ? "M" : " ", 39 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 40 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 41 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 42 } 43 44 void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, GString *buf) 45 { 46 uint64_t qaddr_base = xive2_end_qaddr(end); 47 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 48 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 49 uint32_t qentries = 1 << (qsize + 10); 50 int i; 51 52 /* 53 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 54 */ 55 g_string_append_printf(buf, " [ "); 56 qindex = (qindex - (width - 1)) & (qentries - 1); 57 for (i = 0; i < width; i++) { 58 uint64_t qaddr = qaddr_base + (qindex << 2); 59 uint32_t qdata = -1; 60 61 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 62 sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { 63 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 64 HWADDR_PRIx "\n", qaddr); 65 return; 66 } 67 g_string_append_printf(buf, "%s%08x ", i == width - 1 ? "^" : "", 68 be32_to_cpu(qdata)); 69 qindex = (qindex + 1) & (qentries - 1); 70 } 71 g_string_append_printf(buf, "]"); 72 } 73 74 void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, Monitor *mon) 75 { 76 uint64_t qaddr_base = xive2_end_qaddr(end); 77 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 78 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 79 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 80 uint32_t qentries = 1 << (qsize + 10); 81 82 uint32_t nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6); 83 uint32_t nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6); 84 uint8_t priority = xive_get_field32(END2_W7_F0_PRIORITY, end->w7); 85 uint8_t pq; 86 87 if (!xive2_end_is_valid(end)) { 88 return; 89 } 90 91 pq = xive_get_field32(END2_W1_ESn, end->w1); 92 93 monitor_printf(mon, 94 " %08x %c%c %c%c%c%c%c%c%c%c%c%c prio:%d nvp:%02x/%04x", 95 end_idx, 96 pq & XIVE_ESB_VAL_P ? 'P' : '-', 97 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 98 xive2_end_is_valid(end) ? 'v' : '-', 99 xive2_end_is_enqueue(end) ? 'q' : '-', 100 xive2_end_is_notify(end) ? 'n' : '-', 101 xive2_end_is_backlog(end) ? 'b' : '-', 102 xive2_end_is_escalate(end) ? 'e' : '-', 103 xive2_end_is_escalate_end(end) ? 'N' : '-', 104 xive2_end_is_uncond_escalation(end) ? 'u' : '-', 105 xive2_end_is_silent_escalation(end) ? 's' : '-', 106 xive2_end_is_firmware1(end) ? 'f' : '-', 107 xive2_end_is_firmware2(end) ? 'F' : '-', 108 priority, nvp_blk, nvp_idx); 109 110 if (qaddr_base) { 111 g_autoptr(GString) buf = g_string_new(""); 112 g_autoptr(HumanReadableText) info = NULL; 113 114 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", 115 qaddr_base, qindex, qentries, qgen); 116 xive2_end_queue_pic_print_info(end, 6, buf); 117 info = human_readable_text_from_str(buf); 118 monitor_puts(mon, info->human_readable_text); 119 } 120 monitor_printf(mon, "\n"); 121 } 122 123 void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx, 124 GString *buf) 125 { 126 Xive2Eas *eas = (Xive2Eas *) &end->w4; 127 uint8_t pq; 128 129 if (!xive2_end_is_escalate(end)) { 130 return; 131 } 132 133 pq = xive_get_field32(END2_W1_ESe, end->w1); 134 135 g_string_append_printf(buf, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 136 end_idx, 137 pq & XIVE_ESB_VAL_P ? 'P' : '-', 138 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 139 xive2_eas_is_valid(eas) ? 'v' : ' ', 140 xive2_eas_is_masked(eas) ? 'M' : ' ', 141 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 142 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 143 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 144 } 145 146 static void xive2_end_enqueue(Xive2End *end, uint32_t data) 147 { 148 uint64_t qaddr_base = xive2_end_qaddr(end); 149 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 150 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 151 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 152 153 uint64_t qaddr = qaddr_base + (qindex << 2); 154 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 155 uint32_t qentries = 1 << (qsize + 10); 156 157 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata), 158 MEMTXATTRS_UNSPECIFIED)) { 159 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 160 HWADDR_PRIx "\n", qaddr); 161 return; 162 } 163 164 qindex = (qindex + 1) & (qentries - 1); 165 if (qindex == 0) { 166 qgen ^= 1; 167 end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen); 168 169 /* TODO(PowerNV): reset GF bit on a cache watch operation */ 170 end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, qgen); 171 } 172 end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex); 173 } 174 175 /* 176 * XIVE Thread Interrupt Management Area (TIMA) - Gen2 mode 177 * 178 * TIMA Gen2 VP “save & restore” (S&R) indicated by H bit next to V bit 179 * 180 * - if a context is enabled with the H bit set, the VP context 181 * information is retrieved from the NVP structure (“check out”) 182 * and stored back on a context pull (“check in”), the SW receives 183 * the same context pull information as on P9 184 * 185 * - the H bit cannot be changed while the V bit is set, i.e. a 186 * context cannot be set up in the TIMA and then be “pushed” into 187 * the NVP by changing the H bit while the context is enabled 188 */ 189 190 static void xive2_tctx_save_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx, 191 uint8_t nvp_blk, uint32_t nvp_idx) 192 { 193 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 194 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 195 Xive2Nvp nvp; 196 uint8_t *regs = &tctx->regs[TM_QW1_OS]; 197 198 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 199 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 200 nvp_blk, nvp_idx); 201 return; 202 } 203 204 if (!xive2_nvp_is_valid(&nvp)) { 205 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 206 nvp_blk, nvp_idx); 207 return; 208 } 209 210 if (!xive2_nvp_is_hw(&nvp)) { 211 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n", 212 nvp_blk, nvp_idx); 213 return; 214 } 215 216 if (!xive2_nvp_is_co(&nvp)) { 217 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not checkout\n", 218 nvp_blk, nvp_idx); 219 return; 220 } 221 222 if (xive_get_field32(NVP2_W1_CO_THRID_VALID, nvp.w1) && 223 xive_get_field32(NVP2_W1_CO_THRID, nvp.w1) != pir) { 224 qemu_log_mask(LOG_GUEST_ERROR, 225 "XIVE: NVP %x/%x invalid checkout Thread %x\n", 226 nvp_blk, nvp_idx, pir); 227 return; 228 } 229 230 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, regs[TM_IPB]); 231 nvp.w2 = xive_set_field32(NVP2_W2_CPPR, nvp.w2, regs[TM_CPPR]); 232 nvp.w2 = xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]); 233 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 234 235 nvp.w1 = xive_set_field32(NVP2_W1_CO, nvp.w1, 0); 236 /* NVP2_W1_CO_THRID_VALID only set once */ 237 nvp.w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp.w1, 0xFFFF); 238 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 1); 239 } 240 241 static void xive2_os_cam_decode(uint32_t cam, uint8_t *nvp_blk, 242 uint32_t *nvp_idx, bool *vo, bool *ho) 243 { 244 *nvp_blk = xive2_nvp_blk(cam); 245 *nvp_idx = xive2_nvp_idx(cam); 246 *vo = !!(cam & TM2_QW1W2_VO); 247 *ho = !!(cam & TM2_QW1W2_HO); 248 } 249 250 uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 251 hwaddr offset, unsigned size) 252 { 253 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 254 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 255 uint32_t qw1w2_new; 256 uint32_t cam = be32_to_cpu(qw1w2); 257 uint8_t nvp_blk; 258 uint32_t nvp_idx; 259 bool vo; 260 bool do_save; 261 262 xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_save); 263 264 if (!vo) { 265 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?\n", 266 nvp_blk, nvp_idx); 267 } 268 269 /* Invalidate CAM line */ 270 qw1w2_new = xive_set_field32(TM2_QW1W2_VO, qw1w2, 0); 271 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4); 272 273 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) { 274 xive2_tctx_save_os_ctx(xrtr, tctx, nvp_blk, nvp_idx); 275 } 276 277 xive_tctx_reset_os_signal(tctx); 278 return qw1w2; 279 } 280 281 static uint8_t xive2_tctx_restore_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx, 282 uint8_t nvp_blk, uint32_t nvp_idx, 283 Xive2Nvp *nvp) 284 { 285 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 286 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 287 uint8_t cppr; 288 289 if (!xive2_nvp_is_hw(nvp)) { 290 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n", 291 nvp_blk, nvp_idx); 292 return 0; 293 } 294 295 cppr = xive_get_field32(NVP2_W2_CPPR, nvp->w2); 296 nvp->w2 = xive_set_field32(NVP2_W2_CPPR, nvp->w2, 0); 297 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 2); 298 299 tctx->regs[TM_QW1_OS + TM_CPPR] = cppr; 300 /* we don't model LSMFB */ 301 302 nvp->w1 = xive_set_field32(NVP2_W1_CO, nvp->w1, 1); 303 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID_VALID, nvp->w1, 1); 304 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp->w1, pir); 305 306 /* 307 * Checkout privilege: 0:OS, 1:Pool, 2:Hard 308 * 309 * TODO: we only support OS push/pull 310 */ 311 nvp->w1 = xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 0); 312 313 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 1); 314 315 /* return restored CPPR to generate a CPU exception if needed */ 316 return cppr; 317 } 318 319 static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx, 320 uint8_t nvp_blk, uint32_t nvp_idx, 321 bool do_restore) 322 { 323 Xive2Nvp nvp; 324 uint8_t ipb; 325 326 /* 327 * Grab the associated thread interrupt context registers in the 328 * associated NVP 329 */ 330 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 331 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 332 nvp_blk, nvp_idx); 333 return; 334 } 335 336 if (!xive2_nvp_is_valid(&nvp)) { 337 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 338 nvp_blk, nvp_idx); 339 return; 340 } 341 342 /* Automatically restore thread context registers */ 343 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && 344 do_restore) { 345 xive2_tctx_restore_os_ctx(xrtr, tctx, nvp_blk, nvp_idx, &nvp); 346 } 347 348 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2); 349 if (ipb) { 350 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, 0); 351 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 352 } 353 /* 354 * Always call xive_tctx_ipb_update(). Even if there were no 355 * escalation triggered, there could be a pending interrupt which 356 * was saved when the context was pulled and that we need to take 357 * into account by recalculating the PIPR (which is not 358 * saved/restored). 359 * It will also raise the External interrupt signal if needed. 360 */ 361 xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb); 362 } 363 364 /* 365 * Updating the OS CAM line can trigger a resend of interrupt 366 */ 367 void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 368 hwaddr offset, uint64_t value, unsigned size) 369 { 370 uint32_t cam = value; 371 uint32_t qw1w2 = cpu_to_be32(cam); 372 uint8_t nvp_blk; 373 uint32_t nvp_idx; 374 bool vo; 375 bool do_restore; 376 377 xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore); 378 379 /* First update the thead context */ 380 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 381 382 /* Check the interrupt pending bits */ 383 if (vo) { 384 xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, nvp_blk, nvp_idx, 385 do_restore); 386 } 387 } 388 389 /* 390 * XIVE Router (aka. Virtualization Controller or IVRE) 391 */ 392 393 int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 394 Xive2Eas *eas) 395 { 396 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 397 398 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 399 } 400 401 static 402 int xive2_router_get_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 403 uint8_t *pq) 404 { 405 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 406 407 return xrc->get_pq(xrtr, eas_blk, eas_idx, pq); 408 } 409 410 static 411 int xive2_router_set_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 412 uint8_t *pq) 413 { 414 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 415 416 return xrc->set_pq(xrtr, eas_blk, eas_idx, pq); 417 } 418 419 int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 420 Xive2End *end) 421 { 422 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 423 424 return xrc->get_end(xrtr, end_blk, end_idx, end); 425 } 426 427 int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 428 Xive2End *end, uint8_t word_number) 429 { 430 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 431 432 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 433 } 434 435 int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 436 Xive2Nvp *nvp) 437 { 438 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 439 440 return xrc->get_nvp(xrtr, nvp_blk, nvp_idx, nvp); 441 } 442 443 int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 444 Xive2Nvp *nvp, uint8_t word_number) 445 { 446 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 447 448 return xrc->write_nvp(xrtr, nvp_blk, nvp_idx, nvp, word_number); 449 } 450 451 static int xive2_router_get_block_id(Xive2Router *xrtr) 452 { 453 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 454 455 return xrc->get_block_id(xrtr); 456 } 457 458 /* 459 * Encode the HW CAM line with 7bit or 8bit thread id. The thread id 460 * width and block id width is configurable at the IC level. 461 * 462 * chipid << 24 | 0000 0000 0000 0000 1 threadid (7Bit) 463 * chipid << 24 | 0000 0000 0000 0001 threadid (8Bit) 464 */ 465 static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 466 { 467 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 468 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 469 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 470 uint8_t blk = xive2_router_get_block_id(xrtr); 471 uint8_t tid_shift = 472 xive2_router_get_config(xrtr) & XIVE2_THREADID_8BITS ? 8 : 7; 473 uint8_t tid_mask = (1 << tid_shift) - 1; 474 475 return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask)); 476 } 477 478 /* 479 * The thread context register words are in big-endian format. 480 */ 481 int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 482 uint8_t format, 483 uint8_t nvt_blk, uint32_t nvt_idx, 484 bool cam_ignore, uint32_t logic_serv) 485 { 486 uint32_t cam = xive2_nvp_cam_line(nvt_blk, nvt_idx); 487 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 488 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 489 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 490 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 491 492 /* 493 * TODO (PowerNV): ignore mode. The low order bits of the NVT 494 * identifier are ignored in the "CAM" match. 495 */ 496 497 if (format == 0) { 498 if (cam_ignore == true) { 499 /* 500 * F=0 & i=1: Logical server notification (bits ignored at 501 * the end of the NVT identifier) 502 */ 503 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 504 nvt_blk, nvt_idx); 505 return -1; 506 } 507 508 /* F=0 & i=0: Specific NVT notification */ 509 510 /* PHYS ring */ 511 if ((be32_to_cpu(qw3w2) & TM2_QW3W2_VT) && 512 cam == xive2_tctx_hw_cam_line(xptr, tctx)) { 513 return TM_QW3_HV_PHYS; 514 } 515 516 /* HV POOL ring */ 517 if ((be32_to_cpu(qw2w2) & TM2_QW2W2_VP) && 518 cam == xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2)) { 519 return TM_QW2_HV_POOL; 520 } 521 522 /* OS ring */ 523 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 524 cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) { 525 return TM_QW1_OS; 526 } 527 } else { 528 /* F=1 : User level Event-Based Branch (EBB) notification */ 529 530 /* USER ring */ 531 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 532 (cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) && 533 (be32_to_cpu(qw0w2) & TM2_QW0W2_VU) && 534 (logic_serv == xive_get_field32(TM2_QW0W2_LOGIC_SERV, qw0w2))) { 535 return TM_QW0_USER; 536 } 537 } 538 return -1; 539 } 540 541 static void xive2_router_realize(DeviceState *dev, Error **errp) 542 { 543 Xive2Router *xrtr = XIVE2_ROUTER(dev); 544 545 assert(xrtr->xfb); 546 } 547 548 /* 549 * Notification using the END ESe/ESn bit (Event State Buffer for 550 * escalation and notification). Profide further coalescing in the 551 * Router. 552 */ 553 static bool xive2_router_end_es_notify(Xive2Router *xrtr, uint8_t end_blk, 554 uint32_t end_idx, Xive2End *end, 555 uint32_t end_esmask) 556 { 557 uint8_t pq = xive_get_field32(end_esmask, end->w1); 558 bool notify = xive_esb_trigger(&pq); 559 560 if (pq != xive_get_field32(end_esmask, end->w1)) { 561 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 562 xive2_router_write_end(xrtr, end_blk, end_idx, end, 1); 563 } 564 565 /* ESe/n[Q]=1 : end of notification */ 566 return notify; 567 } 568 569 /* 570 * An END trigger can come from an event trigger (IPI or HW) or from 571 * another chip. We don't model the PowerBus but the END trigger 572 * message has the same parameters than in the function below. 573 */ 574 static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk, 575 uint32_t end_idx, uint32_t end_data) 576 { 577 Xive2End end; 578 uint8_t priority; 579 uint8_t format; 580 bool found; 581 Xive2Nvp nvp; 582 uint8_t nvp_blk; 583 uint32_t nvp_idx; 584 585 /* END cache lookup */ 586 if (xive2_router_get_end(xrtr, end_blk, end_idx, &end)) { 587 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 588 end_idx); 589 return; 590 } 591 592 if (!xive2_end_is_valid(&end)) { 593 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 594 end_blk, end_idx); 595 return; 596 } 597 598 if (xive2_end_is_enqueue(&end)) { 599 xive2_end_enqueue(&end, end_data); 600 /* Enqueuing event data modifies the EQ toggle and index */ 601 xive2_router_write_end(xrtr, end_blk, end_idx, &end, 1); 602 } 603 604 /* 605 * When the END is silent, we skip the notification part. 606 */ 607 if (xive2_end_is_silent_escalation(&end)) { 608 goto do_escalation; 609 } 610 611 /* 612 * The W7 format depends on the F bit in W6. It defines the type 613 * of the notification : 614 * 615 * F=0 : single or multiple NVP notification 616 * F=1 : User level Event-Based Branch (EBB) notification, no 617 * priority 618 */ 619 format = xive_get_field32(END2_W6_FORMAT_BIT, end.w6); 620 priority = xive_get_field32(END2_W7_F0_PRIORITY, end.w7); 621 622 /* The END is masked */ 623 if (format == 0 && priority == 0xff) { 624 return; 625 } 626 627 /* 628 * Check the END ESn (Event State Buffer for notification) for 629 * even further coalescing in the Router 630 */ 631 if (!xive2_end_is_notify(&end)) { 632 /* ESn[Q]=1 : end of notification */ 633 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 634 &end, END2_W1_ESn)) { 635 return; 636 } 637 } 638 639 /* 640 * Follows IVPE notification 641 */ 642 nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end.w6); 643 nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end.w6); 644 645 /* NVP cache lookup */ 646 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 647 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVP %x/%x\n", 648 nvp_blk, nvp_idx); 649 return; 650 } 651 652 if (!xive2_nvp_is_valid(&nvp)) { 653 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is invalid\n", 654 nvp_blk, nvp_idx); 655 return; 656 } 657 658 found = xive_presenter_notify(xrtr->xfb, format, nvp_blk, nvp_idx, 659 xive_get_field32(END2_W6_IGNORE, end.w7), 660 priority, 661 xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w7)); 662 663 /* TODO: Auto EOI. */ 664 665 if (found) { 666 return; 667 } 668 669 /* 670 * If no matching NVP is dispatched on a HW thread : 671 * - specific VP: update the NVP structure if backlog is activated 672 * - logical server : forward request to IVPE (not supported) 673 */ 674 if (xive2_end_is_backlog(&end)) { 675 uint8_t ipb; 676 677 if (format == 1) { 678 qemu_log_mask(LOG_GUEST_ERROR, 679 "XIVE: END %x/%x invalid config: F1 & backlog\n", 680 end_blk, end_idx); 681 return; 682 } 683 684 /* 685 * Record the IPB in the associated NVP structure for later 686 * use. The presenter will resend the interrupt when the vCPU 687 * is dispatched again on a HW thread. 688 */ 689 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2) | 690 xive_priority_to_ipb(priority); 691 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb); 692 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 693 694 /* 695 * On HW, follows a "Broadcast Backlog" to IVPEs 696 */ 697 } 698 699 do_escalation: 700 /* 701 * If activated, escalate notification using the ESe PQ bits and 702 * the EAS in w4-5 703 */ 704 if (!xive2_end_is_escalate(&end)) { 705 return; 706 } 707 708 /* 709 * Check the END ESe (Event State Buffer for escalation) for even 710 * further coalescing in the Router 711 */ 712 if (!xive2_end_is_uncond_escalation(&end)) { 713 /* ESe[Q]=1 : end of escalation notification */ 714 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 715 &end, END2_W1_ESe)) { 716 return; 717 } 718 } 719 720 /* 721 * The END trigger becomes an Escalation trigger 722 */ 723 xive2_router_end_notify(xrtr, 724 xive_get_field32(END2_W4_END_BLOCK, end.w4), 725 xive_get_field32(END2_W4_ESC_END_INDEX, end.w4), 726 xive_get_field32(END2_W5_ESC_END_DATA, end.w5)); 727 } 728 729 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) 730 { 731 Xive2Router *xrtr = XIVE2_ROUTER(xn); 732 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 733 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 734 Xive2Eas eas; 735 736 /* EAS cache lookup */ 737 if (xive2_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 738 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 739 return; 740 } 741 742 if (!pq_checked) { 743 bool notify; 744 uint8_t pq; 745 746 /* PQ cache lookup */ 747 if (xive2_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) { 748 /* Set FIR */ 749 g_assert_not_reached(); 750 } 751 752 notify = xive_esb_trigger(&pq); 753 754 if (xive2_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) { 755 /* Set FIR */ 756 g_assert_not_reached(); 757 } 758 759 if (!notify) { 760 return; 761 } 762 } 763 764 if (!xive2_eas_is_valid(&eas)) { 765 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %x\n", lisn); 766 return; 767 } 768 769 if (xive2_eas_is_masked(&eas)) { 770 /* Notification completed */ 771 return; 772 } 773 774 /* 775 * The event trigger becomes an END trigger 776 */ 777 xive2_router_end_notify(xrtr, 778 xive_get_field64(EAS2_END_BLOCK, eas.w), 779 xive_get_field64(EAS2_END_INDEX, eas.w), 780 xive_get_field64(EAS2_END_DATA, eas.w)); 781 } 782 783 static Property xive2_router_properties[] = { 784 DEFINE_PROP_LINK("xive-fabric", Xive2Router, xfb, 785 TYPE_XIVE_FABRIC, XiveFabric *), 786 DEFINE_PROP_END_OF_LIST(), 787 }; 788 789 static void xive2_router_class_init(ObjectClass *klass, void *data) 790 { 791 DeviceClass *dc = DEVICE_CLASS(klass); 792 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 793 794 dc->desc = "XIVE2 Router Engine"; 795 device_class_set_props(dc, xive2_router_properties); 796 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 797 dc->realize = xive2_router_realize; 798 xnc->notify = xive2_router_notify; 799 } 800 801 static const TypeInfo xive2_router_info = { 802 .name = TYPE_XIVE2_ROUTER, 803 .parent = TYPE_SYS_BUS_DEVICE, 804 .abstract = true, 805 .instance_size = sizeof(Xive2Router), 806 .class_size = sizeof(Xive2RouterClass), 807 .class_init = xive2_router_class_init, 808 .interfaces = (InterfaceInfo[]) { 809 { TYPE_XIVE_NOTIFIER }, 810 { TYPE_XIVE_PRESENTER }, 811 { } 812 } 813 }; 814 815 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 816 { 817 return !((addr >> shift) & 1); 818 } 819 820 static uint64_t xive2_end_source_read(void *opaque, hwaddr addr, unsigned size) 821 { 822 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 823 uint32_t offset = addr & 0xFFF; 824 uint8_t end_blk; 825 uint32_t end_idx; 826 Xive2End end; 827 uint32_t end_esmask; 828 uint8_t pq; 829 uint64_t ret; 830 831 /* 832 * The block id should be deduced from the load address on the END 833 * ESB MMIO but our model only supports a single block per XIVE chip. 834 */ 835 end_blk = xive2_router_get_block_id(xsrc->xrtr); 836 end_idx = addr >> (xsrc->esb_shift + 1); 837 838 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 839 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 840 end_idx); 841 return -1; 842 } 843 844 if (!xive2_end_is_valid(&end)) { 845 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 846 end_blk, end_idx); 847 return -1; 848 } 849 850 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 851 END2_W1_ESe; 852 pq = xive_get_field32(end_esmask, end.w1); 853 854 switch (offset) { 855 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 856 ret = xive_esb_eoi(&pq); 857 858 /* Forward the source event notification for routing ?? */ 859 break; 860 861 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 862 ret = pq; 863 break; 864 865 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 866 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 867 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 868 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 869 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 870 break; 871 default: 872 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 873 offset); 874 return -1; 875 } 876 877 if (pq != xive_get_field32(end_esmask, end.w1)) { 878 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 879 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 880 } 881 882 return ret; 883 } 884 885 static void xive2_end_source_write(void *opaque, hwaddr addr, 886 uint64_t value, unsigned size) 887 { 888 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 889 uint32_t offset = addr & 0xFFF; 890 uint8_t end_blk; 891 uint32_t end_idx; 892 Xive2End end; 893 uint32_t end_esmask; 894 uint8_t pq; 895 bool notify = false; 896 897 /* 898 * The block id should be deduced from the load address on the END 899 * ESB MMIO but our model only supports a single block per XIVE chip. 900 */ 901 end_blk = xive2_router_get_block_id(xsrc->xrtr); 902 end_idx = addr >> (xsrc->esb_shift + 1); 903 904 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 905 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 906 end_idx); 907 return; 908 } 909 910 if (!xive2_end_is_valid(&end)) { 911 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 912 end_blk, end_idx); 913 return; 914 } 915 916 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 917 END2_W1_ESe; 918 pq = xive_get_field32(end_esmask, end.w1); 919 920 switch (offset) { 921 case 0 ... 0x3FF: 922 notify = xive_esb_trigger(&pq); 923 break; 924 925 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 926 /* TODO: can we check StoreEOI availability from the router ? */ 927 notify = xive_esb_eoi(&pq); 928 break; 929 930 case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF: 931 if (end_esmask == END2_W1_ESe) { 932 qemu_log_mask(LOG_GUEST_ERROR, 933 "XIVE: END %x/%x can not EQ inject on ESe\n", 934 end_blk, end_idx); 935 return; 936 } 937 notify = true; 938 break; 939 940 default: 941 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB write addr %d\n", 942 offset); 943 return; 944 } 945 946 if (pq != xive_get_field32(end_esmask, end.w1)) { 947 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 948 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 949 } 950 951 /* TODO: Forward the source event notification for routing */ 952 if (notify) { 953 ; 954 } 955 } 956 957 static const MemoryRegionOps xive2_end_source_ops = { 958 .read = xive2_end_source_read, 959 .write = xive2_end_source_write, 960 .endianness = DEVICE_BIG_ENDIAN, 961 .valid = { 962 .min_access_size = 1, 963 .max_access_size = 8, 964 }, 965 .impl = { 966 .min_access_size = 1, 967 .max_access_size = 8, 968 }, 969 }; 970 971 static void xive2_end_source_realize(DeviceState *dev, Error **errp) 972 { 973 Xive2EndSource *xsrc = XIVE2_END_SOURCE(dev); 974 975 assert(xsrc->xrtr); 976 977 if (!xsrc->nr_ends) { 978 error_setg(errp, "Number of interrupt needs to be greater than 0"); 979 return; 980 } 981 982 if (xsrc->esb_shift != XIVE_ESB_4K && 983 xsrc->esb_shift != XIVE_ESB_64K) { 984 error_setg(errp, "Invalid ESB shift setting"); 985 return; 986 } 987 988 /* 989 * Each END is assigned an even/odd pair of MMIO pages, the even page 990 * manages the ESn field while the odd page manages the ESe field. 991 */ 992 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 993 &xive2_end_source_ops, xsrc, "xive.end", 994 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 995 } 996 997 static Property xive2_end_source_properties[] = { 998 DEFINE_PROP_UINT32("nr-ends", Xive2EndSource, nr_ends, 0), 999 DEFINE_PROP_UINT32("shift", Xive2EndSource, esb_shift, XIVE_ESB_64K), 1000 DEFINE_PROP_LINK("xive", Xive2EndSource, xrtr, TYPE_XIVE2_ROUTER, 1001 Xive2Router *), 1002 DEFINE_PROP_END_OF_LIST(), 1003 }; 1004 1005 static void xive2_end_source_class_init(ObjectClass *klass, void *data) 1006 { 1007 DeviceClass *dc = DEVICE_CLASS(klass); 1008 1009 dc->desc = "XIVE END Source"; 1010 device_class_set_props(dc, xive2_end_source_properties); 1011 dc->realize = xive2_end_source_realize; 1012 dc->user_creatable = false; 1013 } 1014 1015 static const TypeInfo xive2_end_source_info = { 1016 .name = TYPE_XIVE2_END_SOURCE, 1017 .parent = TYPE_DEVICE, 1018 .instance_size = sizeof(Xive2EndSource), 1019 .class_init = xive2_end_source_class_init, 1020 }; 1021 1022 static void xive2_register_types(void) 1023 { 1024 type_register_static(&xive2_router_info); 1025 type_register_static(&xive2_end_source_info); 1026 } 1027 1028 type_init(xive2_register_types) 1029