1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2022, IBM Corporation.. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "hw/qdev-properties.h" 18 #include "monitor/monitor.h" 19 #include "hw/ppc/xive.h" 20 #include "hw/ppc/xive2.h" 21 #include "hw/ppc/xive2_regs.h" 22 23 void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, Monitor *mon) 24 { 25 if (!xive2_eas_is_valid(eas)) { 26 return; 27 } 28 29 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 30 lisn, xive2_eas_is_masked(eas) ? "M" : " ", 31 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 32 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 33 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 34 } 35 36 void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, 37 Monitor *mon) 38 { 39 uint64_t qaddr_base = xive2_end_qaddr(end); 40 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 41 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 42 uint32_t qentries = 1 << (qsize + 10); 43 int i; 44 45 /* 46 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 47 */ 48 monitor_printf(mon, " [ "); 49 qindex = (qindex - (width - 1)) & (qentries - 1); 50 for (i = 0; i < width; i++) { 51 uint64_t qaddr = qaddr_base + (qindex << 2); 52 uint32_t qdata = -1; 53 54 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 55 sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { 56 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 57 HWADDR_PRIx "\n", qaddr); 58 return; 59 } 60 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 61 be32_to_cpu(qdata)); 62 qindex = (qindex + 1) & (qentries - 1); 63 } 64 monitor_printf(mon, "]"); 65 } 66 67 void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, Monitor *mon) 68 { 69 uint64_t qaddr_base = xive2_end_qaddr(end); 70 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 71 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 72 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 73 uint32_t qentries = 1 << (qsize + 10); 74 75 uint32_t nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6); 76 uint32_t nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6); 77 uint8_t priority = xive_get_field32(END2_W7_F0_PRIORITY, end->w7); 78 uint8_t pq; 79 80 if (!xive2_end_is_valid(end)) { 81 return; 82 } 83 84 pq = xive_get_field32(END2_W1_ESn, end->w1); 85 86 monitor_printf(mon, 87 " %08x %c%c %c%c%c%c%c%c%c%c%c%c prio:%d nvp:%02x/%04x", 88 end_idx, 89 pq & XIVE_ESB_VAL_P ? 'P' : '-', 90 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 91 xive2_end_is_valid(end) ? 'v' : '-', 92 xive2_end_is_enqueue(end) ? 'q' : '-', 93 xive2_end_is_notify(end) ? 'n' : '-', 94 xive2_end_is_backlog(end) ? 'b' : '-', 95 xive2_end_is_escalate(end) ? 'e' : '-', 96 xive2_end_is_escalate_end(end) ? 'N' : '-', 97 xive2_end_is_uncond_escalation(end) ? 'u' : '-', 98 xive2_end_is_silent_escalation(end) ? 's' : '-', 99 xive2_end_is_firmware1(end) ? 'f' : '-', 100 xive2_end_is_firmware2(end) ? 'F' : '-', 101 priority, nvp_blk, nvp_idx); 102 103 if (qaddr_base) { 104 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", 105 qaddr_base, qindex, qentries, qgen); 106 xive2_end_queue_pic_print_info(end, 6, mon); 107 } 108 monitor_printf(mon, "\n"); 109 } 110 111 void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx, 112 Monitor *mon) 113 { 114 Xive2Eas *eas = (Xive2Eas *) &end->w4; 115 uint8_t pq; 116 117 if (!xive2_end_is_escalate(end)) { 118 return; 119 } 120 121 pq = xive_get_field32(END2_W1_ESe, end->w1); 122 123 monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 124 end_idx, 125 pq & XIVE_ESB_VAL_P ? 'P' : '-', 126 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 127 xive2_eas_is_valid(eas) ? 'v' : ' ', 128 xive2_eas_is_masked(eas) ? 'M' : ' ', 129 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 130 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 131 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 132 } 133 134 static void xive2_end_enqueue(Xive2End *end, uint32_t data) 135 { 136 uint64_t qaddr_base = xive2_end_qaddr(end); 137 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 138 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 139 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 140 141 uint64_t qaddr = qaddr_base + (qindex << 2); 142 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 143 uint32_t qentries = 1 << (qsize + 10); 144 145 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata), 146 MEMTXATTRS_UNSPECIFIED)) { 147 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 148 HWADDR_PRIx "\n", qaddr); 149 return; 150 } 151 152 qindex = (qindex + 1) & (qentries - 1); 153 if (qindex == 0) { 154 qgen ^= 1; 155 end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen); 156 157 /* TODO(PowerNV): reset GF bit on a cache watch operation */ 158 end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, qgen); 159 } 160 end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex); 161 } 162 /* 163 * XIVE Router (aka. Virtualization Controller or IVRE) 164 */ 165 166 int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 167 Xive2Eas *eas) 168 { 169 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 170 171 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 172 } 173 174 int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 175 Xive2End *end) 176 { 177 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 178 179 return xrc->get_end(xrtr, end_blk, end_idx, end); 180 } 181 182 int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 183 Xive2End *end, uint8_t word_number) 184 { 185 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 186 187 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 188 } 189 190 int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 191 Xive2Nvp *nvp) 192 { 193 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 194 195 return xrc->get_nvp(xrtr, nvp_blk, nvp_idx, nvp); 196 } 197 198 int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 199 Xive2Nvp *nvp, uint8_t word_number) 200 { 201 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 202 203 return xrc->write_nvp(xrtr, nvp_blk, nvp_idx, nvp, word_number); 204 } 205 206 static int xive2_router_get_block_id(Xive2Router *xrtr) 207 { 208 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 209 210 return xrc->get_block_id(xrtr); 211 } 212 213 static void xive2_router_realize(DeviceState *dev, Error **errp) 214 { 215 Xive2Router *xrtr = XIVE2_ROUTER(dev); 216 217 assert(xrtr->xfb); 218 } 219 220 /* 221 * Notification using the END ESe/ESn bit (Event State Buffer for 222 * escalation and notification). Profide futher coalescing in the 223 * Router. 224 */ 225 static bool xive2_router_end_es_notify(Xive2Router *xrtr, uint8_t end_blk, 226 uint32_t end_idx, Xive2End *end, 227 uint32_t end_esmask) 228 { 229 uint8_t pq = xive_get_field32(end_esmask, end->w1); 230 bool notify = xive_esb_trigger(&pq); 231 232 if (pq != xive_get_field32(end_esmask, end->w1)) { 233 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 234 xive2_router_write_end(xrtr, end_blk, end_idx, end, 1); 235 } 236 237 /* ESe/n[Q]=1 : end of notification */ 238 return notify; 239 } 240 241 /* 242 * An END trigger can come from an event trigger (IPI or HW) or from 243 * another chip. We don't model the PowerBus but the END trigger 244 * message has the same parameters than in the function below. 245 */ 246 static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk, 247 uint32_t end_idx, uint32_t end_data) 248 { 249 Xive2End end; 250 uint8_t priority; 251 uint8_t format; 252 bool found; 253 Xive2Nvp nvp; 254 uint8_t nvp_blk; 255 uint32_t nvp_idx; 256 257 /* END cache lookup */ 258 if (xive2_router_get_end(xrtr, end_blk, end_idx, &end)) { 259 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 260 end_idx); 261 return; 262 } 263 264 if (!xive2_end_is_valid(&end)) { 265 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 266 end_blk, end_idx); 267 return; 268 } 269 270 if (xive2_end_is_enqueue(&end)) { 271 xive2_end_enqueue(&end, end_data); 272 /* Enqueuing event data modifies the EQ toggle and index */ 273 xive2_router_write_end(xrtr, end_blk, end_idx, &end, 1); 274 } 275 276 /* 277 * When the END is silent, we skip the notification part. 278 */ 279 if (xive2_end_is_silent_escalation(&end)) { 280 goto do_escalation; 281 } 282 283 /* 284 * The W7 format depends on the F bit in W6. It defines the type 285 * of the notification : 286 * 287 * F=0 : single or multiple NVP notification 288 * F=1 : User level Event-Based Branch (EBB) notification, no 289 * priority 290 */ 291 format = xive_get_field32(END2_W6_FORMAT_BIT, end.w6); 292 priority = xive_get_field32(END2_W7_F0_PRIORITY, end.w7); 293 294 /* The END is masked */ 295 if (format == 0 && priority == 0xff) { 296 return; 297 } 298 299 /* 300 * Check the END ESn (Event State Buffer for notification) for 301 * even futher coalescing in the Router 302 */ 303 if (!xive2_end_is_notify(&end)) { 304 /* ESn[Q]=1 : end of notification */ 305 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 306 &end, END2_W1_ESn)) { 307 return; 308 } 309 } 310 311 /* 312 * Follows IVPE notification 313 */ 314 nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end.w6); 315 nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end.w6); 316 317 /* NVP cache lookup */ 318 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 319 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVP %x/%x\n", 320 nvp_blk, nvp_idx); 321 return; 322 } 323 324 if (!xive2_nvp_is_valid(&nvp)) { 325 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is invalid\n", 326 nvp_blk, nvp_idx); 327 return; 328 } 329 330 found = xive_presenter_notify(xrtr->xfb, format, nvp_blk, nvp_idx, 331 xive_get_field32(END2_W6_IGNORE, end.w7), 332 priority, 333 xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w7)); 334 335 /* TODO: Auto EOI. */ 336 337 if (found) { 338 return; 339 } 340 341 /* 342 * If no matching NVP is dispatched on a HW thread : 343 * - specific VP: update the NVP structure if backlog is activated 344 * - logical server : forward request to IVPE (not supported) 345 */ 346 if (xive2_end_is_backlog(&end)) { 347 uint8_t ipb; 348 349 if (format == 1) { 350 qemu_log_mask(LOG_GUEST_ERROR, 351 "XIVE: END %x/%x invalid config: F1 & backlog\n", 352 end_blk, end_idx); 353 return; 354 } 355 356 /* 357 * Record the IPB in the associated NVP structure for later 358 * use. The presenter will resend the interrupt when the vCPU 359 * is dispatched again on a HW thread. 360 */ 361 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2) | 362 xive_priority_to_ipb(priority); 363 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb); 364 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 365 366 /* 367 * On HW, follows a "Broadcast Backlog" to IVPEs 368 */ 369 } 370 371 do_escalation: 372 /* 373 * If activated, escalate notification using the ESe PQ bits and 374 * the EAS in w4-5 375 */ 376 if (!xive2_end_is_escalate(&end)) { 377 return; 378 } 379 380 /* 381 * Check the END ESe (Event State Buffer for escalation) for even 382 * futher coalescing in the Router 383 */ 384 if (!xive2_end_is_uncond_escalation(&end)) { 385 /* ESe[Q]=1 : end of escalation notification */ 386 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 387 &end, END2_W1_ESe)) { 388 return; 389 } 390 } 391 392 /* 393 * The END trigger becomes an Escalation trigger 394 */ 395 xive2_router_end_notify(xrtr, 396 xive_get_field32(END2_W4_END_BLOCK, end.w4), 397 xive_get_field32(END2_W4_ESC_END_INDEX, end.w4), 398 xive_get_field32(END2_W5_ESC_END_DATA, end.w5)); 399 } 400 401 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn) 402 { 403 Xive2Router *xrtr = XIVE2_ROUTER(xn); 404 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 405 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 406 Xive2Eas eas; 407 408 /* EAS cache lookup */ 409 if (xive2_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 410 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 411 return; 412 } 413 414 if (!xive2_eas_is_valid(&eas)) { 415 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %x\n", lisn); 416 return; 417 } 418 419 if (xive2_eas_is_masked(&eas)) { 420 /* Notification completed */ 421 return; 422 } 423 424 /* 425 * The event trigger becomes an END trigger 426 */ 427 xive2_router_end_notify(xrtr, 428 xive_get_field64(EAS2_END_BLOCK, eas.w), 429 xive_get_field64(EAS2_END_INDEX, eas.w), 430 xive_get_field64(EAS2_END_DATA, eas.w)); 431 } 432 433 static Property xive2_router_properties[] = { 434 DEFINE_PROP_LINK("xive-fabric", Xive2Router, xfb, 435 TYPE_XIVE_FABRIC, XiveFabric *), 436 DEFINE_PROP_END_OF_LIST(), 437 }; 438 439 static void xive2_router_class_init(ObjectClass *klass, void *data) 440 { 441 DeviceClass *dc = DEVICE_CLASS(klass); 442 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 443 444 dc->desc = "XIVE2 Router Engine"; 445 device_class_set_props(dc, xive2_router_properties); 446 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 447 dc->realize = xive2_router_realize; 448 xnc->notify = xive2_router_notify; 449 } 450 451 static const TypeInfo xive2_router_info = { 452 .name = TYPE_XIVE2_ROUTER, 453 .parent = TYPE_SYS_BUS_DEVICE, 454 .abstract = true, 455 .instance_size = sizeof(Xive2Router), 456 .class_size = sizeof(Xive2RouterClass), 457 .class_init = xive2_router_class_init, 458 .interfaces = (InterfaceInfo[]) { 459 { TYPE_XIVE_NOTIFIER }, 460 { TYPE_XIVE_PRESENTER }, 461 { } 462 } 463 }; 464 465 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 466 { 467 return !((addr >> shift) & 1); 468 } 469 470 static uint64_t xive2_end_source_read(void *opaque, hwaddr addr, unsigned size) 471 { 472 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 473 uint32_t offset = addr & 0xFFF; 474 uint8_t end_blk; 475 uint32_t end_idx; 476 Xive2End end; 477 uint32_t end_esmask; 478 uint8_t pq; 479 uint64_t ret; 480 481 /* 482 * The block id should be deduced from the load address on the END 483 * ESB MMIO but our model only supports a single block per XIVE chip. 484 */ 485 end_blk = xive2_router_get_block_id(xsrc->xrtr); 486 end_idx = addr >> (xsrc->esb_shift + 1); 487 488 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 489 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 490 end_idx); 491 return -1; 492 } 493 494 if (!xive2_end_is_valid(&end)) { 495 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 496 end_blk, end_idx); 497 return -1; 498 } 499 500 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 501 END2_W1_ESe; 502 pq = xive_get_field32(end_esmask, end.w1); 503 504 switch (offset) { 505 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 506 ret = xive_esb_eoi(&pq); 507 508 /* Forward the source event notification for routing ?? */ 509 break; 510 511 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 512 ret = pq; 513 break; 514 515 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 516 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 517 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 518 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 519 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 520 break; 521 default: 522 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 523 offset); 524 return -1; 525 } 526 527 if (pq != xive_get_field32(end_esmask, end.w1)) { 528 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 529 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 530 } 531 532 return ret; 533 } 534 535 static void xive2_end_source_write(void *opaque, hwaddr addr, 536 uint64_t value, unsigned size) 537 { 538 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 539 uint32_t offset = addr & 0xFFF; 540 uint8_t end_blk; 541 uint32_t end_idx; 542 Xive2End end; 543 uint32_t end_esmask; 544 uint8_t pq; 545 bool notify = false; 546 547 /* 548 * The block id should be deduced from the load address on the END 549 * ESB MMIO but our model only supports a single block per XIVE chip. 550 */ 551 end_blk = xive2_router_get_block_id(xsrc->xrtr); 552 end_idx = addr >> (xsrc->esb_shift + 1); 553 554 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 555 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 556 end_idx); 557 return; 558 } 559 560 if (!xive2_end_is_valid(&end)) { 561 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 562 end_blk, end_idx); 563 return; 564 } 565 566 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 567 END2_W1_ESe; 568 pq = xive_get_field32(end_esmask, end.w1); 569 570 switch (offset) { 571 case 0 ... 0x3FF: 572 notify = xive_esb_trigger(&pq); 573 break; 574 575 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 576 /* TODO: can we check StoreEOI availability from the router ? */ 577 notify = xive_esb_eoi(&pq); 578 break; 579 580 default: 581 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB write addr %d\n", 582 offset); 583 return; 584 } 585 586 if (pq != xive_get_field32(end_esmask, end.w1)) { 587 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 588 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 589 } 590 591 /* TODO: Forward the source event notification for routing */ 592 if (notify) { 593 ; 594 } 595 } 596 597 static const MemoryRegionOps xive2_end_source_ops = { 598 .read = xive2_end_source_read, 599 .write = xive2_end_source_write, 600 .endianness = DEVICE_BIG_ENDIAN, 601 .valid = { 602 .min_access_size = 8, 603 .max_access_size = 8, 604 }, 605 .impl = { 606 .min_access_size = 8, 607 .max_access_size = 8, 608 }, 609 }; 610 611 static void xive2_end_source_realize(DeviceState *dev, Error **errp) 612 { 613 Xive2EndSource *xsrc = XIVE2_END_SOURCE(dev); 614 615 assert(xsrc->xrtr); 616 617 if (!xsrc->nr_ends) { 618 error_setg(errp, "Number of interrupt needs to be greater than 0"); 619 return; 620 } 621 622 if (xsrc->esb_shift != XIVE_ESB_4K && 623 xsrc->esb_shift != XIVE_ESB_64K) { 624 error_setg(errp, "Invalid ESB shift setting"); 625 return; 626 } 627 628 /* 629 * Each END is assigned an even/odd pair of MMIO pages, the even page 630 * manages the ESn field while the odd page manages the ESe field. 631 */ 632 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 633 &xive2_end_source_ops, xsrc, "xive.end", 634 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 635 } 636 637 static Property xive2_end_source_properties[] = { 638 DEFINE_PROP_UINT32("nr-ends", Xive2EndSource, nr_ends, 0), 639 DEFINE_PROP_UINT32("shift", Xive2EndSource, esb_shift, XIVE_ESB_64K), 640 DEFINE_PROP_LINK("xive", Xive2EndSource, xrtr, TYPE_XIVE2_ROUTER, 641 Xive2Router *), 642 DEFINE_PROP_END_OF_LIST(), 643 }; 644 645 static void xive2_end_source_class_init(ObjectClass *klass, void *data) 646 { 647 DeviceClass *dc = DEVICE_CLASS(klass); 648 649 dc->desc = "XIVE END Source"; 650 device_class_set_props(dc, xive2_end_source_properties); 651 dc->realize = xive2_end_source_realize; 652 } 653 654 static const TypeInfo xive2_end_source_info = { 655 .name = TYPE_XIVE2_END_SOURCE, 656 .parent = TYPE_DEVICE, 657 .instance_size = sizeof(Xive2EndSource), 658 .class_init = xive2_end_source_class_init, 659 }; 660 661 static void xive2_register_types(void) 662 { 663 type_register_static(&xive2_router_info); 664 type_register_static(&xive2_end_source_info); 665 } 666 667 type_init(xive2_register_types) 668