1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2022, IBM Corporation.. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "hw/qdev-properties.h" 18 #include "monitor/monitor.h" 19 #include "hw/ppc/xive.h" 20 #include "hw/ppc/xive2.h" 21 #include "hw/ppc/xive2_regs.h" 22 23 void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, Monitor *mon) 24 { 25 if (!xive2_eas_is_valid(eas)) { 26 return; 27 } 28 29 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 30 lisn, xive2_eas_is_masked(eas) ? "M" : " ", 31 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 32 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 33 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 34 } 35 36 void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, 37 Monitor *mon) 38 { 39 uint64_t qaddr_base = xive2_end_qaddr(end); 40 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 41 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 42 uint32_t qentries = 1 << (qsize + 10); 43 int i; 44 45 /* 46 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 47 */ 48 monitor_printf(mon, " [ "); 49 qindex = (qindex - (width - 1)) & (qentries - 1); 50 for (i = 0; i < width; i++) { 51 uint64_t qaddr = qaddr_base + (qindex << 2); 52 uint32_t qdata = -1; 53 54 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 55 sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { 56 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 57 HWADDR_PRIx "\n", qaddr); 58 return; 59 } 60 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 61 be32_to_cpu(qdata)); 62 qindex = (qindex + 1) & (qentries - 1); 63 } 64 monitor_printf(mon, "]"); 65 } 66 67 void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, Monitor *mon) 68 { 69 uint64_t qaddr_base = xive2_end_qaddr(end); 70 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 71 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 72 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 73 uint32_t qentries = 1 << (qsize + 10); 74 75 uint32_t nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6); 76 uint32_t nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6); 77 uint8_t priority = xive_get_field32(END2_W7_F0_PRIORITY, end->w7); 78 uint8_t pq; 79 80 if (!xive2_end_is_valid(end)) { 81 return; 82 } 83 84 pq = xive_get_field32(END2_W1_ESn, end->w1); 85 86 monitor_printf(mon, 87 " %08x %c%c %c%c%c%c%c%c%c%c%c%c prio:%d nvp:%02x/%04x", 88 end_idx, 89 pq & XIVE_ESB_VAL_P ? 'P' : '-', 90 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 91 xive2_end_is_valid(end) ? 'v' : '-', 92 xive2_end_is_enqueue(end) ? 'q' : '-', 93 xive2_end_is_notify(end) ? 'n' : '-', 94 xive2_end_is_backlog(end) ? 'b' : '-', 95 xive2_end_is_escalate(end) ? 'e' : '-', 96 xive2_end_is_escalate_end(end) ? 'N' : '-', 97 xive2_end_is_uncond_escalation(end) ? 'u' : '-', 98 xive2_end_is_silent_escalation(end) ? 's' : '-', 99 xive2_end_is_firmware1(end) ? 'f' : '-', 100 xive2_end_is_firmware2(end) ? 'F' : '-', 101 priority, nvp_blk, nvp_idx); 102 103 if (qaddr_base) { 104 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", 105 qaddr_base, qindex, qentries, qgen); 106 xive2_end_queue_pic_print_info(end, 6, mon); 107 } 108 monitor_printf(mon, "\n"); 109 } 110 111 void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx, 112 Monitor *mon) 113 { 114 Xive2Eas *eas = (Xive2Eas *) &end->w4; 115 uint8_t pq; 116 117 if (!xive2_end_is_escalate(end)) { 118 return; 119 } 120 121 pq = xive_get_field32(END2_W1_ESe, end->w1); 122 123 monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 124 end_idx, 125 pq & XIVE_ESB_VAL_P ? 'P' : '-', 126 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 127 xive2_eas_is_valid(eas) ? 'v' : ' ', 128 xive2_eas_is_masked(eas) ? 'M' : ' ', 129 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 130 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 131 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 132 } 133 134 static void xive2_end_enqueue(Xive2End *end, uint32_t data) 135 { 136 uint64_t qaddr_base = xive2_end_qaddr(end); 137 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 138 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 139 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 140 141 uint64_t qaddr = qaddr_base + (qindex << 2); 142 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 143 uint32_t qentries = 1 << (qsize + 10); 144 145 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata), 146 MEMTXATTRS_UNSPECIFIED)) { 147 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 148 HWADDR_PRIx "\n", qaddr); 149 return; 150 } 151 152 qindex = (qindex + 1) & (qentries - 1); 153 if (qindex == 0) { 154 qgen ^= 1; 155 end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen); 156 157 /* TODO(PowerNV): reset GF bit on a cache watch operation */ 158 end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, qgen); 159 } 160 end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex); 161 } 162 /* 163 * XIVE Router (aka. Virtualization Controller or IVRE) 164 */ 165 166 int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 167 Xive2Eas *eas) 168 { 169 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 170 171 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 172 } 173 174 int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 175 Xive2End *end) 176 { 177 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 178 179 return xrc->get_end(xrtr, end_blk, end_idx, end); 180 } 181 182 int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 183 Xive2End *end, uint8_t word_number) 184 { 185 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 186 187 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 188 } 189 190 int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 191 Xive2Nvp *nvp) 192 { 193 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 194 195 return xrc->get_nvp(xrtr, nvp_blk, nvp_idx, nvp); 196 } 197 198 int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 199 Xive2Nvp *nvp, uint8_t word_number) 200 { 201 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 202 203 return xrc->write_nvp(xrtr, nvp_blk, nvp_idx, nvp, word_number); 204 } 205 206 static int xive2_router_get_block_id(Xive2Router *xrtr) 207 { 208 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 209 210 return xrc->get_block_id(xrtr); 211 } 212 213 /* 214 * Encode the HW CAM line with 7bit or 8bit thread id. The thread id 215 * width and block id width is configurable at the IC level. 216 * 217 * chipid << 24 | 0000 0000 0000 0000 1 threadid (7Bit) 218 * chipid << 24 | 0000 0000 0000 0001 threadid (8Bit) 219 */ 220 static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 221 { 222 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 223 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 224 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 225 uint8_t blk = xive2_router_get_block_id(xrtr); 226 uint8_t tid_shift = 7; 227 uint8_t tid_mask = (1 << tid_shift) - 1; 228 229 return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask)); 230 } 231 232 /* 233 * The thread context register words are in big-endian format. 234 */ 235 int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 236 uint8_t format, 237 uint8_t nvt_blk, uint32_t nvt_idx, 238 bool cam_ignore, uint32_t logic_serv) 239 { 240 uint32_t cam = xive2_nvp_cam_line(nvt_blk, nvt_idx); 241 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 242 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 243 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 244 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 245 246 /* 247 * TODO (PowerNV): ignore mode. The low order bits of the NVT 248 * identifier are ignored in the "CAM" match. 249 */ 250 251 if (format == 0) { 252 if (cam_ignore == true) { 253 /* 254 * F=0 & i=1: Logical server notification (bits ignored at 255 * the end of the NVT identifier) 256 */ 257 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 258 nvt_blk, nvt_idx); 259 return -1; 260 } 261 262 /* F=0 & i=0: Specific NVT notification */ 263 264 /* PHYS ring */ 265 if ((be32_to_cpu(qw3w2) & TM2_QW3W2_VT) && 266 cam == xive2_tctx_hw_cam_line(xptr, tctx)) { 267 return TM_QW3_HV_PHYS; 268 } 269 270 /* HV POOL ring */ 271 if ((be32_to_cpu(qw2w2) & TM2_QW2W2_VP) && 272 cam == xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2)) { 273 return TM_QW2_HV_POOL; 274 } 275 276 /* OS ring */ 277 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 278 cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) { 279 return TM_QW1_OS; 280 } 281 } else { 282 /* F=1 : User level Event-Based Branch (EBB) notification */ 283 284 /* USER ring */ 285 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 286 (cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) && 287 (be32_to_cpu(qw0w2) & TM2_QW0W2_VU) && 288 (logic_serv == xive_get_field32(TM2_QW0W2_LOGIC_SERV, qw0w2))) { 289 return TM_QW0_USER; 290 } 291 } 292 return -1; 293 } 294 295 static void xive2_router_realize(DeviceState *dev, Error **errp) 296 { 297 Xive2Router *xrtr = XIVE2_ROUTER(dev); 298 299 assert(xrtr->xfb); 300 } 301 302 /* 303 * Notification using the END ESe/ESn bit (Event State Buffer for 304 * escalation and notification). Profide futher coalescing in the 305 * Router. 306 */ 307 static bool xive2_router_end_es_notify(Xive2Router *xrtr, uint8_t end_blk, 308 uint32_t end_idx, Xive2End *end, 309 uint32_t end_esmask) 310 { 311 uint8_t pq = xive_get_field32(end_esmask, end->w1); 312 bool notify = xive_esb_trigger(&pq); 313 314 if (pq != xive_get_field32(end_esmask, end->w1)) { 315 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 316 xive2_router_write_end(xrtr, end_blk, end_idx, end, 1); 317 } 318 319 /* ESe/n[Q]=1 : end of notification */ 320 return notify; 321 } 322 323 /* 324 * An END trigger can come from an event trigger (IPI or HW) or from 325 * another chip. We don't model the PowerBus but the END trigger 326 * message has the same parameters than in the function below. 327 */ 328 static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk, 329 uint32_t end_idx, uint32_t end_data) 330 { 331 Xive2End end; 332 uint8_t priority; 333 uint8_t format; 334 bool found; 335 Xive2Nvp nvp; 336 uint8_t nvp_blk; 337 uint32_t nvp_idx; 338 339 /* END cache lookup */ 340 if (xive2_router_get_end(xrtr, end_blk, end_idx, &end)) { 341 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 342 end_idx); 343 return; 344 } 345 346 if (!xive2_end_is_valid(&end)) { 347 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 348 end_blk, end_idx); 349 return; 350 } 351 352 if (xive2_end_is_enqueue(&end)) { 353 xive2_end_enqueue(&end, end_data); 354 /* Enqueuing event data modifies the EQ toggle and index */ 355 xive2_router_write_end(xrtr, end_blk, end_idx, &end, 1); 356 } 357 358 /* 359 * When the END is silent, we skip the notification part. 360 */ 361 if (xive2_end_is_silent_escalation(&end)) { 362 goto do_escalation; 363 } 364 365 /* 366 * The W7 format depends on the F bit in W6. It defines the type 367 * of the notification : 368 * 369 * F=0 : single or multiple NVP notification 370 * F=1 : User level Event-Based Branch (EBB) notification, no 371 * priority 372 */ 373 format = xive_get_field32(END2_W6_FORMAT_BIT, end.w6); 374 priority = xive_get_field32(END2_W7_F0_PRIORITY, end.w7); 375 376 /* The END is masked */ 377 if (format == 0 && priority == 0xff) { 378 return; 379 } 380 381 /* 382 * Check the END ESn (Event State Buffer for notification) for 383 * even futher coalescing in the Router 384 */ 385 if (!xive2_end_is_notify(&end)) { 386 /* ESn[Q]=1 : end of notification */ 387 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 388 &end, END2_W1_ESn)) { 389 return; 390 } 391 } 392 393 /* 394 * Follows IVPE notification 395 */ 396 nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end.w6); 397 nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end.w6); 398 399 /* NVP cache lookup */ 400 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 401 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVP %x/%x\n", 402 nvp_blk, nvp_idx); 403 return; 404 } 405 406 if (!xive2_nvp_is_valid(&nvp)) { 407 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is invalid\n", 408 nvp_blk, nvp_idx); 409 return; 410 } 411 412 found = xive_presenter_notify(xrtr->xfb, format, nvp_blk, nvp_idx, 413 xive_get_field32(END2_W6_IGNORE, end.w7), 414 priority, 415 xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w7)); 416 417 /* TODO: Auto EOI. */ 418 419 if (found) { 420 return; 421 } 422 423 /* 424 * If no matching NVP is dispatched on a HW thread : 425 * - specific VP: update the NVP structure if backlog is activated 426 * - logical server : forward request to IVPE (not supported) 427 */ 428 if (xive2_end_is_backlog(&end)) { 429 uint8_t ipb; 430 431 if (format == 1) { 432 qemu_log_mask(LOG_GUEST_ERROR, 433 "XIVE: END %x/%x invalid config: F1 & backlog\n", 434 end_blk, end_idx); 435 return; 436 } 437 438 /* 439 * Record the IPB in the associated NVP structure for later 440 * use. The presenter will resend the interrupt when the vCPU 441 * is dispatched again on a HW thread. 442 */ 443 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2) | 444 xive_priority_to_ipb(priority); 445 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb); 446 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 447 448 /* 449 * On HW, follows a "Broadcast Backlog" to IVPEs 450 */ 451 } 452 453 do_escalation: 454 /* 455 * If activated, escalate notification using the ESe PQ bits and 456 * the EAS in w4-5 457 */ 458 if (!xive2_end_is_escalate(&end)) { 459 return; 460 } 461 462 /* 463 * Check the END ESe (Event State Buffer for escalation) for even 464 * futher coalescing in the Router 465 */ 466 if (!xive2_end_is_uncond_escalation(&end)) { 467 /* ESe[Q]=1 : end of escalation notification */ 468 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 469 &end, END2_W1_ESe)) { 470 return; 471 } 472 } 473 474 /* 475 * The END trigger becomes an Escalation trigger 476 */ 477 xive2_router_end_notify(xrtr, 478 xive_get_field32(END2_W4_END_BLOCK, end.w4), 479 xive_get_field32(END2_W4_ESC_END_INDEX, end.w4), 480 xive_get_field32(END2_W5_ESC_END_DATA, end.w5)); 481 } 482 483 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn) 484 { 485 Xive2Router *xrtr = XIVE2_ROUTER(xn); 486 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 487 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 488 Xive2Eas eas; 489 490 /* EAS cache lookup */ 491 if (xive2_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 492 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 493 return; 494 } 495 496 if (!xive2_eas_is_valid(&eas)) { 497 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %x\n", lisn); 498 return; 499 } 500 501 if (xive2_eas_is_masked(&eas)) { 502 /* Notification completed */ 503 return; 504 } 505 506 /* 507 * The event trigger becomes an END trigger 508 */ 509 xive2_router_end_notify(xrtr, 510 xive_get_field64(EAS2_END_BLOCK, eas.w), 511 xive_get_field64(EAS2_END_INDEX, eas.w), 512 xive_get_field64(EAS2_END_DATA, eas.w)); 513 } 514 515 static Property xive2_router_properties[] = { 516 DEFINE_PROP_LINK("xive-fabric", Xive2Router, xfb, 517 TYPE_XIVE_FABRIC, XiveFabric *), 518 DEFINE_PROP_END_OF_LIST(), 519 }; 520 521 static void xive2_router_class_init(ObjectClass *klass, void *data) 522 { 523 DeviceClass *dc = DEVICE_CLASS(klass); 524 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 525 526 dc->desc = "XIVE2 Router Engine"; 527 device_class_set_props(dc, xive2_router_properties); 528 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 529 dc->realize = xive2_router_realize; 530 xnc->notify = xive2_router_notify; 531 } 532 533 static const TypeInfo xive2_router_info = { 534 .name = TYPE_XIVE2_ROUTER, 535 .parent = TYPE_SYS_BUS_DEVICE, 536 .abstract = true, 537 .instance_size = sizeof(Xive2Router), 538 .class_size = sizeof(Xive2RouterClass), 539 .class_init = xive2_router_class_init, 540 .interfaces = (InterfaceInfo[]) { 541 { TYPE_XIVE_NOTIFIER }, 542 { TYPE_XIVE_PRESENTER }, 543 { } 544 } 545 }; 546 547 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 548 { 549 return !((addr >> shift) & 1); 550 } 551 552 static uint64_t xive2_end_source_read(void *opaque, hwaddr addr, unsigned size) 553 { 554 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 555 uint32_t offset = addr & 0xFFF; 556 uint8_t end_blk; 557 uint32_t end_idx; 558 Xive2End end; 559 uint32_t end_esmask; 560 uint8_t pq; 561 uint64_t ret; 562 563 /* 564 * The block id should be deduced from the load address on the END 565 * ESB MMIO but our model only supports a single block per XIVE chip. 566 */ 567 end_blk = xive2_router_get_block_id(xsrc->xrtr); 568 end_idx = addr >> (xsrc->esb_shift + 1); 569 570 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 571 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 572 end_idx); 573 return -1; 574 } 575 576 if (!xive2_end_is_valid(&end)) { 577 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 578 end_blk, end_idx); 579 return -1; 580 } 581 582 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 583 END2_W1_ESe; 584 pq = xive_get_field32(end_esmask, end.w1); 585 586 switch (offset) { 587 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 588 ret = xive_esb_eoi(&pq); 589 590 /* Forward the source event notification for routing ?? */ 591 break; 592 593 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 594 ret = pq; 595 break; 596 597 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 598 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 599 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 600 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 601 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 602 break; 603 default: 604 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 605 offset); 606 return -1; 607 } 608 609 if (pq != xive_get_field32(end_esmask, end.w1)) { 610 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 611 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 612 } 613 614 return ret; 615 } 616 617 static void xive2_end_source_write(void *opaque, hwaddr addr, 618 uint64_t value, unsigned size) 619 { 620 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 621 uint32_t offset = addr & 0xFFF; 622 uint8_t end_blk; 623 uint32_t end_idx; 624 Xive2End end; 625 uint32_t end_esmask; 626 uint8_t pq; 627 bool notify = false; 628 629 /* 630 * The block id should be deduced from the load address on the END 631 * ESB MMIO but our model only supports a single block per XIVE chip. 632 */ 633 end_blk = xive2_router_get_block_id(xsrc->xrtr); 634 end_idx = addr >> (xsrc->esb_shift + 1); 635 636 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 637 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 638 end_idx); 639 return; 640 } 641 642 if (!xive2_end_is_valid(&end)) { 643 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 644 end_blk, end_idx); 645 return; 646 } 647 648 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 649 END2_W1_ESe; 650 pq = xive_get_field32(end_esmask, end.w1); 651 652 switch (offset) { 653 case 0 ... 0x3FF: 654 notify = xive_esb_trigger(&pq); 655 break; 656 657 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 658 /* TODO: can we check StoreEOI availability from the router ? */ 659 notify = xive_esb_eoi(&pq); 660 break; 661 662 case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF: 663 if (end_esmask == END2_W1_ESe) { 664 qemu_log_mask(LOG_GUEST_ERROR, 665 "XIVE: END %x/%x can not EQ inject on ESe\n", 666 end_blk, end_idx); 667 return; 668 } 669 notify = true; 670 break; 671 672 default: 673 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB write addr %d\n", 674 offset); 675 return; 676 } 677 678 if (pq != xive_get_field32(end_esmask, end.w1)) { 679 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 680 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 681 } 682 683 /* TODO: Forward the source event notification for routing */ 684 if (notify) { 685 ; 686 } 687 } 688 689 static const MemoryRegionOps xive2_end_source_ops = { 690 .read = xive2_end_source_read, 691 .write = xive2_end_source_write, 692 .endianness = DEVICE_BIG_ENDIAN, 693 .valid = { 694 .min_access_size = 8, 695 .max_access_size = 8, 696 }, 697 .impl = { 698 .min_access_size = 8, 699 .max_access_size = 8, 700 }, 701 }; 702 703 static void xive2_end_source_realize(DeviceState *dev, Error **errp) 704 { 705 Xive2EndSource *xsrc = XIVE2_END_SOURCE(dev); 706 707 assert(xsrc->xrtr); 708 709 if (!xsrc->nr_ends) { 710 error_setg(errp, "Number of interrupt needs to be greater than 0"); 711 return; 712 } 713 714 if (xsrc->esb_shift != XIVE_ESB_4K && 715 xsrc->esb_shift != XIVE_ESB_64K) { 716 error_setg(errp, "Invalid ESB shift setting"); 717 return; 718 } 719 720 /* 721 * Each END is assigned an even/odd pair of MMIO pages, the even page 722 * manages the ESn field while the odd page manages the ESe field. 723 */ 724 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 725 &xive2_end_source_ops, xsrc, "xive.end", 726 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 727 } 728 729 static Property xive2_end_source_properties[] = { 730 DEFINE_PROP_UINT32("nr-ends", Xive2EndSource, nr_ends, 0), 731 DEFINE_PROP_UINT32("shift", Xive2EndSource, esb_shift, XIVE_ESB_64K), 732 DEFINE_PROP_LINK("xive", Xive2EndSource, xrtr, TYPE_XIVE2_ROUTER, 733 Xive2Router *), 734 DEFINE_PROP_END_OF_LIST(), 735 }; 736 737 static void xive2_end_source_class_init(ObjectClass *klass, void *data) 738 { 739 DeviceClass *dc = DEVICE_CLASS(klass); 740 741 dc->desc = "XIVE END Source"; 742 device_class_set_props(dc, xive2_end_source_properties); 743 dc->realize = xive2_end_source_realize; 744 } 745 746 static const TypeInfo xive2_end_source_info = { 747 .name = TYPE_XIVE2_END_SOURCE, 748 .parent = TYPE_DEVICE, 749 .instance_size = sizeof(Xive2EndSource), 750 .class_init = xive2_end_source_class_init, 751 }; 752 753 static void xive2_register_types(void) 754 { 755 type_register_static(&xive2_router_info); 756 type_register_static(&xive2_end_source_info); 757 } 758 759 type_init(xive2_register_types) 760