1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2022, IBM Corporation.. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #include "qemu/osdep.h" 11 #include "qemu/log.h" 12 #include "qemu/module.h" 13 #include "qapi/error.h" 14 #include "target/ppc/cpu.h" 15 #include "sysemu/cpus.h" 16 #include "sysemu/dma.h" 17 #include "hw/qdev-properties.h" 18 #include "monitor/monitor.h" 19 #include "hw/ppc/xive.h" 20 #include "hw/ppc/xive2.h" 21 #include "hw/ppc/xive2_regs.h" 22 23 uint32_t xive2_router_get_config(Xive2Router *xrtr) 24 { 25 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 26 27 return xrc->get_config(xrtr); 28 } 29 30 void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, Monitor *mon) 31 { 32 if (!xive2_eas_is_valid(eas)) { 33 return; 34 } 35 36 monitor_printf(mon, " %08x %s end:%02x/%04x data:%08x\n", 37 lisn, xive2_eas_is_masked(eas) ? "M" : " ", 38 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 39 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 40 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 41 } 42 43 void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, 44 Monitor *mon) 45 { 46 uint64_t qaddr_base = xive2_end_qaddr(end); 47 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 48 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 49 uint32_t qentries = 1 << (qsize + 10); 50 int i; 51 52 /* 53 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 54 */ 55 monitor_printf(mon, " [ "); 56 qindex = (qindex - (width - 1)) & (qentries - 1); 57 for (i = 0; i < width; i++) { 58 uint64_t qaddr = qaddr_base + (qindex << 2); 59 uint32_t qdata = -1; 60 61 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 62 sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { 63 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 64 HWADDR_PRIx "\n", qaddr); 65 return; 66 } 67 monitor_printf(mon, "%s%08x ", i == width - 1 ? "^" : "", 68 be32_to_cpu(qdata)); 69 qindex = (qindex + 1) & (qentries - 1); 70 } 71 monitor_printf(mon, "]"); 72 } 73 74 void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, Monitor *mon) 75 { 76 uint64_t qaddr_base = xive2_end_qaddr(end); 77 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 78 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 79 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 80 uint32_t qentries = 1 << (qsize + 10); 81 82 uint32_t nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6); 83 uint32_t nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6); 84 uint8_t priority = xive_get_field32(END2_W7_F0_PRIORITY, end->w7); 85 uint8_t pq; 86 87 if (!xive2_end_is_valid(end)) { 88 return; 89 } 90 91 pq = xive_get_field32(END2_W1_ESn, end->w1); 92 93 monitor_printf(mon, 94 " %08x %c%c %c%c%c%c%c%c%c%c%c%c prio:%d nvp:%02x/%04x", 95 end_idx, 96 pq & XIVE_ESB_VAL_P ? 'P' : '-', 97 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 98 xive2_end_is_valid(end) ? 'v' : '-', 99 xive2_end_is_enqueue(end) ? 'q' : '-', 100 xive2_end_is_notify(end) ? 'n' : '-', 101 xive2_end_is_backlog(end) ? 'b' : '-', 102 xive2_end_is_escalate(end) ? 'e' : '-', 103 xive2_end_is_escalate_end(end) ? 'N' : '-', 104 xive2_end_is_uncond_escalation(end) ? 'u' : '-', 105 xive2_end_is_silent_escalation(end) ? 's' : '-', 106 xive2_end_is_firmware1(end) ? 'f' : '-', 107 xive2_end_is_firmware2(end) ? 'F' : '-', 108 priority, nvp_blk, nvp_idx); 109 110 if (qaddr_base) { 111 monitor_printf(mon, " eq:@%08"PRIx64"% 6d/%5d ^%d", 112 qaddr_base, qindex, qentries, qgen); 113 xive2_end_queue_pic_print_info(end, 6, mon); 114 } 115 monitor_printf(mon, "\n"); 116 } 117 118 void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx, 119 Monitor *mon) 120 { 121 Xive2Eas *eas = (Xive2Eas *) &end->w4; 122 uint8_t pq; 123 124 if (!xive2_end_is_escalate(end)) { 125 return; 126 } 127 128 pq = xive_get_field32(END2_W1_ESe, end->w1); 129 130 monitor_printf(mon, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 131 end_idx, 132 pq & XIVE_ESB_VAL_P ? 'P' : '-', 133 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 134 xive2_eas_is_valid(eas) ? 'v' : ' ', 135 xive2_eas_is_masked(eas) ? 'M' : ' ', 136 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 137 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 138 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 139 } 140 141 static void xive2_end_enqueue(Xive2End *end, uint32_t data) 142 { 143 uint64_t qaddr_base = xive2_end_qaddr(end); 144 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 145 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 146 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 147 148 uint64_t qaddr = qaddr_base + (qindex << 2); 149 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 150 uint32_t qentries = 1 << (qsize + 10); 151 152 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata), 153 MEMTXATTRS_UNSPECIFIED)) { 154 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 155 HWADDR_PRIx "\n", qaddr); 156 return; 157 } 158 159 qindex = (qindex + 1) & (qentries - 1); 160 if (qindex == 0) { 161 qgen ^= 1; 162 end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen); 163 164 /* TODO(PowerNV): reset GF bit on a cache watch operation */ 165 end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, qgen); 166 } 167 end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex); 168 } 169 170 /* 171 * XIVE Thread Interrupt Management Area (TIMA) - Gen2 mode 172 * 173 * TIMA Gen2 VP “save & restore” (S&R) indicated by H bit next to V bit 174 * 175 * - if a context is enabled with the H bit set, the VP context 176 * information is retrieved from the NVP structure (“check out”) 177 * and stored back on a context pull (“check in”), the SW receives 178 * the same context pull information as on P9 179 * 180 * - the H bit cannot be changed while the V bit is set, i.e. a 181 * context cannot be set up in the TIMA and then be “pushed” into 182 * the NVP by changing the H bit while the context is enabled 183 */ 184 185 static void xive2_tctx_save_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx, 186 uint8_t nvp_blk, uint32_t nvp_idx) 187 { 188 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 189 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 190 Xive2Nvp nvp; 191 uint8_t *regs = &tctx->regs[TM_QW1_OS]; 192 193 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 194 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 195 nvp_blk, nvp_idx); 196 return; 197 } 198 199 if (!xive2_nvp_is_valid(&nvp)) { 200 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 201 nvp_blk, nvp_idx); 202 return; 203 } 204 205 if (!xive2_nvp_is_hw(&nvp)) { 206 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n", 207 nvp_blk, nvp_idx); 208 return; 209 } 210 211 if (!xive2_nvp_is_co(&nvp)) { 212 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not checkout\n", 213 nvp_blk, nvp_idx); 214 return; 215 } 216 217 if (xive_get_field32(NVP2_W1_CO_THRID_VALID, nvp.w1) && 218 xive_get_field32(NVP2_W1_CO_THRID, nvp.w1) != pir) { 219 qemu_log_mask(LOG_GUEST_ERROR, 220 "XIVE: NVP %x/%x invalid checkout Thread %x\n", 221 nvp_blk, nvp_idx, pir); 222 return; 223 } 224 225 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, regs[TM_IPB]); 226 nvp.w2 = xive_set_field32(NVP2_W2_CPPR, nvp.w2, regs[TM_CPPR]); 227 nvp.w2 = xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]); 228 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 229 230 nvp.w1 = xive_set_field32(NVP2_W1_CO, nvp.w1, 0); 231 /* NVP2_W1_CO_THRID_VALID only set once */ 232 nvp.w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp.w1, 0xFFFF); 233 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 1); 234 } 235 236 static void xive2_os_cam_decode(uint32_t cam, uint8_t *nvp_blk, 237 uint32_t *nvp_idx, bool *vo, bool *ho) 238 { 239 *nvp_blk = xive2_nvp_blk(cam); 240 *nvp_idx = xive2_nvp_idx(cam); 241 *vo = !!(cam & TM2_QW1W2_VO); 242 *ho = !!(cam & TM2_QW1W2_HO); 243 } 244 245 uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 246 hwaddr offset, unsigned size) 247 { 248 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 249 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 250 uint32_t qw1w2_new; 251 uint32_t cam = be32_to_cpu(qw1w2); 252 uint8_t nvp_blk; 253 uint32_t nvp_idx; 254 bool vo; 255 bool do_save; 256 257 xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_save); 258 259 if (!vo) { 260 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?\n", 261 nvp_blk, nvp_idx); 262 } 263 264 /* Invalidate CAM line */ 265 qw1w2_new = xive_set_field32(TM2_QW1W2_VO, qw1w2, 0); 266 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4); 267 268 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) { 269 xive2_tctx_save_os_ctx(xrtr, tctx, nvp_blk, nvp_idx); 270 } 271 272 return qw1w2; 273 } 274 275 static uint8_t xive2_tctx_restore_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx, 276 uint8_t nvp_blk, uint32_t nvp_idx, 277 Xive2Nvp *nvp) 278 { 279 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 280 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 281 uint8_t cppr; 282 283 if (!xive2_nvp_is_hw(nvp)) { 284 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n", 285 nvp_blk, nvp_idx); 286 return 0; 287 } 288 289 cppr = xive_get_field32(NVP2_W2_CPPR, nvp->w2); 290 nvp->w2 = xive_set_field32(NVP2_W2_CPPR, nvp->w2, 0); 291 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 2); 292 293 tctx->regs[TM_QW1_OS + TM_CPPR] = cppr; 294 /* we don't model LSMFB */ 295 296 nvp->w1 = xive_set_field32(NVP2_W1_CO, nvp->w1, 1); 297 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID_VALID, nvp->w1, 1); 298 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp->w1, pir); 299 300 /* 301 * Checkout privilege: 0:OS, 1:Pool, 2:Hard 302 * 303 * TODO: we only support OS push/pull 304 */ 305 nvp->w1 = xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 0); 306 307 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 1); 308 309 /* return restored CPPR to generate a CPU exception if needed */ 310 return cppr; 311 } 312 313 static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx, 314 uint8_t nvp_blk, uint32_t nvp_idx, 315 bool do_restore) 316 { 317 Xive2Nvp nvp; 318 uint8_t ipb; 319 320 /* 321 * Grab the associated thread interrupt context registers in the 322 * associated NVP 323 */ 324 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 325 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 326 nvp_blk, nvp_idx); 327 return; 328 } 329 330 if (!xive2_nvp_is_valid(&nvp)) { 331 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 332 nvp_blk, nvp_idx); 333 return; 334 } 335 336 /* Automatically restore thread context registers */ 337 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && 338 do_restore) { 339 xive2_tctx_restore_os_ctx(xrtr, tctx, nvp_blk, nvp_idx, &nvp); 340 } 341 342 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2); 343 if (ipb) { 344 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, 0); 345 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 346 } 347 /* 348 * Always call xive_tctx_ipb_update(). Even if there were no 349 * escalation triggered, there could be a pending interrupt which 350 * was saved when the context was pulled and that we need to take 351 * into account by recalculating the PIPR (which is not 352 * saved/restored). 353 */ 354 xive_tctx_ipb_update(tctx, TM_QW1_OS, ipb); 355 } 356 357 /* 358 * Updating the OS CAM line can trigger a resend of interrupt 359 */ 360 void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 361 hwaddr offset, uint64_t value, unsigned size) 362 { 363 uint32_t cam = value; 364 uint32_t qw1w2 = cpu_to_be32(cam); 365 uint8_t nvp_blk; 366 uint32_t nvp_idx; 367 bool vo; 368 bool do_restore; 369 370 xive2_os_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore); 371 372 /* First update the thead context */ 373 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 374 375 /* Check the interrupt pending bits */ 376 if (vo) { 377 xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, nvp_blk, nvp_idx, 378 do_restore); 379 } 380 } 381 382 /* 383 * XIVE Router (aka. Virtualization Controller or IVRE) 384 */ 385 386 int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 387 Xive2Eas *eas) 388 { 389 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 390 391 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 392 } 393 394 static 395 int xive2_router_get_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 396 uint8_t *pq) 397 { 398 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 399 400 return xrc->get_pq(xrtr, eas_blk, eas_idx, pq); 401 } 402 403 static 404 int xive2_router_set_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 405 uint8_t *pq) 406 { 407 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 408 409 return xrc->set_pq(xrtr, eas_blk, eas_idx, pq); 410 } 411 412 int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 413 Xive2End *end) 414 { 415 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 416 417 return xrc->get_end(xrtr, end_blk, end_idx, end); 418 } 419 420 int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 421 Xive2End *end, uint8_t word_number) 422 { 423 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 424 425 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 426 } 427 428 int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 429 Xive2Nvp *nvp) 430 { 431 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 432 433 return xrc->get_nvp(xrtr, nvp_blk, nvp_idx, nvp); 434 } 435 436 int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 437 Xive2Nvp *nvp, uint8_t word_number) 438 { 439 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 440 441 return xrc->write_nvp(xrtr, nvp_blk, nvp_idx, nvp, word_number); 442 } 443 444 static int xive2_router_get_block_id(Xive2Router *xrtr) 445 { 446 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 447 448 return xrc->get_block_id(xrtr); 449 } 450 451 /* 452 * Encode the HW CAM line with 7bit or 8bit thread id. The thread id 453 * width and block id width is configurable at the IC level. 454 * 455 * chipid << 24 | 0000 0000 0000 0000 1 threadid (7Bit) 456 * chipid << 24 | 0000 0000 0000 0001 threadid (8Bit) 457 */ 458 static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 459 { 460 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 461 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 462 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 463 uint8_t blk = xive2_router_get_block_id(xrtr); 464 uint8_t tid_shift = 465 xive2_router_get_config(xrtr) & XIVE2_THREADID_8BITS ? 8 : 7; 466 uint8_t tid_mask = (1 << tid_shift) - 1; 467 468 return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask)); 469 } 470 471 /* 472 * The thread context register words are in big-endian format. 473 */ 474 int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 475 uint8_t format, 476 uint8_t nvt_blk, uint32_t nvt_idx, 477 bool cam_ignore, uint32_t logic_serv) 478 { 479 uint32_t cam = xive2_nvp_cam_line(nvt_blk, nvt_idx); 480 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 481 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 482 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 483 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 484 485 /* 486 * TODO (PowerNV): ignore mode. The low order bits of the NVT 487 * identifier are ignored in the "CAM" match. 488 */ 489 490 if (format == 0) { 491 if (cam_ignore == true) { 492 /* 493 * F=0 & i=1: Logical server notification (bits ignored at 494 * the end of the NVT identifier) 495 */ 496 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 497 nvt_blk, nvt_idx); 498 return -1; 499 } 500 501 /* F=0 & i=0: Specific NVT notification */ 502 503 /* PHYS ring */ 504 if ((be32_to_cpu(qw3w2) & TM2_QW3W2_VT) && 505 cam == xive2_tctx_hw_cam_line(xptr, tctx)) { 506 return TM_QW3_HV_PHYS; 507 } 508 509 /* HV POOL ring */ 510 if ((be32_to_cpu(qw2w2) & TM2_QW2W2_VP) && 511 cam == xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2)) { 512 return TM_QW2_HV_POOL; 513 } 514 515 /* OS ring */ 516 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 517 cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) { 518 return TM_QW1_OS; 519 } 520 } else { 521 /* F=1 : User level Event-Based Branch (EBB) notification */ 522 523 /* USER ring */ 524 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 525 (cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) && 526 (be32_to_cpu(qw0w2) & TM2_QW0W2_VU) && 527 (logic_serv == xive_get_field32(TM2_QW0W2_LOGIC_SERV, qw0w2))) { 528 return TM_QW0_USER; 529 } 530 } 531 return -1; 532 } 533 534 static void xive2_router_realize(DeviceState *dev, Error **errp) 535 { 536 Xive2Router *xrtr = XIVE2_ROUTER(dev); 537 538 assert(xrtr->xfb); 539 } 540 541 /* 542 * Notification using the END ESe/ESn bit (Event State Buffer for 543 * escalation and notification). Profide futher coalescing in the 544 * Router. 545 */ 546 static bool xive2_router_end_es_notify(Xive2Router *xrtr, uint8_t end_blk, 547 uint32_t end_idx, Xive2End *end, 548 uint32_t end_esmask) 549 { 550 uint8_t pq = xive_get_field32(end_esmask, end->w1); 551 bool notify = xive_esb_trigger(&pq); 552 553 if (pq != xive_get_field32(end_esmask, end->w1)) { 554 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 555 xive2_router_write_end(xrtr, end_blk, end_idx, end, 1); 556 } 557 558 /* ESe/n[Q]=1 : end of notification */ 559 return notify; 560 } 561 562 /* 563 * An END trigger can come from an event trigger (IPI or HW) or from 564 * another chip. We don't model the PowerBus but the END trigger 565 * message has the same parameters than in the function below. 566 */ 567 static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk, 568 uint32_t end_idx, uint32_t end_data) 569 { 570 Xive2End end; 571 uint8_t priority; 572 uint8_t format; 573 bool found; 574 Xive2Nvp nvp; 575 uint8_t nvp_blk; 576 uint32_t nvp_idx; 577 578 /* END cache lookup */ 579 if (xive2_router_get_end(xrtr, end_blk, end_idx, &end)) { 580 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 581 end_idx); 582 return; 583 } 584 585 if (!xive2_end_is_valid(&end)) { 586 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 587 end_blk, end_idx); 588 return; 589 } 590 591 if (xive2_end_is_enqueue(&end)) { 592 xive2_end_enqueue(&end, end_data); 593 /* Enqueuing event data modifies the EQ toggle and index */ 594 xive2_router_write_end(xrtr, end_blk, end_idx, &end, 1); 595 } 596 597 /* 598 * When the END is silent, we skip the notification part. 599 */ 600 if (xive2_end_is_silent_escalation(&end)) { 601 goto do_escalation; 602 } 603 604 /* 605 * The W7 format depends on the F bit in W6. It defines the type 606 * of the notification : 607 * 608 * F=0 : single or multiple NVP notification 609 * F=1 : User level Event-Based Branch (EBB) notification, no 610 * priority 611 */ 612 format = xive_get_field32(END2_W6_FORMAT_BIT, end.w6); 613 priority = xive_get_field32(END2_W7_F0_PRIORITY, end.w7); 614 615 /* The END is masked */ 616 if (format == 0 && priority == 0xff) { 617 return; 618 } 619 620 /* 621 * Check the END ESn (Event State Buffer for notification) for 622 * even futher coalescing in the Router 623 */ 624 if (!xive2_end_is_notify(&end)) { 625 /* ESn[Q]=1 : end of notification */ 626 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 627 &end, END2_W1_ESn)) { 628 return; 629 } 630 } 631 632 /* 633 * Follows IVPE notification 634 */ 635 nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end.w6); 636 nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end.w6); 637 638 /* NVP cache lookup */ 639 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 640 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVP %x/%x\n", 641 nvp_blk, nvp_idx); 642 return; 643 } 644 645 if (!xive2_nvp_is_valid(&nvp)) { 646 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is invalid\n", 647 nvp_blk, nvp_idx); 648 return; 649 } 650 651 found = xive_presenter_notify(xrtr->xfb, format, nvp_blk, nvp_idx, 652 xive_get_field32(END2_W6_IGNORE, end.w7), 653 priority, 654 xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w7)); 655 656 /* TODO: Auto EOI. */ 657 658 if (found) { 659 return; 660 } 661 662 /* 663 * If no matching NVP is dispatched on a HW thread : 664 * - specific VP: update the NVP structure if backlog is activated 665 * - logical server : forward request to IVPE (not supported) 666 */ 667 if (xive2_end_is_backlog(&end)) { 668 uint8_t ipb; 669 670 if (format == 1) { 671 qemu_log_mask(LOG_GUEST_ERROR, 672 "XIVE: END %x/%x invalid config: F1 & backlog\n", 673 end_blk, end_idx); 674 return; 675 } 676 677 /* 678 * Record the IPB in the associated NVP structure for later 679 * use. The presenter will resend the interrupt when the vCPU 680 * is dispatched again on a HW thread. 681 */ 682 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2) | 683 xive_priority_to_ipb(priority); 684 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb); 685 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 686 687 /* 688 * On HW, follows a "Broadcast Backlog" to IVPEs 689 */ 690 } 691 692 do_escalation: 693 /* 694 * If activated, escalate notification using the ESe PQ bits and 695 * the EAS in w4-5 696 */ 697 if (!xive2_end_is_escalate(&end)) { 698 return; 699 } 700 701 /* 702 * Check the END ESe (Event State Buffer for escalation) for even 703 * futher coalescing in the Router 704 */ 705 if (!xive2_end_is_uncond_escalation(&end)) { 706 /* ESe[Q]=1 : end of escalation notification */ 707 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 708 &end, END2_W1_ESe)) { 709 return; 710 } 711 } 712 713 /* 714 * The END trigger becomes an Escalation trigger 715 */ 716 xive2_router_end_notify(xrtr, 717 xive_get_field32(END2_W4_END_BLOCK, end.w4), 718 xive_get_field32(END2_W4_ESC_END_INDEX, end.w4), 719 xive_get_field32(END2_W5_ESC_END_DATA, end.w5)); 720 } 721 722 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) 723 { 724 Xive2Router *xrtr = XIVE2_ROUTER(xn); 725 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 726 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 727 Xive2Eas eas; 728 729 /* EAS cache lookup */ 730 if (xive2_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 731 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 732 return; 733 } 734 735 if (!pq_checked) { 736 bool notify; 737 uint8_t pq; 738 739 /* PQ cache lookup */ 740 if (xive2_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) { 741 /* Set FIR */ 742 g_assert_not_reached(); 743 } 744 745 notify = xive_esb_trigger(&pq); 746 747 if (xive2_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) { 748 /* Set FIR */ 749 g_assert_not_reached(); 750 } 751 752 if (!notify) { 753 return; 754 } 755 } 756 757 if (!xive2_eas_is_valid(&eas)) { 758 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %x\n", lisn); 759 return; 760 } 761 762 if (xive2_eas_is_masked(&eas)) { 763 /* Notification completed */ 764 return; 765 } 766 767 /* 768 * The event trigger becomes an END trigger 769 */ 770 xive2_router_end_notify(xrtr, 771 xive_get_field64(EAS2_END_BLOCK, eas.w), 772 xive_get_field64(EAS2_END_INDEX, eas.w), 773 xive_get_field64(EAS2_END_DATA, eas.w)); 774 } 775 776 static Property xive2_router_properties[] = { 777 DEFINE_PROP_LINK("xive-fabric", Xive2Router, xfb, 778 TYPE_XIVE_FABRIC, XiveFabric *), 779 DEFINE_PROP_END_OF_LIST(), 780 }; 781 782 static void xive2_router_class_init(ObjectClass *klass, void *data) 783 { 784 DeviceClass *dc = DEVICE_CLASS(klass); 785 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 786 787 dc->desc = "XIVE2 Router Engine"; 788 device_class_set_props(dc, xive2_router_properties); 789 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 790 dc->realize = xive2_router_realize; 791 xnc->notify = xive2_router_notify; 792 } 793 794 static const TypeInfo xive2_router_info = { 795 .name = TYPE_XIVE2_ROUTER, 796 .parent = TYPE_SYS_BUS_DEVICE, 797 .abstract = true, 798 .instance_size = sizeof(Xive2Router), 799 .class_size = sizeof(Xive2RouterClass), 800 .class_init = xive2_router_class_init, 801 .interfaces = (InterfaceInfo[]) { 802 { TYPE_XIVE_NOTIFIER }, 803 { TYPE_XIVE_PRESENTER }, 804 { } 805 } 806 }; 807 808 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 809 { 810 return !((addr >> shift) & 1); 811 } 812 813 static uint64_t xive2_end_source_read(void *opaque, hwaddr addr, unsigned size) 814 { 815 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 816 uint32_t offset = addr & 0xFFF; 817 uint8_t end_blk; 818 uint32_t end_idx; 819 Xive2End end; 820 uint32_t end_esmask; 821 uint8_t pq; 822 uint64_t ret; 823 824 /* 825 * The block id should be deduced from the load address on the END 826 * ESB MMIO but our model only supports a single block per XIVE chip. 827 */ 828 end_blk = xive2_router_get_block_id(xsrc->xrtr); 829 end_idx = addr >> (xsrc->esb_shift + 1); 830 831 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 832 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 833 end_idx); 834 return -1; 835 } 836 837 if (!xive2_end_is_valid(&end)) { 838 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 839 end_blk, end_idx); 840 return -1; 841 } 842 843 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 844 END2_W1_ESe; 845 pq = xive_get_field32(end_esmask, end.w1); 846 847 switch (offset) { 848 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 849 ret = xive_esb_eoi(&pq); 850 851 /* Forward the source event notification for routing ?? */ 852 break; 853 854 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 855 ret = pq; 856 break; 857 858 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 859 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 860 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 861 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 862 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 863 break; 864 default: 865 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 866 offset); 867 return -1; 868 } 869 870 if (pq != xive_get_field32(end_esmask, end.w1)) { 871 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 872 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 873 } 874 875 return ret; 876 } 877 878 static void xive2_end_source_write(void *opaque, hwaddr addr, 879 uint64_t value, unsigned size) 880 { 881 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 882 uint32_t offset = addr & 0xFFF; 883 uint8_t end_blk; 884 uint32_t end_idx; 885 Xive2End end; 886 uint32_t end_esmask; 887 uint8_t pq; 888 bool notify = false; 889 890 /* 891 * The block id should be deduced from the load address on the END 892 * ESB MMIO but our model only supports a single block per XIVE chip. 893 */ 894 end_blk = xive2_router_get_block_id(xsrc->xrtr); 895 end_idx = addr >> (xsrc->esb_shift + 1); 896 897 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 898 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 899 end_idx); 900 return; 901 } 902 903 if (!xive2_end_is_valid(&end)) { 904 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 905 end_blk, end_idx); 906 return; 907 } 908 909 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 910 END2_W1_ESe; 911 pq = xive_get_field32(end_esmask, end.w1); 912 913 switch (offset) { 914 case 0 ... 0x3FF: 915 notify = xive_esb_trigger(&pq); 916 break; 917 918 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 919 /* TODO: can we check StoreEOI availability from the router ? */ 920 notify = xive_esb_eoi(&pq); 921 break; 922 923 case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF: 924 if (end_esmask == END2_W1_ESe) { 925 qemu_log_mask(LOG_GUEST_ERROR, 926 "XIVE: END %x/%x can not EQ inject on ESe\n", 927 end_blk, end_idx); 928 return; 929 } 930 notify = true; 931 break; 932 933 default: 934 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB write addr %d\n", 935 offset); 936 return; 937 } 938 939 if (pq != xive_get_field32(end_esmask, end.w1)) { 940 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 941 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 942 } 943 944 /* TODO: Forward the source event notification for routing */ 945 if (notify) { 946 ; 947 } 948 } 949 950 static const MemoryRegionOps xive2_end_source_ops = { 951 .read = xive2_end_source_read, 952 .write = xive2_end_source_write, 953 .endianness = DEVICE_BIG_ENDIAN, 954 .valid = { 955 .min_access_size = 8, 956 .max_access_size = 8, 957 }, 958 .impl = { 959 .min_access_size = 8, 960 .max_access_size = 8, 961 }, 962 }; 963 964 static void xive2_end_source_realize(DeviceState *dev, Error **errp) 965 { 966 Xive2EndSource *xsrc = XIVE2_END_SOURCE(dev); 967 968 assert(xsrc->xrtr); 969 970 if (!xsrc->nr_ends) { 971 error_setg(errp, "Number of interrupt needs to be greater than 0"); 972 return; 973 } 974 975 if (xsrc->esb_shift != XIVE_ESB_4K && 976 xsrc->esb_shift != XIVE_ESB_64K) { 977 error_setg(errp, "Invalid ESB shift setting"); 978 return; 979 } 980 981 /* 982 * Each END is assigned an even/odd pair of MMIO pages, the even page 983 * manages the ESn field while the odd page manages the ESe field. 984 */ 985 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 986 &xive2_end_source_ops, xsrc, "xive.end", 987 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 988 } 989 990 static Property xive2_end_source_properties[] = { 991 DEFINE_PROP_UINT32("nr-ends", Xive2EndSource, nr_ends, 0), 992 DEFINE_PROP_UINT32("shift", Xive2EndSource, esb_shift, XIVE_ESB_64K), 993 DEFINE_PROP_LINK("xive", Xive2EndSource, xrtr, TYPE_XIVE2_ROUTER, 994 Xive2Router *), 995 DEFINE_PROP_END_OF_LIST(), 996 }; 997 998 static void xive2_end_source_class_init(ObjectClass *klass, void *data) 999 { 1000 DeviceClass *dc = DEVICE_CLASS(klass); 1001 1002 dc->desc = "XIVE END Source"; 1003 device_class_set_props(dc, xive2_end_source_properties); 1004 dc->realize = xive2_end_source_realize; 1005 dc->user_creatable = false; 1006 } 1007 1008 static const TypeInfo xive2_end_source_info = { 1009 .name = TYPE_XIVE2_END_SOURCE, 1010 .parent = TYPE_DEVICE, 1011 .instance_size = sizeof(Xive2EndSource), 1012 .class_init = xive2_end_source_class_init, 1013 }; 1014 1015 static void xive2_register_types(void) 1016 { 1017 type_register_static(&xive2_router_info); 1018 type_register_static(&xive2_end_source_info); 1019 } 1020 1021 type_init(xive2_register_types) 1022