1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2024, IBM Corporation.. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/log.h" 11 #include "qemu/module.h" 12 #include "qapi/error.h" 13 #include "target/ppc/cpu.h" 14 #include "system/cpus.h" 15 #include "system/dma.h" 16 #include "hw/qdev-properties.h" 17 #include "hw/ppc/xive.h" 18 #include "hw/ppc/xive2.h" 19 #include "hw/ppc/xive2_regs.h" 20 21 uint32_t xive2_router_get_config(Xive2Router *xrtr) 22 { 23 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 24 25 return xrc->get_config(xrtr); 26 } 27 28 static int xive2_router_get_block_id(Xive2Router *xrtr) 29 { 30 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 31 32 return xrc->get_block_id(xrtr); 33 } 34 35 static uint64_t xive2_nvp_reporting_addr(Xive2Nvp *nvp) 36 { 37 uint64_t cache_addr; 38 39 cache_addr = xive_get_field32(NVP2_W6_REPORTING_LINE, nvp->w6) << 24 | 40 xive_get_field32(NVP2_W7_REPORTING_LINE, nvp->w7); 41 cache_addr <<= 8; /* aligned on a cache line pair */ 42 return cache_addr; 43 } 44 45 static uint32_t xive2_nvgc_get_backlog(Xive2Nvgc *nvgc, uint8_t priority) 46 { 47 uint32_t val = 0; 48 uint8_t *ptr, i; 49 50 if (priority > 7) { 51 return 0; 52 } 53 54 /* 55 * The per-priority backlog counters are 24-bit and the structure 56 * is stored in big endian 57 */ 58 ptr = (uint8_t *)&nvgc->w2 + priority * 3; 59 for (i = 0; i < 3; i++, ptr++) { 60 val = (val << 8) + *ptr; 61 } 62 return val; 63 } 64 65 void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf) 66 { 67 if (!xive2_eas_is_valid(eas)) { 68 return; 69 } 70 71 g_string_append_printf(buf, " %08x %s end:%02x/%04x data:%08x\n", 72 lisn, xive2_eas_is_masked(eas) ? "M" : " ", 73 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 74 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 75 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 76 } 77 78 void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, GString *buf) 79 { 80 uint64_t qaddr_base = xive2_end_qaddr(end); 81 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 82 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 83 uint32_t qentries = 1 << (qsize + 10); 84 int i; 85 86 /* 87 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 88 */ 89 g_string_append_printf(buf, " [ "); 90 qindex = (qindex - (width - 1)) & (qentries - 1); 91 for (i = 0; i < width; i++) { 92 uint64_t qaddr = qaddr_base + (qindex << 2); 93 uint32_t qdata = -1; 94 95 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 96 sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { 97 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 98 HWADDR_PRIx "\n", qaddr); 99 return; 100 } 101 g_string_append_printf(buf, "%s%08x ", i == width - 1 ? "^" : "", 102 be32_to_cpu(qdata)); 103 qindex = (qindex + 1) & (qentries - 1); 104 } 105 g_string_append_printf(buf, "]"); 106 } 107 108 void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, GString *buf) 109 { 110 uint64_t qaddr_base = xive2_end_qaddr(end); 111 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 112 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 113 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 114 uint32_t qentries = 1 << (qsize + 10); 115 116 uint32_t nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6); 117 uint32_t nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6); 118 uint8_t priority = xive_get_field32(END2_W7_F0_PRIORITY, end->w7); 119 uint8_t pq; 120 121 if (!xive2_end_is_valid(end)) { 122 return; 123 } 124 125 pq = xive_get_field32(END2_W1_ESn, end->w1); 126 127 g_string_append_printf(buf, 128 " %08x %c%c %c%c%c%c%c%c%c%c%c%c%c %c%c " 129 "prio:%d nvp:%02x/%04x", 130 end_idx, 131 pq & XIVE_ESB_VAL_P ? 'P' : '-', 132 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 133 xive2_end_is_valid(end) ? 'v' : '-', 134 xive2_end_is_enqueue(end) ? 'q' : '-', 135 xive2_end_is_notify(end) ? 'n' : '-', 136 xive2_end_is_backlog(end) ? 'b' : '-', 137 xive2_end_is_precluded_escalation(end) ? 'p' : '-', 138 xive2_end_is_escalate(end) ? 'e' : '-', 139 xive2_end_is_escalate_end(end) ? 'N' : '-', 140 xive2_end_is_uncond_escalation(end) ? 'u' : '-', 141 xive2_end_is_silent_escalation(end) ? 's' : '-', 142 xive2_end_is_firmware1(end) ? 'f' : '-', 143 xive2_end_is_firmware2(end) ? 'F' : '-', 144 xive2_end_is_ignore(end) ? 'i' : '-', 145 xive2_end_is_crowd(end) ? 'c' : '-', 146 priority, nvp_blk, nvp_idx); 147 148 if (qaddr_base) { 149 g_string_append_printf(buf, " eq:@%08"PRIx64"% 6d/%5d ^%d", 150 qaddr_base, qindex, qentries, qgen); 151 xive2_end_queue_pic_print_info(end, 6, buf); 152 } 153 g_string_append_c(buf, '\n'); 154 } 155 156 void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx, 157 GString *buf) 158 { 159 Xive2Eas *eas = (Xive2Eas *) &end->w4; 160 uint8_t pq; 161 162 if (!xive2_end_is_escalate(end)) { 163 return; 164 } 165 166 pq = xive_get_field32(END2_W1_ESe, end->w1); 167 168 g_string_append_printf(buf, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 169 end_idx, 170 pq & XIVE_ESB_VAL_P ? 'P' : '-', 171 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 172 xive2_eas_is_valid(eas) ? 'v' : ' ', 173 xive2_eas_is_masked(eas) ? 'M' : ' ', 174 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 175 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 176 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 177 } 178 179 void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, GString *buf) 180 { 181 uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5); 182 uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5); 183 uint64_t cache_line = xive2_nvp_reporting_addr(nvp); 184 185 if (!xive2_nvp_is_valid(nvp)) { 186 return; 187 } 188 189 g_string_append_printf(buf, " %08x end:%02x/%04x IPB:%02x PGoFirst:%02x", 190 nvp_idx, eq_blk, eq_idx, 191 xive_get_field32(NVP2_W2_IPB, nvp->w2), 192 xive_get_field32(NVP2_W0_PGOFIRST, nvp->w0)); 193 if (cache_line) { 194 g_string_append_printf(buf, " reporting CL:%016"PRIx64, cache_line); 195 } 196 197 /* 198 * When the NVP is HW controlled, more fields are updated 199 */ 200 if (xive2_nvp_is_hw(nvp)) { 201 g_string_append_printf(buf, " CPPR:%02x", 202 xive_get_field32(NVP2_W2_CPPR, nvp->w2)); 203 if (xive2_nvp_is_co(nvp)) { 204 g_string_append_printf(buf, " CO:%04x", 205 xive_get_field32(NVP2_W1_CO_THRID, nvp->w1)); 206 } 207 } 208 g_string_append_c(buf, '\n'); 209 } 210 211 void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uint32_t nvgc_idx, GString *buf) 212 { 213 uint8_t i; 214 215 if (!xive2_nvgc_is_valid(nvgc)) { 216 return; 217 } 218 219 g_string_append_printf(buf, " %08x PGoNext:%02x bklog: ", nvgc_idx, 220 xive_get_field32(NVGC2_W0_PGONEXT, nvgc->w0)); 221 for (i = 0; i <= XIVE_PRIORITY_MAX; i++) { 222 g_string_append_printf(buf, "[%d]=0x%x ", 223 i, xive2_nvgc_get_backlog(nvgc, i)); 224 } 225 g_string_append_printf(buf, "\n"); 226 } 227 228 static void xive2_end_enqueue(Xive2End *end, uint32_t data) 229 { 230 uint64_t qaddr_base = xive2_end_qaddr(end); 231 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 232 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 233 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 234 235 uint64_t qaddr = qaddr_base + (qindex << 2); 236 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 237 uint32_t qentries = 1 << (qsize + 10); 238 239 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata), 240 MEMTXATTRS_UNSPECIFIED)) { 241 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 242 HWADDR_PRIx "\n", qaddr); 243 return; 244 } 245 246 qindex = (qindex + 1) & (qentries - 1); 247 if (qindex == 0) { 248 qgen ^= 1; 249 end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen); 250 251 /* TODO(PowerNV): reset GF bit on a cache watch operation */ 252 end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, qgen); 253 } 254 end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex); 255 } 256 257 /* 258 * XIVE Thread Interrupt Management Area (TIMA) - Gen2 mode 259 * 260 * TIMA Gen2 VP “save & restore” (S&R) indicated by H bit next to V bit 261 * 262 * - if a context is enabled with the H bit set, the VP context 263 * information is retrieved from the NVP structure (“check out”) 264 * and stored back on a context pull (“check in”), the SW receives 265 * the same context pull information as on P9 266 * 267 * - the H bit cannot be changed while the V bit is set, i.e. a 268 * context cannot be set up in the TIMA and then be “pushed” into 269 * the NVP by changing the H bit while the context is enabled 270 */ 271 272 static void xive2_tctx_save_ctx(Xive2Router *xrtr, XiveTCTX *tctx, 273 uint8_t nvp_blk, uint32_t nvp_idx, 274 uint8_t ring) 275 { 276 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 277 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 278 Xive2Nvp nvp; 279 uint8_t *regs = &tctx->regs[ring]; 280 281 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 282 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 283 nvp_blk, nvp_idx); 284 return; 285 } 286 287 if (!xive2_nvp_is_valid(&nvp)) { 288 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 289 nvp_blk, nvp_idx); 290 return; 291 } 292 293 if (!xive2_nvp_is_hw(&nvp)) { 294 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n", 295 nvp_blk, nvp_idx); 296 return; 297 } 298 299 if (!xive2_nvp_is_co(&nvp)) { 300 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not checkout\n", 301 nvp_blk, nvp_idx); 302 return; 303 } 304 305 if (xive_get_field32(NVP2_W1_CO_THRID_VALID, nvp.w1) && 306 xive_get_field32(NVP2_W1_CO_THRID, nvp.w1) != pir) { 307 qemu_log_mask(LOG_GUEST_ERROR, 308 "XIVE: NVP %x/%x invalid checkout Thread %x\n", 309 nvp_blk, nvp_idx, pir); 310 return; 311 } 312 313 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, regs[TM_IPB]); 314 nvp.w2 = xive_set_field32(NVP2_W2_CPPR, nvp.w2, regs[TM_CPPR]); 315 if (nvp.w0 & NVP2_W0_L) { 316 /* 317 * Typically not used. If LSMFB is restored with 0, it will 318 * force a backlog rescan 319 */ 320 nvp.w2 = xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]); 321 } 322 if (nvp.w0 & NVP2_W0_G) { 323 nvp.w2 = xive_set_field32(NVP2_W2_LGS, nvp.w2, regs[TM_LGS]); 324 } 325 if (nvp.w0 & NVP2_W0_T) { 326 nvp.w2 = xive_set_field32(NVP2_W2_T, nvp.w2, regs[TM_T]); 327 } 328 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 329 330 nvp.w1 = xive_set_field32(NVP2_W1_CO, nvp.w1, 0); 331 /* NVP2_W1_CO_THRID_VALID only set once */ 332 nvp.w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp.w1, 0xFFFF); 333 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 1); 334 } 335 336 static void xive2_cam_decode(uint32_t cam, uint8_t *nvp_blk, 337 uint32_t *nvp_idx, bool *valid, bool *hw) 338 { 339 *nvp_blk = xive2_nvp_blk(cam); 340 *nvp_idx = xive2_nvp_idx(cam); 341 *valid = !!(cam & TM2_W2_VALID); 342 *hw = !!(cam & TM2_W2_HW); 343 } 344 345 /* 346 * Encode the HW CAM line with 7bit or 8bit thread id. The thread id 347 * width and block id width is configurable at the IC level. 348 * 349 * chipid << 24 | 0000 0000 0000 0000 1 threadid (7Bit) 350 * chipid << 24 | 0000 0000 0000 0001 threadid (8Bit) 351 */ 352 static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 353 { 354 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 355 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 356 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 357 uint8_t blk = xive2_router_get_block_id(xrtr); 358 uint8_t tid_shift = 359 xive2_router_get_config(xrtr) & XIVE2_THREADID_8BITS ? 8 : 7; 360 uint8_t tid_mask = (1 << tid_shift) - 1; 361 362 return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask)); 363 } 364 365 static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr, XiveTCTX *tctx, 366 hwaddr offset, unsigned size, uint8_t ring) 367 { 368 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 369 uint32_t target_ringw2 = xive_tctx_word2(&tctx->regs[ring]); 370 uint32_t cam = be32_to_cpu(target_ringw2); 371 uint8_t nvp_blk; 372 uint32_t nvp_idx; 373 uint8_t cur_ring; 374 bool valid; 375 bool do_save; 376 377 xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &valid, &do_save); 378 379 if (!valid) { 380 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?\n", 381 nvp_blk, nvp_idx); 382 } 383 384 /* Invalidate CAM line of requested ring and all lower rings */ 385 for (cur_ring = TM_QW0_USER; cur_ring <= ring; 386 cur_ring += XIVE_TM_RING_SIZE) { 387 uint32_t ringw2 = xive_tctx_word2(&tctx->regs[cur_ring]); 388 uint32_t ringw2_new = xive_set_field32(TM2_QW1W2_VO, ringw2, 0); 389 memcpy(&tctx->regs[cur_ring + TM_WORD2], &ringw2_new, 4); 390 } 391 392 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) { 393 xive2_tctx_save_ctx(xrtr, tctx, nvp_blk, nvp_idx, ring); 394 } 395 396 /* 397 * Lower external interrupt line of requested ring and below except for 398 * USER, which doesn't exist. 399 */ 400 for (cur_ring = TM_QW1_OS; cur_ring <= ring; 401 cur_ring += XIVE_TM_RING_SIZE) { 402 xive_tctx_reset_signal(tctx, cur_ring); 403 } 404 return target_ringw2; 405 } 406 407 uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 408 hwaddr offset, unsigned size) 409 { 410 return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW1_OS); 411 } 412 413 #define REPORT_LINE_GEN1_SIZE 16 414 415 static void xive2_tm_report_line_gen1(XiveTCTX *tctx, uint8_t *data, 416 uint8_t size) 417 { 418 uint8_t *regs = tctx->regs; 419 420 g_assert(size == REPORT_LINE_GEN1_SIZE); 421 memset(data, 0, size); 422 /* 423 * See xive architecture for description of what is saved. It is 424 * hand-picked information to fit in 16 bytes. 425 */ 426 data[0x0] = regs[TM_QW3_HV_PHYS + TM_NSR]; 427 data[0x1] = regs[TM_QW3_HV_PHYS + TM_CPPR]; 428 data[0x2] = regs[TM_QW3_HV_PHYS + TM_IPB]; 429 data[0x3] = regs[TM_QW2_HV_POOL + TM_IPB]; 430 data[0x4] = regs[TM_QW1_OS + TM_ACK_CNT]; 431 data[0x5] = regs[TM_QW3_HV_PHYS + TM_LGS]; 432 data[0x6] = 0xFF; 433 data[0x7] = regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x80; 434 data[0x7] |= (regs[TM_QW2_HV_POOL + TM_WORD2] & 0x80) >> 1; 435 data[0x7] |= (regs[TM_QW1_OS + TM_WORD2] & 0x80) >> 2; 436 data[0x7] |= (regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x3); 437 data[0x8] = regs[TM_QW1_OS + TM_NSR]; 438 data[0x9] = regs[TM_QW1_OS + TM_CPPR]; 439 data[0xA] = regs[TM_QW1_OS + TM_IPB]; 440 data[0xB] = regs[TM_QW1_OS + TM_LGS]; 441 if (regs[TM_QW0_USER + TM_WORD2] & 0x80) { 442 /* 443 * Logical server extension, except VU bit replaced by EB bit 444 * from NSR 445 */ 446 data[0xC] = regs[TM_QW0_USER + TM_WORD2]; 447 data[0xC] &= ~0x80; 448 data[0xC] |= regs[TM_QW0_USER + TM_NSR] & 0x80; 449 data[0xD] = regs[TM_QW0_USER + TM_WORD2 + 1]; 450 data[0xE] = regs[TM_QW0_USER + TM_WORD2 + 2]; 451 data[0xF] = regs[TM_QW0_USER + TM_WORD2 + 3]; 452 } 453 } 454 455 static void xive2_tm_pull_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 456 hwaddr offset, uint64_t value, 457 unsigned size, uint8_t ring) 458 { 459 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 460 uint32_t hw_cam, nvp_idx, xive2_cfg, reserved; 461 uint8_t nvp_blk; 462 Xive2Nvp nvp; 463 uint64_t phys_addr; 464 MemTxResult result; 465 466 hw_cam = xive2_tctx_hw_cam_line(xptr, tctx); 467 nvp_blk = xive2_nvp_blk(hw_cam); 468 nvp_idx = xive2_nvp_idx(hw_cam); 469 470 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 471 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 472 nvp_blk, nvp_idx); 473 return; 474 } 475 476 if (!xive2_nvp_is_valid(&nvp)) { 477 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 478 nvp_blk, nvp_idx); 479 return; 480 } 481 482 xive2_cfg = xive2_router_get_config(xrtr); 483 484 phys_addr = xive2_nvp_reporting_addr(&nvp) + 0x80; /* odd line */ 485 if (xive2_cfg & XIVE2_GEN1_TIMA_OS) { 486 uint8_t pull_ctxt[REPORT_LINE_GEN1_SIZE]; 487 488 xive2_tm_report_line_gen1(tctx, pull_ctxt, REPORT_LINE_GEN1_SIZE); 489 result = dma_memory_write(&address_space_memory, phys_addr, 490 pull_ctxt, REPORT_LINE_GEN1_SIZE, 491 MEMTXATTRS_UNSPECIFIED); 492 assert(result == MEMTX_OK); 493 } else { 494 result = dma_memory_write(&address_space_memory, phys_addr, 495 &tctx->regs, sizeof(tctx->regs), 496 MEMTXATTRS_UNSPECIFIED); 497 assert(result == MEMTX_OK); 498 reserved = 0xFFFFFFFF; 499 result = dma_memory_write(&address_space_memory, phys_addr + 12, 500 &reserved, sizeof(reserved), 501 MEMTXATTRS_UNSPECIFIED); 502 assert(result == MEMTX_OK); 503 } 504 505 /* the rest is similar to pull context to registers */ 506 xive2_tm_pull_ctx(xptr, tctx, offset, size, ring); 507 } 508 509 void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 510 hwaddr offset, uint64_t value, unsigned size) 511 { 512 xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW1_OS); 513 } 514 515 516 void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 517 hwaddr offset, uint64_t value, unsigned size) 518 { 519 xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW3_HV_PHYS); 520 } 521 522 static uint8_t xive2_tctx_restore_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx, 523 uint8_t nvp_blk, uint32_t nvp_idx, 524 Xive2Nvp *nvp) 525 { 526 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 527 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 528 uint8_t cppr; 529 530 if (!xive2_nvp_is_hw(nvp)) { 531 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n", 532 nvp_blk, nvp_idx); 533 return 0; 534 } 535 536 cppr = xive_get_field32(NVP2_W2_CPPR, nvp->w2); 537 nvp->w2 = xive_set_field32(NVP2_W2_CPPR, nvp->w2, 0); 538 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 2); 539 540 tctx->regs[TM_QW1_OS + TM_CPPR] = cppr; 541 tctx->regs[TM_QW1_OS + TM_LSMFB] = xive_get_field32(NVP2_W2_LSMFB, nvp->w2); 542 tctx->regs[TM_QW1_OS + TM_LGS] = xive_get_field32(NVP2_W2_LGS, nvp->w2); 543 tctx->regs[TM_QW1_OS + TM_T] = xive_get_field32(NVP2_W2_T, nvp->w2); 544 545 nvp->w1 = xive_set_field32(NVP2_W1_CO, nvp->w1, 1); 546 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID_VALID, nvp->w1, 1); 547 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp->w1, pir); 548 549 /* 550 * Checkout privilege: 0:OS, 1:Pool, 2:Hard 551 * 552 * TODO: we only support OS push/pull 553 */ 554 nvp->w1 = xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 0); 555 556 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 1); 557 558 /* return restored CPPR to generate a CPU exception if needed */ 559 return cppr; 560 } 561 562 static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx, 563 uint8_t nvp_blk, uint32_t nvp_idx, 564 bool do_restore) 565 { 566 uint8_t ipb; 567 uint8_t backlog_level; 568 uint8_t backlog_prio; 569 uint8_t *regs = &tctx->regs[TM_QW1_OS]; 570 Xive2Nvp nvp; 571 572 /* 573 * Grab the associated thread interrupt context registers in the 574 * associated NVP 575 */ 576 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 577 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 578 nvp_blk, nvp_idx); 579 return; 580 } 581 582 if (!xive2_nvp_is_valid(&nvp)) { 583 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 584 nvp_blk, nvp_idx); 585 return; 586 } 587 588 /* Automatically restore thread context registers */ 589 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && 590 do_restore) { 591 xive2_tctx_restore_os_ctx(xrtr, tctx, nvp_blk, nvp_idx, &nvp); 592 } 593 594 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2); 595 if (ipb) { 596 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, 0); 597 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 598 } 599 regs[TM_IPB] |= ipb; 600 backlog_prio = xive_ipb_to_pipr(ipb); 601 backlog_level = 0; 602 603 /* 604 * Compute the PIPR based on the restored state. 605 * It will raise the External interrupt signal if needed. 606 */ 607 xive_tctx_pipr_update(tctx, TM_QW1_OS, backlog_prio, backlog_level); 608 } 609 610 /* 611 * Updating the OS CAM line can trigger a resend of interrupt 612 */ 613 void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 614 hwaddr offset, uint64_t value, unsigned size) 615 { 616 uint32_t cam; 617 uint32_t qw1w2; 618 uint64_t qw1dw1; 619 uint8_t nvp_blk; 620 uint32_t nvp_idx; 621 bool vo; 622 bool do_restore; 623 624 /* First update the thead context */ 625 switch (size) { 626 case 4: 627 cam = value; 628 qw1w2 = cpu_to_be32(cam); 629 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 630 break; 631 case 8: 632 cam = value >> 32; 633 qw1dw1 = cpu_to_be64(value); 634 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1dw1, 8); 635 break; 636 default: 637 g_assert_not_reached(); 638 } 639 640 xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore); 641 642 /* Check the interrupt pending bits */ 643 if (vo) { 644 xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, nvp_blk, nvp_idx, 645 do_restore); 646 } 647 } 648 649 static void xive2_tctx_set_target(XiveTCTX *tctx, uint8_t ring, uint8_t target) 650 { 651 uint8_t *regs = &tctx->regs[ring]; 652 653 regs[TM_T] = target; 654 } 655 656 void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx, 657 hwaddr offset, uint64_t value, unsigned size) 658 { 659 xive2_tctx_set_target(tctx, TM_QW3_HV_PHYS, value & 0xff); 660 } 661 662 /* 663 * XIVE Router (aka. Virtualization Controller or IVRE) 664 */ 665 666 int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 667 Xive2Eas *eas) 668 { 669 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 670 671 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 672 } 673 674 static 675 int xive2_router_get_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 676 uint8_t *pq) 677 { 678 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 679 680 return xrc->get_pq(xrtr, eas_blk, eas_idx, pq); 681 } 682 683 static 684 int xive2_router_set_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 685 uint8_t *pq) 686 { 687 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 688 689 return xrc->set_pq(xrtr, eas_blk, eas_idx, pq); 690 } 691 692 int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 693 Xive2End *end) 694 { 695 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 696 697 return xrc->get_end(xrtr, end_blk, end_idx, end); 698 } 699 700 int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 701 Xive2End *end, uint8_t word_number) 702 { 703 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 704 705 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 706 } 707 708 int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 709 Xive2Nvp *nvp) 710 { 711 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 712 713 return xrc->get_nvp(xrtr, nvp_blk, nvp_idx, nvp); 714 } 715 716 int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 717 Xive2Nvp *nvp, uint8_t word_number) 718 { 719 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 720 721 return xrc->write_nvp(xrtr, nvp_blk, nvp_idx, nvp, word_number); 722 } 723 724 int xive2_router_get_nvgc(Xive2Router *xrtr, bool crowd, 725 uint8_t nvgc_blk, uint32_t nvgc_idx, 726 Xive2Nvgc *nvgc) 727 { 728 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 729 730 return xrc->get_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc); 731 } 732 733 int xive2_router_write_nvgc(Xive2Router *xrtr, bool crowd, 734 uint8_t nvgc_blk, uint32_t nvgc_idx, 735 Xive2Nvgc *nvgc) 736 { 737 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 738 739 return xrc->write_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc); 740 } 741 742 /* 743 * The thread context register words are in big-endian format. 744 */ 745 int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 746 uint8_t format, 747 uint8_t nvt_blk, uint32_t nvt_idx, 748 bool cam_ignore, uint32_t logic_serv) 749 { 750 uint32_t cam = xive2_nvp_cam_line(nvt_blk, nvt_idx); 751 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 752 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 753 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 754 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 755 756 /* 757 * TODO (PowerNV): ignore mode. The low order bits of the NVT 758 * identifier are ignored in the "CAM" match. 759 */ 760 761 if (format == 0) { 762 if (cam_ignore == true) { 763 /* 764 * F=0 & i=1: Logical server notification (bits ignored at 765 * the end of the NVT identifier) 766 */ 767 qemu_log_mask(LOG_UNIMP, "XIVE: no support for LS NVT %x/%x\n", 768 nvt_blk, nvt_idx); 769 return -1; 770 } 771 772 /* F=0 & i=0: Specific NVT notification */ 773 774 /* PHYS ring */ 775 if ((be32_to_cpu(qw3w2) & TM2_QW3W2_VT) && 776 cam == xive2_tctx_hw_cam_line(xptr, tctx)) { 777 return TM_QW3_HV_PHYS; 778 } 779 780 /* HV POOL ring */ 781 if ((be32_to_cpu(qw2w2) & TM2_QW2W2_VP) && 782 cam == xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2)) { 783 return TM_QW2_HV_POOL; 784 } 785 786 /* OS ring */ 787 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 788 cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) { 789 return TM_QW1_OS; 790 } 791 } else { 792 /* F=1 : User level Event-Based Branch (EBB) notification */ 793 794 /* USER ring */ 795 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 796 (cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) && 797 (be32_to_cpu(qw0w2) & TM2_QW0W2_VU) && 798 (logic_serv == xive_get_field32(TM2_QW0W2_LOGIC_SERV, qw0w2))) { 799 return TM_QW0_USER; 800 } 801 } 802 return -1; 803 } 804 805 static void xive2_router_realize(DeviceState *dev, Error **errp) 806 { 807 Xive2Router *xrtr = XIVE2_ROUTER(dev); 808 809 assert(xrtr->xfb); 810 } 811 812 /* 813 * Notification using the END ESe/ESn bit (Event State Buffer for 814 * escalation and notification). Profide further coalescing in the 815 * Router. 816 */ 817 static bool xive2_router_end_es_notify(Xive2Router *xrtr, uint8_t end_blk, 818 uint32_t end_idx, Xive2End *end, 819 uint32_t end_esmask) 820 { 821 uint8_t pq = xive_get_field32(end_esmask, end->w1); 822 bool notify = xive_esb_trigger(&pq); 823 824 if (pq != xive_get_field32(end_esmask, end->w1)) { 825 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 826 xive2_router_write_end(xrtr, end_blk, end_idx, end, 1); 827 } 828 829 /* ESe/n[Q]=1 : end of notification */ 830 return notify; 831 } 832 833 /* 834 * An END trigger can come from an event trigger (IPI or HW) or from 835 * another chip. We don't model the PowerBus but the END trigger 836 * message has the same parameters than in the function below. 837 */ 838 static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk, 839 uint32_t end_idx, uint32_t end_data) 840 { 841 Xive2End end; 842 uint8_t priority; 843 uint8_t format; 844 bool found; 845 Xive2Nvp nvp; 846 uint8_t nvp_blk; 847 uint32_t nvp_idx; 848 849 /* END cache lookup */ 850 if (xive2_router_get_end(xrtr, end_blk, end_idx, &end)) { 851 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 852 end_idx); 853 return; 854 } 855 856 if (!xive2_end_is_valid(&end)) { 857 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 858 end_blk, end_idx); 859 return; 860 } 861 862 if (xive2_end_is_enqueue(&end)) { 863 xive2_end_enqueue(&end, end_data); 864 /* Enqueuing event data modifies the EQ toggle and index */ 865 xive2_router_write_end(xrtr, end_blk, end_idx, &end, 1); 866 } 867 868 /* 869 * When the END is silent, we skip the notification part. 870 */ 871 if (xive2_end_is_silent_escalation(&end)) { 872 goto do_escalation; 873 } 874 875 /* 876 * The W7 format depends on the F bit in W6. It defines the type 877 * of the notification : 878 * 879 * F=0 : single or multiple NVP notification 880 * F=1 : User level Event-Based Branch (EBB) notification, no 881 * priority 882 */ 883 format = xive_get_field32(END2_W6_FORMAT_BIT, end.w6); 884 priority = xive_get_field32(END2_W7_F0_PRIORITY, end.w7); 885 886 /* The END is masked */ 887 if (format == 0 && priority == 0xff) { 888 return; 889 } 890 891 /* 892 * Check the END ESn (Event State Buffer for notification) for 893 * even further coalescing in the Router 894 */ 895 if (!xive2_end_is_notify(&end)) { 896 /* ESn[Q]=1 : end of notification */ 897 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 898 &end, END2_W1_ESn)) { 899 return; 900 } 901 } 902 903 /* 904 * Follows IVPE notification 905 */ 906 nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end.w6); 907 nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end.w6); 908 909 /* NVP cache lookup */ 910 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 911 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVP %x/%x\n", 912 nvp_blk, nvp_idx); 913 return; 914 } 915 916 if (!xive2_nvp_is_valid(&nvp)) { 917 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is invalid\n", 918 nvp_blk, nvp_idx); 919 return; 920 } 921 922 found = xive_presenter_notify(xrtr->xfb, format, nvp_blk, nvp_idx, 923 xive2_end_is_ignore(&end), 924 priority, 925 xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w7)); 926 927 /* TODO: Auto EOI. */ 928 929 if (found) { 930 return; 931 } 932 933 /* 934 * If no matching NVP is dispatched on a HW thread : 935 * - specific VP: update the NVP structure if backlog is activated 936 * - logical server : forward request to IVPE (not supported) 937 */ 938 if (xive2_end_is_backlog(&end)) { 939 uint8_t ipb; 940 941 if (format == 1) { 942 qemu_log_mask(LOG_GUEST_ERROR, 943 "XIVE: END %x/%x invalid config: F1 & backlog\n", 944 end_blk, end_idx); 945 return; 946 } 947 948 /* 949 * Record the IPB in the associated NVP structure for later 950 * use. The presenter will resend the interrupt when the vCPU 951 * is dispatched again on a HW thread. 952 */ 953 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2) | 954 xive_priority_to_ipb(priority); 955 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb); 956 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 957 958 /* 959 * On HW, follows a "Broadcast Backlog" to IVPEs 960 */ 961 } 962 963 do_escalation: 964 /* 965 * If activated, escalate notification using the ESe PQ bits and 966 * the EAS in w4-5 967 */ 968 if (!xive2_end_is_escalate(&end)) { 969 return; 970 } 971 972 /* 973 * Check the END ESe (Event State Buffer for escalation) for even 974 * further coalescing in the Router 975 */ 976 if (!xive2_end_is_uncond_escalation(&end)) { 977 /* ESe[Q]=1 : end of escalation notification */ 978 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 979 &end, END2_W1_ESe)) { 980 return; 981 } 982 } 983 984 /* 985 * The END trigger becomes an Escalation trigger 986 */ 987 xive2_router_end_notify(xrtr, 988 xive_get_field32(END2_W4_END_BLOCK, end.w4), 989 xive_get_field32(END2_W4_ESC_END_INDEX, end.w4), 990 xive_get_field32(END2_W5_ESC_END_DATA, end.w5)); 991 } 992 993 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) 994 { 995 Xive2Router *xrtr = XIVE2_ROUTER(xn); 996 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 997 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 998 Xive2Eas eas; 999 1000 /* EAS cache lookup */ 1001 if (xive2_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1002 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1003 return; 1004 } 1005 1006 if (!pq_checked) { 1007 bool notify; 1008 uint8_t pq; 1009 1010 /* PQ cache lookup */ 1011 if (xive2_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) { 1012 /* Set FIR */ 1013 g_assert_not_reached(); 1014 } 1015 1016 notify = xive_esb_trigger(&pq); 1017 1018 if (xive2_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) { 1019 /* Set FIR */ 1020 g_assert_not_reached(); 1021 } 1022 1023 if (!notify) { 1024 return; 1025 } 1026 } 1027 1028 if (!xive2_eas_is_valid(&eas)) { 1029 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %x\n", lisn); 1030 return; 1031 } 1032 1033 if (xive2_eas_is_masked(&eas)) { 1034 /* Notification completed */ 1035 return; 1036 } 1037 1038 /* 1039 * The event trigger becomes an END trigger 1040 */ 1041 xive2_router_end_notify(xrtr, 1042 xive_get_field64(EAS2_END_BLOCK, eas.w), 1043 xive_get_field64(EAS2_END_INDEX, eas.w), 1044 xive_get_field64(EAS2_END_DATA, eas.w)); 1045 } 1046 1047 static const Property xive2_router_properties[] = { 1048 DEFINE_PROP_LINK("xive-fabric", Xive2Router, xfb, 1049 TYPE_XIVE_FABRIC, XiveFabric *), 1050 }; 1051 1052 static void xive2_router_class_init(ObjectClass *klass, void *data) 1053 { 1054 DeviceClass *dc = DEVICE_CLASS(klass); 1055 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1056 1057 dc->desc = "XIVE2 Router Engine"; 1058 device_class_set_props(dc, xive2_router_properties); 1059 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 1060 dc->realize = xive2_router_realize; 1061 xnc->notify = xive2_router_notify; 1062 } 1063 1064 static const TypeInfo xive2_router_info = { 1065 .name = TYPE_XIVE2_ROUTER, 1066 .parent = TYPE_SYS_BUS_DEVICE, 1067 .abstract = true, 1068 .instance_size = sizeof(Xive2Router), 1069 .class_size = sizeof(Xive2RouterClass), 1070 .class_init = xive2_router_class_init, 1071 .interfaces = (InterfaceInfo[]) { 1072 { TYPE_XIVE_NOTIFIER }, 1073 { TYPE_XIVE_PRESENTER }, 1074 { } 1075 } 1076 }; 1077 1078 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 1079 { 1080 return !((addr >> shift) & 1); 1081 } 1082 1083 static uint64_t xive2_end_source_read(void *opaque, hwaddr addr, unsigned size) 1084 { 1085 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 1086 uint32_t offset = addr & 0xFFF; 1087 uint8_t end_blk; 1088 uint32_t end_idx; 1089 Xive2End end; 1090 uint32_t end_esmask; 1091 uint8_t pq; 1092 uint64_t ret; 1093 1094 /* 1095 * The block id should be deduced from the load address on the END 1096 * ESB MMIO but our model only supports a single block per XIVE chip. 1097 */ 1098 end_blk = xive2_router_get_block_id(xsrc->xrtr); 1099 end_idx = addr >> (xsrc->esb_shift + 1); 1100 1101 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1102 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1103 end_idx); 1104 return -1; 1105 } 1106 1107 if (!xive2_end_is_valid(&end)) { 1108 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1109 end_blk, end_idx); 1110 return -1; 1111 } 1112 1113 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 1114 END2_W1_ESe; 1115 pq = xive_get_field32(end_esmask, end.w1); 1116 1117 switch (offset) { 1118 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1119 ret = xive_esb_eoi(&pq); 1120 1121 /* Forward the source event notification for routing ?? */ 1122 break; 1123 1124 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1125 ret = pq; 1126 break; 1127 1128 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1129 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1130 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1131 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1132 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1133 break; 1134 default: 1135 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1136 offset); 1137 return -1; 1138 } 1139 1140 if (pq != xive_get_field32(end_esmask, end.w1)) { 1141 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1142 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1143 } 1144 1145 return ret; 1146 } 1147 1148 static void xive2_end_source_write(void *opaque, hwaddr addr, 1149 uint64_t value, unsigned size) 1150 { 1151 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 1152 uint32_t offset = addr & 0xFFF; 1153 uint8_t end_blk; 1154 uint32_t end_idx; 1155 Xive2End end; 1156 uint32_t end_esmask; 1157 uint8_t pq; 1158 bool notify = false; 1159 1160 /* 1161 * The block id should be deduced from the load address on the END 1162 * ESB MMIO but our model only supports a single block per XIVE chip. 1163 */ 1164 end_blk = xive2_router_get_block_id(xsrc->xrtr); 1165 end_idx = addr >> (xsrc->esb_shift + 1); 1166 1167 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1168 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1169 end_idx); 1170 return; 1171 } 1172 1173 if (!xive2_end_is_valid(&end)) { 1174 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1175 end_blk, end_idx); 1176 return; 1177 } 1178 1179 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 1180 END2_W1_ESe; 1181 pq = xive_get_field32(end_esmask, end.w1); 1182 1183 switch (offset) { 1184 case 0 ... 0x3FF: 1185 notify = xive_esb_trigger(&pq); 1186 break; 1187 1188 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 1189 /* TODO: can we check StoreEOI availability from the router ? */ 1190 notify = xive_esb_eoi(&pq); 1191 break; 1192 1193 case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF: 1194 if (end_esmask == END2_W1_ESe) { 1195 qemu_log_mask(LOG_GUEST_ERROR, 1196 "XIVE: END %x/%x can not EQ inject on ESe\n", 1197 end_blk, end_idx); 1198 return; 1199 } 1200 notify = true; 1201 break; 1202 1203 default: 1204 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB write addr %d\n", 1205 offset); 1206 return; 1207 } 1208 1209 if (pq != xive_get_field32(end_esmask, end.w1)) { 1210 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1211 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1212 } 1213 1214 /* TODO: Forward the source event notification for routing */ 1215 if (notify) { 1216 ; 1217 } 1218 } 1219 1220 static const MemoryRegionOps xive2_end_source_ops = { 1221 .read = xive2_end_source_read, 1222 .write = xive2_end_source_write, 1223 .endianness = DEVICE_BIG_ENDIAN, 1224 .valid = { 1225 .min_access_size = 1, 1226 .max_access_size = 8, 1227 }, 1228 .impl = { 1229 .min_access_size = 1, 1230 .max_access_size = 8, 1231 }, 1232 }; 1233 1234 static void xive2_end_source_realize(DeviceState *dev, Error **errp) 1235 { 1236 Xive2EndSource *xsrc = XIVE2_END_SOURCE(dev); 1237 1238 assert(xsrc->xrtr); 1239 1240 if (!xsrc->nr_ends) { 1241 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1242 return; 1243 } 1244 1245 if (xsrc->esb_shift != XIVE_ESB_4K && 1246 xsrc->esb_shift != XIVE_ESB_64K) { 1247 error_setg(errp, "Invalid ESB shift setting"); 1248 return; 1249 } 1250 1251 /* 1252 * Each END is assigned an even/odd pair of MMIO pages, the even page 1253 * manages the ESn field while the odd page manages the ESe field. 1254 */ 1255 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1256 &xive2_end_source_ops, xsrc, "xive.end", 1257 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 1258 } 1259 1260 static const Property xive2_end_source_properties[] = { 1261 DEFINE_PROP_UINT32("nr-ends", Xive2EndSource, nr_ends, 0), 1262 DEFINE_PROP_UINT32("shift", Xive2EndSource, esb_shift, XIVE_ESB_64K), 1263 DEFINE_PROP_LINK("xive", Xive2EndSource, xrtr, TYPE_XIVE2_ROUTER, 1264 Xive2Router *), 1265 }; 1266 1267 static void xive2_end_source_class_init(ObjectClass *klass, void *data) 1268 { 1269 DeviceClass *dc = DEVICE_CLASS(klass); 1270 1271 dc->desc = "XIVE END Source"; 1272 device_class_set_props(dc, xive2_end_source_properties); 1273 dc->realize = xive2_end_source_realize; 1274 dc->user_creatable = false; 1275 } 1276 1277 static const TypeInfo xive2_end_source_info = { 1278 .name = TYPE_XIVE2_END_SOURCE, 1279 .parent = TYPE_DEVICE, 1280 .instance_size = sizeof(Xive2EndSource), 1281 .class_init = xive2_end_source_class_init, 1282 }; 1283 1284 static void xive2_register_types(void) 1285 { 1286 type_register_static(&xive2_router_info); 1287 type_register_static(&xive2_end_source_info); 1288 } 1289 1290 type_init(xive2_register_types) 1291