1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2024, IBM Corporation.. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/log.h" 11 #include "qemu/module.h" 12 #include "qapi/error.h" 13 #include "target/ppc/cpu.h" 14 #include "system/cpus.h" 15 #include "system/dma.h" 16 #include "hw/qdev-properties.h" 17 #include "hw/ppc/xive.h" 18 #include "hw/ppc/xive2.h" 19 #include "hw/ppc/xive2_regs.h" 20 21 uint32_t xive2_router_get_config(Xive2Router *xrtr) 22 { 23 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 24 25 return xrc->get_config(xrtr); 26 } 27 28 static int xive2_router_get_block_id(Xive2Router *xrtr) 29 { 30 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 31 32 return xrc->get_block_id(xrtr); 33 } 34 35 static uint64_t xive2_nvp_reporting_addr(Xive2Nvp *nvp) 36 { 37 uint64_t cache_addr; 38 39 cache_addr = xive_get_field32(NVP2_W6_REPORTING_LINE, nvp->w6) << 24 | 40 xive_get_field32(NVP2_W7_REPORTING_LINE, nvp->w7); 41 cache_addr <<= 8; /* aligned on a cache line pair */ 42 return cache_addr; 43 } 44 45 static uint32_t xive2_nvgc_get_backlog(Xive2Nvgc *nvgc, uint8_t priority) 46 { 47 uint32_t val = 0; 48 uint8_t *ptr, i; 49 50 if (priority > 7) { 51 return 0; 52 } 53 54 /* 55 * The per-priority backlog counters are 24-bit and the structure 56 * is stored in big endian 57 */ 58 ptr = (uint8_t *)&nvgc->w2 + priority * 3; 59 for (i = 0; i < 3; i++, ptr++) { 60 val = (val << 8) + *ptr; 61 } 62 return val; 63 } 64 65 void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf) 66 { 67 if (!xive2_eas_is_valid(eas)) { 68 return; 69 } 70 71 g_string_append_printf(buf, " %08x %s end:%02x/%04x data:%08x\n", 72 lisn, xive2_eas_is_masked(eas) ? "M" : " ", 73 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 74 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 75 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 76 } 77 78 void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, GString *buf) 79 { 80 uint64_t qaddr_base = xive2_end_qaddr(end); 81 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 82 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 83 uint32_t qentries = 1 << (qsize + 10); 84 int i; 85 86 /* 87 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 88 */ 89 g_string_append_printf(buf, " [ "); 90 qindex = (qindex - (width - 1)) & (qentries - 1); 91 for (i = 0; i < width; i++) { 92 uint64_t qaddr = qaddr_base + (qindex << 2); 93 uint32_t qdata = -1; 94 95 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 96 sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { 97 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 98 HWADDR_PRIx "\n", qaddr); 99 return; 100 } 101 g_string_append_printf(buf, "%s%08x ", i == width - 1 ? "^" : "", 102 be32_to_cpu(qdata)); 103 qindex = (qindex + 1) & (qentries - 1); 104 } 105 g_string_append_printf(buf, "]"); 106 } 107 108 void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, GString *buf) 109 { 110 uint64_t qaddr_base = xive2_end_qaddr(end); 111 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 112 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 113 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 114 uint32_t qentries = 1 << (qsize + 10); 115 116 uint32_t nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6); 117 uint32_t nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6); 118 uint8_t priority = xive_get_field32(END2_W7_F0_PRIORITY, end->w7); 119 uint8_t pq; 120 121 if (!xive2_end_is_valid(end)) { 122 return; 123 } 124 125 pq = xive_get_field32(END2_W1_ESn, end->w1); 126 127 g_string_append_printf(buf, 128 " %08x %c%c %c%c%c%c%c%c%c%c%c%c%c %c%c " 129 "prio:%d nvp:%02x/%04x", 130 end_idx, 131 pq & XIVE_ESB_VAL_P ? 'P' : '-', 132 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 133 xive2_end_is_valid(end) ? 'v' : '-', 134 xive2_end_is_enqueue(end) ? 'q' : '-', 135 xive2_end_is_notify(end) ? 'n' : '-', 136 xive2_end_is_backlog(end) ? 'b' : '-', 137 xive2_end_is_precluded_escalation(end) ? 'p' : '-', 138 xive2_end_is_escalate(end) ? 'e' : '-', 139 xive2_end_is_escalate_end(end) ? 'N' : '-', 140 xive2_end_is_uncond_escalation(end) ? 'u' : '-', 141 xive2_end_is_silent_escalation(end) ? 's' : '-', 142 xive2_end_is_firmware1(end) ? 'f' : '-', 143 xive2_end_is_firmware2(end) ? 'F' : '-', 144 xive2_end_is_ignore(end) ? 'i' : '-', 145 xive2_end_is_crowd(end) ? 'c' : '-', 146 priority, nvp_blk, nvp_idx); 147 148 if (qaddr_base) { 149 g_string_append_printf(buf, " eq:@%08"PRIx64"% 6d/%5d ^%d", 150 qaddr_base, qindex, qentries, qgen); 151 xive2_end_queue_pic_print_info(end, 6, buf); 152 } 153 g_string_append_c(buf, '\n'); 154 } 155 156 void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx, 157 GString *buf) 158 { 159 Xive2Eas *eas = (Xive2Eas *) &end->w4; 160 uint8_t pq; 161 162 if (!xive2_end_is_escalate(end)) { 163 return; 164 } 165 166 pq = xive_get_field32(END2_W1_ESe, end->w1); 167 168 g_string_append_printf(buf, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 169 end_idx, 170 pq & XIVE_ESB_VAL_P ? 'P' : '-', 171 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 172 xive2_eas_is_valid(eas) ? 'v' : ' ', 173 xive2_eas_is_masked(eas) ? 'M' : ' ', 174 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 175 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 176 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 177 } 178 179 void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, GString *buf) 180 { 181 uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5); 182 uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5); 183 uint64_t cache_line = xive2_nvp_reporting_addr(nvp); 184 185 if (!xive2_nvp_is_valid(nvp)) { 186 return; 187 } 188 189 g_string_append_printf(buf, " %08x end:%02x/%04x IPB:%02x PGoFirst:%02x", 190 nvp_idx, eq_blk, eq_idx, 191 xive_get_field32(NVP2_W2_IPB, nvp->w2), 192 xive_get_field32(NVP2_W0_PGOFIRST, nvp->w0)); 193 if (cache_line) { 194 g_string_append_printf(buf, " reporting CL:%016"PRIx64, cache_line); 195 } 196 197 /* 198 * When the NVP is HW controlled, more fields are updated 199 */ 200 if (xive2_nvp_is_hw(nvp)) { 201 g_string_append_printf(buf, " CPPR:%02x", 202 xive_get_field32(NVP2_W2_CPPR, nvp->w2)); 203 if (xive2_nvp_is_co(nvp)) { 204 g_string_append_printf(buf, " CO:%04x", 205 xive_get_field32(NVP2_W1_CO_THRID, nvp->w1)); 206 } 207 } 208 g_string_append_c(buf, '\n'); 209 } 210 211 void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uint32_t nvgc_idx, GString *buf) 212 { 213 uint8_t i; 214 215 if (!xive2_nvgc_is_valid(nvgc)) { 216 return; 217 } 218 219 g_string_append_printf(buf, " %08x PGoNext:%02x bklog: ", nvgc_idx, 220 xive_get_field32(NVGC2_W0_PGONEXT, nvgc->w0)); 221 for (i = 0; i <= XIVE_PRIORITY_MAX; i++) { 222 g_string_append_printf(buf, "[%d]=0x%x ", 223 i, xive2_nvgc_get_backlog(nvgc, i)); 224 } 225 g_string_append_printf(buf, "\n"); 226 } 227 228 static void xive2_end_enqueue(Xive2End *end, uint32_t data) 229 { 230 uint64_t qaddr_base = xive2_end_qaddr(end); 231 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, end->w3); 232 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 233 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 234 235 uint64_t qaddr = qaddr_base + (qindex << 2); 236 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 237 uint32_t qentries = 1 << (qsize + 10); 238 239 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata), 240 MEMTXATTRS_UNSPECIFIED)) { 241 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 242 HWADDR_PRIx "\n", qaddr); 243 return; 244 } 245 246 qindex = (qindex + 1) & (qentries - 1); 247 if (qindex == 0) { 248 qgen ^= 1; 249 end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen); 250 251 /* TODO(PowerNV): reset GF bit on a cache watch operation */ 252 end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, qgen); 253 } 254 end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex); 255 } 256 257 /* 258 * XIVE Thread Interrupt Management Area (TIMA) - Gen2 mode 259 * 260 * TIMA Gen2 VP “save & restore” (S&R) indicated by H bit next to V bit 261 * 262 * - if a context is enabled with the H bit set, the VP context 263 * information is retrieved from the NVP structure (“check out”) 264 * and stored back on a context pull (“check in”), the SW receives 265 * the same context pull information as on P9 266 * 267 * - the H bit cannot be changed while the V bit is set, i.e. a 268 * context cannot be set up in the TIMA and then be “pushed” into 269 * the NVP by changing the H bit while the context is enabled 270 */ 271 272 static void xive2_tctx_save_ctx(Xive2Router *xrtr, XiveTCTX *tctx, 273 uint8_t nvp_blk, uint32_t nvp_idx, 274 uint8_t ring) 275 { 276 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 277 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 278 Xive2Nvp nvp; 279 uint8_t *regs = &tctx->regs[ring]; 280 281 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 282 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 283 nvp_blk, nvp_idx); 284 return; 285 } 286 287 if (!xive2_nvp_is_valid(&nvp)) { 288 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 289 nvp_blk, nvp_idx); 290 return; 291 } 292 293 if (!xive2_nvp_is_hw(&nvp)) { 294 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n", 295 nvp_blk, nvp_idx); 296 return; 297 } 298 299 if (!xive2_nvp_is_co(&nvp)) { 300 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not checkout\n", 301 nvp_blk, nvp_idx); 302 return; 303 } 304 305 if (xive_get_field32(NVP2_W1_CO_THRID_VALID, nvp.w1) && 306 xive_get_field32(NVP2_W1_CO_THRID, nvp.w1) != pir) { 307 qemu_log_mask(LOG_GUEST_ERROR, 308 "XIVE: NVP %x/%x invalid checkout Thread %x\n", 309 nvp_blk, nvp_idx, pir); 310 return; 311 } 312 313 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, regs[TM_IPB]); 314 nvp.w2 = xive_set_field32(NVP2_W2_CPPR, nvp.w2, regs[TM_CPPR]); 315 if (nvp.w0 & NVP2_W0_L) { 316 /* 317 * Typically not used. If LSMFB is restored with 0, it will 318 * force a backlog rescan 319 */ 320 nvp.w2 = xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]); 321 } 322 if (nvp.w0 & NVP2_W0_G) { 323 nvp.w2 = xive_set_field32(NVP2_W2_LGS, nvp.w2, regs[TM_LGS]); 324 } 325 if (nvp.w0 & NVP2_W0_T) { 326 nvp.w2 = xive_set_field32(NVP2_W2_T, nvp.w2, regs[TM_T]); 327 } 328 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 329 330 nvp.w1 = xive_set_field32(NVP2_W1_CO, nvp.w1, 0); 331 /* NVP2_W1_CO_THRID_VALID only set once */ 332 nvp.w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp.w1, 0xFFFF); 333 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 1); 334 } 335 336 static void xive2_cam_decode(uint32_t cam, uint8_t *nvp_blk, 337 uint32_t *nvp_idx, bool *valid, bool *hw) 338 { 339 *nvp_blk = xive2_nvp_blk(cam); 340 *nvp_idx = xive2_nvp_idx(cam); 341 *valid = !!(cam & TM2_W2_VALID); 342 *hw = !!(cam & TM2_W2_HW); 343 } 344 345 /* 346 * Encode the HW CAM line with 7bit or 8bit thread id. The thread id 347 * width and block id width is configurable at the IC level. 348 * 349 * chipid << 24 | 0000 0000 0000 0000 1 threadid (7Bit) 350 * chipid << 24 | 0000 0000 0000 0001 threadid (8Bit) 351 */ 352 static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 353 { 354 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 355 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 356 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 357 uint8_t blk = xive2_router_get_block_id(xrtr); 358 uint8_t tid_shift = 359 xive2_router_get_config(xrtr) & XIVE2_THREADID_8BITS ? 8 : 7; 360 uint8_t tid_mask = (1 << tid_shift) - 1; 361 362 return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask)); 363 } 364 365 static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr, XiveTCTX *tctx, 366 hwaddr offset, unsigned size, uint8_t ring) 367 { 368 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 369 uint32_t target_ringw2 = xive_tctx_word2(&tctx->regs[ring]); 370 uint32_t cam = be32_to_cpu(target_ringw2); 371 uint8_t nvp_blk; 372 uint32_t nvp_idx; 373 uint8_t cur_ring; 374 bool valid; 375 bool do_save; 376 377 xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &valid, &do_save); 378 379 if (!valid) { 380 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?\n", 381 nvp_blk, nvp_idx); 382 } 383 384 /* Invalidate CAM line of requested ring and all lower rings */ 385 for (cur_ring = TM_QW0_USER; cur_ring <= ring; 386 cur_ring += XIVE_TM_RING_SIZE) { 387 uint32_t ringw2 = xive_tctx_word2(&tctx->regs[cur_ring]); 388 uint32_t ringw2_new = xive_set_field32(TM2_QW1W2_VO, ringw2, 0); 389 memcpy(&tctx->regs[cur_ring + TM_WORD2], &ringw2_new, 4); 390 } 391 392 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) { 393 xive2_tctx_save_ctx(xrtr, tctx, nvp_blk, nvp_idx, ring); 394 } 395 396 /* 397 * Lower external interrupt line of requested ring and below except for 398 * USER, which doesn't exist. 399 */ 400 for (cur_ring = TM_QW1_OS; cur_ring <= ring; 401 cur_ring += XIVE_TM_RING_SIZE) { 402 xive_tctx_reset_signal(tctx, cur_ring); 403 } 404 return target_ringw2; 405 } 406 407 uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 408 hwaddr offset, unsigned size) 409 { 410 return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW1_OS); 411 } 412 413 #define REPORT_LINE_GEN1_SIZE 16 414 415 static void xive2_tm_report_line_gen1(XiveTCTX *tctx, uint8_t *data, 416 uint8_t size) 417 { 418 uint8_t *regs = tctx->regs; 419 420 g_assert(size == REPORT_LINE_GEN1_SIZE); 421 memset(data, 0, size); 422 /* 423 * See xive architecture for description of what is saved. It is 424 * hand-picked information to fit in 16 bytes. 425 */ 426 data[0x0] = regs[TM_QW3_HV_PHYS + TM_NSR]; 427 data[0x1] = regs[TM_QW3_HV_PHYS + TM_CPPR]; 428 data[0x2] = regs[TM_QW3_HV_PHYS + TM_IPB]; 429 data[0x3] = regs[TM_QW2_HV_POOL + TM_IPB]; 430 data[0x4] = regs[TM_QW1_OS + TM_ACK_CNT]; 431 data[0x5] = regs[TM_QW3_HV_PHYS + TM_LGS]; 432 data[0x6] = 0xFF; 433 data[0x7] = regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x80; 434 data[0x7] |= (regs[TM_QW2_HV_POOL + TM_WORD2] & 0x80) >> 1; 435 data[0x7] |= (regs[TM_QW1_OS + TM_WORD2] & 0x80) >> 2; 436 data[0x7] |= (regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x3); 437 data[0x8] = regs[TM_QW1_OS + TM_NSR]; 438 data[0x9] = regs[TM_QW1_OS + TM_CPPR]; 439 data[0xA] = regs[TM_QW1_OS + TM_IPB]; 440 data[0xB] = regs[TM_QW1_OS + TM_LGS]; 441 if (regs[TM_QW0_USER + TM_WORD2] & 0x80) { 442 /* 443 * Logical server extension, except VU bit replaced by EB bit 444 * from NSR 445 */ 446 data[0xC] = regs[TM_QW0_USER + TM_WORD2]; 447 data[0xC] &= ~0x80; 448 data[0xC] |= regs[TM_QW0_USER + TM_NSR] & 0x80; 449 data[0xD] = regs[TM_QW0_USER + TM_WORD2 + 1]; 450 data[0xE] = regs[TM_QW0_USER + TM_WORD2 + 2]; 451 data[0xF] = regs[TM_QW0_USER + TM_WORD2 + 3]; 452 } 453 } 454 455 static void xive2_tm_pull_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 456 hwaddr offset, uint64_t value, 457 unsigned size, uint8_t ring) 458 { 459 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 460 uint32_t hw_cam, nvp_idx, xive2_cfg, reserved; 461 uint8_t nvp_blk; 462 Xive2Nvp nvp; 463 uint64_t phys_addr; 464 MemTxResult result; 465 466 hw_cam = xive2_tctx_hw_cam_line(xptr, tctx); 467 nvp_blk = xive2_nvp_blk(hw_cam); 468 nvp_idx = xive2_nvp_idx(hw_cam); 469 470 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 471 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 472 nvp_blk, nvp_idx); 473 return; 474 } 475 476 if (!xive2_nvp_is_valid(&nvp)) { 477 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 478 nvp_blk, nvp_idx); 479 return; 480 } 481 482 xive2_cfg = xive2_router_get_config(xrtr); 483 484 phys_addr = xive2_nvp_reporting_addr(&nvp) + 0x80; /* odd line */ 485 if (xive2_cfg & XIVE2_GEN1_TIMA_OS) { 486 uint8_t pull_ctxt[REPORT_LINE_GEN1_SIZE]; 487 488 xive2_tm_report_line_gen1(tctx, pull_ctxt, REPORT_LINE_GEN1_SIZE); 489 result = dma_memory_write(&address_space_memory, phys_addr, 490 pull_ctxt, REPORT_LINE_GEN1_SIZE, 491 MEMTXATTRS_UNSPECIFIED); 492 assert(result == MEMTX_OK); 493 } else { 494 result = dma_memory_write(&address_space_memory, phys_addr, 495 &tctx->regs, sizeof(tctx->regs), 496 MEMTXATTRS_UNSPECIFIED); 497 assert(result == MEMTX_OK); 498 reserved = 0xFFFFFFFF; 499 result = dma_memory_write(&address_space_memory, phys_addr + 12, 500 &reserved, sizeof(reserved), 501 MEMTXATTRS_UNSPECIFIED); 502 assert(result == MEMTX_OK); 503 } 504 505 /* the rest is similar to pull context to registers */ 506 xive2_tm_pull_ctx(xptr, tctx, offset, size, ring); 507 } 508 509 void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 510 hwaddr offset, uint64_t value, unsigned size) 511 { 512 xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW1_OS); 513 } 514 515 516 void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 517 hwaddr offset, uint64_t value, unsigned size) 518 { 519 xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW3_HV_PHYS); 520 } 521 522 static uint8_t xive2_tctx_restore_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx, 523 uint8_t nvp_blk, uint32_t nvp_idx, 524 Xive2Nvp *nvp) 525 { 526 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 527 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 528 uint8_t cppr; 529 530 if (!xive2_nvp_is_hw(nvp)) { 531 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n", 532 nvp_blk, nvp_idx); 533 return 0; 534 } 535 536 cppr = xive_get_field32(NVP2_W2_CPPR, nvp->w2); 537 nvp->w2 = xive_set_field32(NVP2_W2_CPPR, nvp->w2, 0); 538 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 2); 539 540 tctx->regs[TM_QW1_OS + TM_CPPR] = cppr; 541 tctx->regs[TM_QW1_OS + TM_LSMFB] = xive_get_field32(NVP2_W2_LSMFB, nvp->w2); 542 tctx->regs[TM_QW1_OS + TM_LGS] = xive_get_field32(NVP2_W2_LGS, nvp->w2); 543 tctx->regs[TM_QW1_OS + TM_T] = xive_get_field32(NVP2_W2_T, nvp->w2); 544 545 nvp->w1 = xive_set_field32(NVP2_W1_CO, nvp->w1, 1); 546 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID_VALID, nvp->w1, 1); 547 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp->w1, pir); 548 549 /* 550 * Checkout privilege: 0:OS, 1:Pool, 2:Hard 551 * 552 * TODO: we only support OS push/pull 553 */ 554 nvp->w1 = xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 0); 555 556 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 1); 557 558 /* return restored CPPR to generate a CPU exception if needed */ 559 return cppr; 560 } 561 562 static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx, 563 uint8_t nvp_blk, uint32_t nvp_idx, 564 bool do_restore) 565 { 566 uint8_t ipb; 567 uint8_t backlog_level; 568 uint8_t backlog_prio; 569 uint8_t *regs = &tctx->regs[TM_QW1_OS]; 570 Xive2Nvp nvp; 571 572 /* 573 * Grab the associated thread interrupt context registers in the 574 * associated NVP 575 */ 576 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 577 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 578 nvp_blk, nvp_idx); 579 return; 580 } 581 582 if (!xive2_nvp_is_valid(&nvp)) { 583 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 584 nvp_blk, nvp_idx); 585 return; 586 } 587 588 /* Automatically restore thread context registers */ 589 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && 590 do_restore) { 591 xive2_tctx_restore_os_ctx(xrtr, tctx, nvp_blk, nvp_idx, &nvp); 592 } 593 594 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2); 595 if (ipb) { 596 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, 0); 597 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 598 } 599 regs[TM_IPB] |= ipb; 600 backlog_prio = xive_ipb_to_pipr(ipb); 601 backlog_level = 0; 602 603 /* 604 * Compute the PIPR based on the restored state. 605 * It will raise the External interrupt signal if needed. 606 */ 607 xive_tctx_pipr_update(tctx, TM_QW1_OS, backlog_prio, backlog_level); 608 } 609 610 /* 611 * Updating the OS CAM line can trigger a resend of interrupt 612 */ 613 void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 614 hwaddr offset, uint64_t value, unsigned size) 615 { 616 uint32_t cam; 617 uint32_t qw1w2; 618 uint64_t qw1dw1; 619 uint8_t nvp_blk; 620 uint32_t nvp_idx; 621 bool vo; 622 bool do_restore; 623 624 /* First update the thead context */ 625 switch (size) { 626 case 4: 627 cam = value; 628 qw1w2 = cpu_to_be32(cam); 629 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 630 break; 631 case 8: 632 cam = value >> 32; 633 qw1dw1 = cpu_to_be64(value); 634 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1dw1, 8); 635 break; 636 default: 637 g_assert_not_reached(); 638 } 639 640 xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore); 641 642 /* Check the interrupt pending bits */ 643 if (vo) { 644 xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, nvp_blk, nvp_idx, 645 do_restore); 646 } 647 } 648 649 static void xive2_tctx_set_target(XiveTCTX *tctx, uint8_t ring, uint8_t target) 650 { 651 uint8_t *regs = &tctx->regs[ring]; 652 653 regs[TM_T] = target; 654 } 655 656 void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx, 657 hwaddr offset, uint64_t value, unsigned size) 658 { 659 xive2_tctx_set_target(tctx, TM_QW3_HV_PHYS, value & 0xff); 660 } 661 662 /* 663 * XIVE Router (aka. Virtualization Controller or IVRE) 664 */ 665 666 int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 667 Xive2Eas *eas) 668 { 669 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 670 671 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 672 } 673 674 static 675 int xive2_router_get_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 676 uint8_t *pq) 677 { 678 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 679 680 return xrc->get_pq(xrtr, eas_blk, eas_idx, pq); 681 } 682 683 static 684 int xive2_router_set_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 685 uint8_t *pq) 686 { 687 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 688 689 return xrc->set_pq(xrtr, eas_blk, eas_idx, pq); 690 } 691 692 int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 693 Xive2End *end) 694 { 695 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 696 697 return xrc->get_end(xrtr, end_blk, end_idx, end); 698 } 699 700 int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 701 Xive2End *end, uint8_t word_number) 702 { 703 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 704 705 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 706 } 707 708 int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 709 Xive2Nvp *nvp) 710 { 711 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 712 713 return xrc->get_nvp(xrtr, nvp_blk, nvp_idx, nvp); 714 } 715 716 int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 717 Xive2Nvp *nvp, uint8_t word_number) 718 { 719 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 720 721 return xrc->write_nvp(xrtr, nvp_blk, nvp_idx, nvp, word_number); 722 } 723 724 int xive2_router_get_nvgc(Xive2Router *xrtr, bool crowd, 725 uint8_t nvgc_blk, uint32_t nvgc_idx, 726 Xive2Nvgc *nvgc) 727 { 728 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 729 730 return xrc->get_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc); 731 } 732 733 int xive2_router_write_nvgc(Xive2Router *xrtr, bool crowd, 734 uint8_t nvgc_blk, uint32_t nvgc_idx, 735 Xive2Nvgc *nvgc) 736 { 737 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 738 739 return xrc->write_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc); 740 } 741 742 static bool xive2_vp_match_mask(uint32_t cam1, uint32_t cam2, 743 uint32_t vp_mask) 744 { 745 return (cam1 & vp_mask) == (cam2 & vp_mask); 746 } 747 748 /* 749 * The thread context register words are in big-endian format. 750 */ 751 int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 752 uint8_t format, 753 uint8_t nvt_blk, uint32_t nvt_idx, 754 bool cam_ignore, uint32_t logic_serv) 755 { 756 uint32_t cam = xive2_nvp_cam_line(nvt_blk, nvt_idx); 757 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 758 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 759 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 760 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 761 762 uint32_t vp_mask = 0xFFFFFFFF; 763 764 if (format == 0) { 765 /* 766 * i=0: Specific NVT notification 767 * i=1: VP-group notification (bits ignored at the end of the 768 * NVT identifier) 769 */ 770 if (cam_ignore) { 771 vp_mask = ~(xive_get_vpgroup_size(nvt_idx) - 1); 772 } 773 774 /* For VP-group notifications, threads with LGS=0 are excluded */ 775 776 /* PHYS ring */ 777 if ((be32_to_cpu(qw3w2) & TM2_QW3W2_VT) && 778 !(cam_ignore && tctx->regs[TM_QW3_HV_PHYS + TM_LGS] == 0) && 779 xive2_vp_match_mask(cam, 780 xive2_tctx_hw_cam_line(xptr, tctx), 781 vp_mask)) { 782 return TM_QW3_HV_PHYS; 783 } 784 785 /* HV POOL ring */ 786 if ((be32_to_cpu(qw2w2) & TM2_QW2W2_VP) && 787 !(cam_ignore && tctx->regs[TM_QW2_HV_POOL + TM_LGS] == 0) && 788 xive2_vp_match_mask(cam, 789 xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2), 790 vp_mask)) { 791 return TM_QW2_HV_POOL; 792 } 793 794 /* OS ring */ 795 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 796 !(cam_ignore && tctx->regs[TM_QW1_OS + TM_LGS] == 0) && 797 xive2_vp_match_mask(cam, 798 xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2), 799 vp_mask)) { 800 return TM_QW1_OS; 801 } 802 } else { 803 /* F=1 : User level Event-Based Branch (EBB) notification */ 804 805 /* FIXME: what if cam_ignore and LGS = 0 ? */ 806 /* USER ring */ 807 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 808 (cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) && 809 (be32_to_cpu(qw0w2) & TM2_QW0W2_VU) && 810 (logic_serv == xive_get_field32(TM2_QW0W2_LOGIC_SERV, qw0w2))) { 811 return TM_QW0_USER; 812 } 813 } 814 return -1; 815 } 816 817 bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, uint8_t priority) 818 { 819 uint8_t *regs = &tctx->regs[ring]; 820 821 /* 822 * The xive2_presenter_tctx_match() above tells if there's a match 823 * but for VP-group notification, we still need to look at the 824 * priority to know if the thread can take the interrupt now or if 825 * it is precluded. 826 */ 827 if (priority < regs[TM_CPPR]) { 828 return false; 829 } 830 return true; 831 } 832 833 static void xive2_router_realize(DeviceState *dev, Error **errp) 834 { 835 Xive2Router *xrtr = XIVE2_ROUTER(dev); 836 837 assert(xrtr->xfb); 838 } 839 840 /* 841 * Notification using the END ESe/ESn bit (Event State Buffer for 842 * escalation and notification). Profide further coalescing in the 843 * Router. 844 */ 845 static bool xive2_router_end_es_notify(Xive2Router *xrtr, uint8_t end_blk, 846 uint32_t end_idx, Xive2End *end, 847 uint32_t end_esmask) 848 { 849 uint8_t pq = xive_get_field32(end_esmask, end->w1); 850 bool notify = xive_esb_trigger(&pq); 851 852 if (pq != xive_get_field32(end_esmask, end->w1)) { 853 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 854 xive2_router_write_end(xrtr, end_blk, end_idx, end, 1); 855 } 856 857 /* ESe/n[Q]=1 : end of notification */ 858 return notify; 859 } 860 861 /* 862 * An END trigger can come from an event trigger (IPI or HW) or from 863 * another chip. We don't model the PowerBus but the END trigger 864 * message has the same parameters than in the function below. 865 */ 866 static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk, 867 uint32_t end_idx, uint32_t end_data) 868 { 869 Xive2End end; 870 uint8_t priority; 871 uint8_t format; 872 bool found, precluded; 873 Xive2Nvp nvp; 874 uint8_t nvp_blk; 875 uint32_t nvp_idx; 876 877 /* END cache lookup */ 878 if (xive2_router_get_end(xrtr, end_blk, end_idx, &end)) { 879 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 880 end_idx); 881 return; 882 } 883 884 if (!xive2_end_is_valid(&end)) { 885 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 886 end_blk, end_idx); 887 return; 888 } 889 890 if (xive2_end_is_enqueue(&end)) { 891 xive2_end_enqueue(&end, end_data); 892 /* Enqueuing event data modifies the EQ toggle and index */ 893 xive2_router_write_end(xrtr, end_blk, end_idx, &end, 1); 894 } 895 896 /* 897 * When the END is silent, we skip the notification part. 898 */ 899 if (xive2_end_is_silent_escalation(&end)) { 900 goto do_escalation; 901 } 902 903 /* 904 * The W7 format depends on the F bit in W6. It defines the type 905 * of the notification : 906 * 907 * F=0 : single or multiple NVP notification 908 * F=1 : User level Event-Based Branch (EBB) notification, no 909 * priority 910 */ 911 format = xive_get_field32(END2_W6_FORMAT_BIT, end.w6); 912 priority = xive_get_field32(END2_W7_F0_PRIORITY, end.w7); 913 914 /* The END is masked */ 915 if (format == 0 && priority == 0xff) { 916 return; 917 } 918 919 /* 920 * Check the END ESn (Event State Buffer for notification) for 921 * even further coalescing in the Router 922 */ 923 if (!xive2_end_is_notify(&end)) { 924 /* ESn[Q]=1 : end of notification */ 925 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 926 &end, END2_W1_ESn)) { 927 return; 928 } 929 } 930 931 /* 932 * Follows IVPE notification 933 */ 934 nvp_blk = xive_get_field32(END2_W6_VP_BLOCK, end.w6); 935 nvp_idx = xive_get_field32(END2_W6_VP_OFFSET, end.w6); 936 937 /* NVP cache lookup */ 938 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 939 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVP %x/%x\n", 940 nvp_blk, nvp_idx); 941 return; 942 } 943 944 if (!xive2_nvp_is_valid(&nvp)) { 945 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is invalid\n", 946 nvp_blk, nvp_idx); 947 return; 948 } 949 950 found = xive_presenter_notify(xrtr->xfb, format, nvp_blk, nvp_idx, 951 xive2_end_is_ignore(&end), 952 priority, 953 xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w7), 954 &precluded); 955 956 /* TODO: Auto EOI. */ 957 958 if (found) { 959 return; 960 } 961 962 /* 963 * If no matching NVP is dispatched on a HW thread : 964 * - specific VP: update the NVP structure if backlog is activated 965 * - logical server : forward request to IVPE (not supported) 966 */ 967 if (xive2_end_is_backlog(&end)) { 968 uint8_t ipb; 969 970 if (format == 1) { 971 qemu_log_mask(LOG_GUEST_ERROR, 972 "XIVE: END %x/%x invalid config: F1 & backlog\n", 973 end_blk, end_idx); 974 return; 975 } 976 977 /* 978 * Record the IPB in the associated NVP structure for later 979 * use. The presenter will resend the interrupt when the vCPU 980 * is dispatched again on a HW thread. 981 */ 982 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2) | 983 xive_priority_to_ipb(priority); 984 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb); 985 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 986 987 /* 988 * On HW, follows a "Broadcast Backlog" to IVPEs 989 */ 990 } 991 992 do_escalation: 993 /* 994 * If activated, escalate notification using the ESe PQ bits and 995 * the EAS in w4-5 996 */ 997 if (!xive2_end_is_escalate(&end)) { 998 return; 999 } 1000 1001 /* 1002 * Check the END ESe (Event State Buffer for escalation) for even 1003 * further coalescing in the Router 1004 */ 1005 if (!xive2_end_is_uncond_escalation(&end)) { 1006 /* ESe[Q]=1 : end of escalation notification */ 1007 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 1008 &end, END2_W1_ESe)) { 1009 return; 1010 } 1011 } 1012 1013 /* 1014 * The END trigger becomes an Escalation trigger 1015 */ 1016 xive2_router_end_notify(xrtr, 1017 xive_get_field32(END2_W4_END_BLOCK, end.w4), 1018 xive_get_field32(END2_W4_ESC_END_INDEX, end.w4), 1019 xive_get_field32(END2_W5_ESC_END_DATA, end.w5)); 1020 } 1021 1022 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) 1023 { 1024 Xive2Router *xrtr = XIVE2_ROUTER(xn); 1025 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1026 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1027 Xive2Eas eas; 1028 1029 /* EAS cache lookup */ 1030 if (xive2_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1031 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1032 return; 1033 } 1034 1035 if (!pq_checked) { 1036 bool notify; 1037 uint8_t pq; 1038 1039 /* PQ cache lookup */ 1040 if (xive2_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) { 1041 /* Set FIR */ 1042 g_assert_not_reached(); 1043 } 1044 1045 notify = xive_esb_trigger(&pq); 1046 1047 if (xive2_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) { 1048 /* Set FIR */ 1049 g_assert_not_reached(); 1050 } 1051 1052 if (!notify) { 1053 return; 1054 } 1055 } 1056 1057 if (!xive2_eas_is_valid(&eas)) { 1058 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %x\n", lisn); 1059 return; 1060 } 1061 1062 if (xive2_eas_is_masked(&eas)) { 1063 /* Notification completed */ 1064 return; 1065 } 1066 1067 /* 1068 * The event trigger becomes an END trigger 1069 */ 1070 xive2_router_end_notify(xrtr, 1071 xive_get_field64(EAS2_END_BLOCK, eas.w), 1072 xive_get_field64(EAS2_END_INDEX, eas.w), 1073 xive_get_field64(EAS2_END_DATA, eas.w)); 1074 } 1075 1076 static const Property xive2_router_properties[] = { 1077 DEFINE_PROP_LINK("xive-fabric", Xive2Router, xfb, 1078 TYPE_XIVE_FABRIC, XiveFabric *), 1079 }; 1080 1081 static void xive2_router_class_init(ObjectClass *klass, void *data) 1082 { 1083 DeviceClass *dc = DEVICE_CLASS(klass); 1084 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1085 1086 dc->desc = "XIVE2 Router Engine"; 1087 device_class_set_props(dc, xive2_router_properties); 1088 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 1089 dc->realize = xive2_router_realize; 1090 xnc->notify = xive2_router_notify; 1091 } 1092 1093 static const TypeInfo xive2_router_info = { 1094 .name = TYPE_XIVE2_ROUTER, 1095 .parent = TYPE_SYS_BUS_DEVICE, 1096 .abstract = true, 1097 .instance_size = sizeof(Xive2Router), 1098 .class_size = sizeof(Xive2RouterClass), 1099 .class_init = xive2_router_class_init, 1100 .interfaces = (InterfaceInfo[]) { 1101 { TYPE_XIVE_NOTIFIER }, 1102 { TYPE_XIVE_PRESENTER }, 1103 { } 1104 } 1105 }; 1106 1107 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 1108 { 1109 return !((addr >> shift) & 1); 1110 } 1111 1112 static uint64_t xive2_end_source_read(void *opaque, hwaddr addr, unsigned size) 1113 { 1114 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 1115 uint32_t offset = addr & 0xFFF; 1116 uint8_t end_blk; 1117 uint32_t end_idx; 1118 Xive2End end; 1119 uint32_t end_esmask; 1120 uint8_t pq; 1121 uint64_t ret; 1122 1123 /* 1124 * The block id should be deduced from the load address on the END 1125 * ESB MMIO but our model only supports a single block per XIVE chip. 1126 */ 1127 end_blk = xive2_router_get_block_id(xsrc->xrtr); 1128 end_idx = addr >> (xsrc->esb_shift + 1); 1129 1130 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1131 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1132 end_idx); 1133 return -1; 1134 } 1135 1136 if (!xive2_end_is_valid(&end)) { 1137 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1138 end_blk, end_idx); 1139 return -1; 1140 } 1141 1142 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 1143 END2_W1_ESe; 1144 pq = xive_get_field32(end_esmask, end.w1); 1145 1146 switch (offset) { 1147 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1148 ret = xive_esb_eoi(&pq); 1149 1150 /* Forward the source event notification for routing ?? */ 1151 break; 1152 1153 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1154 ret = pq; 1155 break; 1156 1157 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1158 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1159 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1160 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1161 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1162 break; 1163 default: 1164 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1165 offset); 1166 return -1; 1167 } 1168 1169 if (pq != xive_get_field32(end_esmask, end.w1)) { 1170 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1171 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1172 } 1173 1174 return ret; 1175 } 1176 1177 static void xive2_end_source_write(void *opaque, hwaddr addr, 1178 uint64_t value, unsigned size) 1179 { 1180 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 1181 uint32_t offset = addr & 0xFFF; 1182 uint8_t end_blk; 1183 uint32_t end_idx; 1184 Xive2End end; 1185 uint32_t end_esmask; 1186 uint8_t pq; 1187 bool notify = false; 1188 1189 /* 1190 * The block id should be deduced from the load address on the END 1191 * ESB MMIO but our model only supports a single block per XIVE chip. 1192 */ 1193 end_blk = xive2_router_get_block_id(xsrc->xrtr); 1194 end_idx = addr >> (xsrc->esb_shift + 1); 1195 1196 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1197 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1198 end_idx); 1199 return; 1200 } 1201 1202 if (!xive2_end_is_valid(&end)) { 1203 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1204 end_blk, end_idx); 1205 return; 1206 } 1207 1208 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 1209 END2_W1_ESe; 1210 pq = xive_get_field32(end_esmask, end.w1); 1211 1212 switch (offset) { 1213 case 0 ... 0x3FF: 1214 notify = xive_esb_trigger(&pq); 1215 break; 1216 1217 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 1218 /* TODO: can we check StoreEOI availability from the router ? */ 1219 notify = xive_esb_eoi(&pq); 1220 break; 1221 1222 case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF: 1223 if (end_esmask == END2_W1_ESe) { 1224 qemu_log_mask(LOG_GUEST_ERROR, 1225 "XIVE: END %x/%x can not EQ inject on ESe\n", 1226 end_blk, end_idx); 1227 return; 1228 } 1229 notify = true; 1230 break; 1231 1232 default: 1233 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB write addr %d\n", 1234 offset); 1235 return; 1236 } 1237 1238 if (pq != xive_get_field32(end_esmask, end.w1)) { 1239 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1240 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1241 } 1242 1243 /* TODO: Forward the source event notification for routing */ 1244 if (notify) { 1245 ; 1246 } 1247 } 1248 1249 static const MemoryRegionOps xive2_end_source_ops = { 1250 .read = xive2_end_source_read, 1251 .write = xive2_end_source_write, 1252 .endianness = DEVICE_BIG_ENDIAN, 1253 .valid = { 1254 .min_access_size = 1, 1255 .max_access_size = 8, 1256 }, 1257 .impl = { 1258 .min_access_size = 1, 1259 .max_access_size = 8, 1260 }, 1261 }; 1262 1263 static void xive2_end_source_realize(DeviceState *dev, Error **errp) 1264 { 1265 Xive2EndSource *xsrc = XIVE2_END_SOURCE(dev); 1266 1267 assert(xsrc->xrtr); 1268 1269 if (!xsrc->nr_ends) { 1270 error_setg(errp, "Number of interrupt needs to be greater than 0"); 1271 return; 1272 } 1273 1274 if (xsrc->esb_shift != XIVE_ESB_4K && 1275 xsrc->esb_shift != XIVE_ESB_64K) { 1276 error_setg(errp, "Invalid ESB shift setting"); 1277 return; 1278 } 1279 1280 /* 1281 * Each END is assigned an even/odd pair of MMIO pages, the even page 1282 * manages the ESn field while the odd page manages the ESe field. 1283 */ 1284 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 1285 &xive2_end_source_ops, xsrc, "xive.end", 1286 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 1287 } 1288 1289 static const Property xive2_end_source_properties[] = { 1290 DEFINE_PROP_UINT32("nr-ends", Xive2EndSource, nr_ends, 0), 1291 DEFINE_PROP_UINT32("shift", Xive2EndSource, esb_shift, XIVE_ESB_64K), 1292 DEFINE_PROP_LINK("xive", Xive2EndSource, xrtr, TYPE_XIVE2_ROUTER, 1293 Xive2Router *), 1294 }; 1295 1296 static void xive2_end_source_class_init(ObjectClass *klass, void *data) 1297 { 1298 DeviceClass *dc = DEVICE_CLASS(klass); 1299 1300 dc->desc = "XIVE END Source"; 1301 device_class_set_props(dc, xive2_end_source_properties); 1302 dc->realize = xive2_end_source_realize; 1303 dc->user_creatable = false; 1304 } 1305 1306 static const TypeInfo xive2_end_source_info = { 1307 .name = TYPE_XIVE2_END_SOURCE, 1308 .parent = TYPE_DEVICE, 1309 .instance_size = sizeof(Xive2EndSource), 1310 .class_init = xive2_end_source_class_init, 1311 }; 1312 1313 static void xive2_register_types(void) 1314 { 1315 type_register_static(&xive2_router_info); 1316 type_register_static(&xive2_end_source_info); 1317 } 1318 1319 type_init(xive2_register_types) 1320