1 /* 2 * QEMU PowerPC XIVE2 interrupt controller model (POWER10) 3 * 4 * Copyright (c) 2019-2024, IBM Corporation.. 5 * 6 * SPDX-License-Identifier: GPL-2.0-or-later 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/log.h" 11 #include "qemu/module.h" 12 #include "qapi/error.h" 13 #include "target/ppc/cpu.h" 14 #include "system/cpus.h" 15 #include "system/dma.h" 16 #include "hw/qdev-properties.h" 17 #include "hw/ppc/xive.h" 18 #include "hw/ppc/xive2.h" 19 #include "hw/ppc/xive2_regs.h" 20 #include "trace.h" 21 22 static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk, 23 uint32_t end_idx, uint32_t end_data, 24 bool redistribute); 25 26 uint32_t xive2_router_get_config(Xive2Router *xrtr) 27 { 28 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 29 30 return xrc->get_config(xrtr); 31 } 32 33 static int xive2_router_get_block_id(Xive2Router *xrtr) 34 { 35 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 36 37 return xrc->get_block_id(xrtr); 38 } 39 40 static uint64_t xive2_nvp_reporting_addr(Xive2Nvp *nvp) 41 { 42 uint64_t cache_addr; 43 44 cache_addr = xive_get_field32(NVP2_W6_REPORTING_LINE, nvp->w6) << 24 | 45 xive_get_field32(NVP2_W7_REPORTING_LINE, nvp->w7); 46 cache_addr <<= 8; /* aligned on a cache line pair */ 47 return cache_addr; 48 } 49 50 static uint32_t xive2_nvgc_get_backlog(Xive2Nvgc *nvgc, uint8_t priority) 51 { 52 uint32_t val = 0; 53 uint8_t *ptr, i; 54 55 if (priority > 7) { 56 return 0; 57 } 58 59 /* 60 * The per-priority backlog counters are 24-bit and the structure 61 * is stored in big endian. NVGC is 32-bytes long, so 24-bytes from 62 * w2, which fits 8 priorities * 24-bits per priority. 63 */ 64 ptr = (uint8_t *)&nvgc->w2 + priority * 3; 65 for (i = 0; i < 3; i++, ptr++) { 66 val = (val << 8) + *ptr; 67 } 68 return val; 69 } 70 71 static void xive2_nvgc_set_backlog(Xive2Nvgc *nvgc, uint8_t priority, 72 uint32_t val) 73 { 74 uint8_t *ptr, i; 75 uint32_t shift; 76 77 if (priority > 7) { 78 return; 79 } 80 81 if (val > 0xFFFFFF) { 82 val = 0xFFFFFF; 83 } 84 /* 85 * The per-priority backlog counters are 24-bit and the structure 86 * is stored in big endian 87 */ 88 ptr = (uint8_t *)&nvgc->w2 + priority * 3; 89 for (i = 0; i < 3; i++, ptr++) { 90 shift = 8 * (2 - i); 91 *ptr = (val >> shift) & 0xFF; 92 } 93 } 94 95 uint64_t xive2_presenter_nvgc_backlog_op(XivePresenter *xptr, 96 bool crowd, 97 uint8_t blk, uint32_t idx, 98 uint16_t offset, uint16_t val) 99 { 100 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 101 uint8_t priority = GETFIELD(NVx_BACKLOG_PRIO, offset); 102 uint8_t op = GETFIELD(NVx_BACKLOG_OP, offset); 103 Xive2Nvgc nvgc; 104 uint32_t count, old_count; 105 106 if (xive2_router_get_nvgc(xrtr, crowd, blk, idx, &nvgc)) { 107 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No %s %x/%x\n", 108 crowd ? "NVC" : "NVG", blk, idx); 109 return -1; 110 } 111 if (!xive2_nvgc_is_valid(&nvgc)) { 112 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVG %x/%x\n", blk, idx); 113 return -1; 114 } 115 116 old_count = xive2_nvgc_get_backlog(&nvgc, priority); 117 count = old_count; 118 /* 119 * op: 120 * 0b00 => increment 121 * 0b01 => decrement 122 * 0b1- => read 123 */ 124 if (op == 0b00 || op == 0b01) { 125 if (op == 0b00) { 126 count += val; 127 } else { 128 if (count > val) { 129 count -= val; 130 } else { 131 count = 0; 132 } 133 } 134 xive2_nvgc_set_backlog(&nvgc, priority, count); 135 xive2_router_write_nvgc(xrtr, crowd, blk, idx, &nvgc); 136 } 137 trace_xive_nvgc_backlog_op(crowd, blk, idx, op, priority, old_count); 138 return old_count; 139 } 140 141 uint64_t xive2_presenter_nvp_backlog_op(XivePresenter *xptr, 142 uint8_t blk, uint32_t idx, 143 uint16_t offset) 144 { 145 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 146 uint8_t priority = GETFIELD(NVx_BACKLOG_PRIO, offset); 147 uint8_t op = GETFIELD(NVx_BACKLOG_OP, offset); 148 Xive2Nvp nvp; 149 uint8_t ipb, old_ipb, rc; 150 151 if (xive2_router_get_nvp(xrtr, blk, idx, &nvp)) { 152 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", blk, idx); 153 return -1; 154 } 155 if (!xive2_nvp_is_valid(&nvp)) { 156 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVP %x/%x\n", blk, idx); 157 return -1; 158 } 159 160 old_ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2); 161 ipb = old_ipb; 162 /* 163 * op: 164 * 0b00 => set priority bit 165 * 0b01 => reset priority bit 166 * 0b1- => read 167 */ 168 if (op == 0b00 || op == 0b01) { 169 if (op == 0b00) { 170 ipb |= xive_priority_to_ipb(priority); 171 } else { 172 ipb &= ~xive_priority_to_ipb(priority); 173 } 174 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb); 175 xive2_router_write_nvp(xrtr, blk, idx, &nvp, 2); 176 } 177 rc = !!(old_ipb & xive_priority_to_ipb(priority)); 178 trace_xive_nvp_backlog_op(blk, idx, op, priority, rc); 179 return rc; 180 } 181 182 void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf) 183 { 184 if (!xive2_eas_is_valid(eas)) { 185 return; 186 } 187 188 g_string_append_printf(buf, " %08x %s end:%02x/%04x data:%08x\n", 189 lisn, xive2_eas_is_masked(eas) ? "M" : " ", 190 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 191 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 192 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 193 } 194 195 #define XIVE2_QSIZE_CHUNK_CL 128 196 #define XIVE2_QSIZE_CHUNK_4k 4096 197 /* Calculate max number of queue entries for an END */ 198 static uint32_t xive2_end_get_qentries(Xive2End *end) 199 { 200 uint32_t w3 = end->w3; 201 uint32_t qsize = xive_get_field32(END2_W3_QSIZE, w3); 202 if (xive_get_field32(END2_W3_CL, w3)) { 203 g_assert(qsize <= 4); 204 return (XIVE2_QSIZE_CHUNK_CL << qsize) / sizeof(uint32_t); 205 } else { 206 g_assert(qsize <= 12); 207 return (XIVE2_QSIZE_CHUNK_4k << qsize) / sizeof(uint32_t); 208 } 209 } 210 211 void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, GString *buf) 212 { 213 uint64_t qaddr_base = xive2_end_qaddr(end); 214 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 215 uint32_t qentries = xive2_end_get_qentries(end); 216 int i; 217 218 /* 219 * print out the [ (qindex - (width - 1)) .. (qindex + 1)] window 220 */ 221 g_string_append_printf(buf, " [ "); 222 qindex = (qindex - (width - 1)) & (qentries - 1); 223 for (i = 0; i < width; i++) { 224 uint64_t qaddr = qaddr_base + (qindex << 2); 225 uint32_t qdata = -1; 226 227 if (dma_memory_read(&address_space_memory, qaddr, &qdata, 228 sizeof(qdata), MEMTXATTRS_UNSPECIFIED)) { 229 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to read EQ @0x%" 230 HWADDR_PRIx "\n", qaddr); 231 return; 232 } 233 g_string_append_printf(buf, "%s%08x ", i == width - 1 ? "^" : "", 234 be32_to_cpu(qdata)); 235 qindex = (qindex + 1) & (qentries - 1); 236 } 237 g_string_append_printf(buf, "]"); 238 } 239 240 void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, GString *buf) 241 { 242 uint64_t qaddr_base = xive2_end_qaddr(end); 243 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 244 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 245 uint32_t qentries = xive2_end_get_qentries(end); 246 247 uint32_t nvx_blk = xive_get_field32(END2_W6_VP_BLOCK, end->w6); 248 uint32_t nvx_idx = xive_get_field32(END2_W6_VP_OFFSET, end->w6); 249 uint8_t priority = xive_get_field32(END2_W7_F0_PRIORITY, end->w7); 250 uint8_t pq; 251 252 if (!xive2_end_is_valid(end)) { 253 return; 254 } 255 256 pq = xive_get_field32(END2_W1_ESn, end->w1); 257 258 g_string_append_printf(buf, 259 " %08x %c%c %c%c%c%c%c%c%c%c%c%c%c %c%c " 260 "prio:%d nvp:%02x/%04x", 261 end_idx, 262 pq & XIVE_ESB_VAL_P ? 'P' : '-', 263 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 264 xive2_end_is_valid(end) ? 'v' : '-', 265 xive2_end_is_enqueue(end) ? 'q' : '-', 266 xive2_end_is_notify(end) ? 'n' : '-', 267 xive2_end_is_backlog(end) ? 'b' : '-', 268 xive2_end_is_precluded_escalation(end) ? 'p' : '-', 269 xive2_end_is_escalate(end) ? 'e' : '-', 270 xive2_end_is_escalate_end(end) ? 'N' : '-', 271 xive2_end_is_uncond_escalation(end) ? 'u' : '-', 272 xive2_end_is_silent_escalation(end) ? 's' : '-', 273 xive2_end_is_firmware1(end) ? 'f' : '-', 274 xive2_end_is_firmware2(end) ? 'F' : '-', 275 xive2_end_is_ignore(end) ? 'i' : '-', 276 xive2_end_is_crowd(end) ? 'c' : '-', 277 priority, nvx_blk, nvx_idx); 278 279 if (qaddr_base) { 280 g_string_append_printf(buf, " eq:@%08"PRIx64"% 6d/%5d ^%d", 281 qaddr_base, qindex, qentries, qgen); 282 xive2_end_queue_pic_print_info(end, 6, buf); 283 } 284 g_string_append_c(buf, '\n'); 285 } 286 287 void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx, 288 GString *buf) 289 { 290 Xive2Eas *eas = (Xive2Eas *) &end->w4; 291 uint8_t pq; 292 293 if (!xive2_end_is_escalate(end)) { 294 return; 295 } 296 297 pq = xive_get_field32(END2_W1_ESe, end->w1); 298 299 g_string_append_printf(buf, " %08x %c%c %c%c end:%02x/%04x data:%08x\n", 300 end_idx, 301 pq & XIVE_ESB_VAL_P ? 'P' : '-', 302 pq & XIVE_ESB_VAL_Q ? 'Q' : '-', 303 xive2_eas_is_valid(eas) ? 'v' : ' ', 304 xive2_eas_is_masked(eas) ? 'M' : ' ', 305 (uint8_t) xive_get_field64(EAS2_END_BLOCK, eas->w), 306 (uint32_t) xive_get_field64(EAS2_END_INDEX, eas->w), 307 (uint32_t) xive_get_field64(EAS2_END_DATA, eas->w)); 308 } 309 310 void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, GString *buf) 311 { 312 uint8_t eq_blk = xive_get_field32(NVP2_W5_VP_END_BLOCK, nvp->w5); 313 uint32_t eq_idx = xive_get_field32(NVP2_W5_VP_END_INDEX, nvp->w5); 314 uint64_t cache_line = xive2_nvp_reporting_addr(nvp); 315 316 if (!xive2_nvp_is_valid(nvp)) { 317 return; 318 } 319 320 g_string_append_printf(buf, " %08x end:%02x/%04x IPB:%02x PGoFirst:%02x", 321 nvp_idx, eq_blk, eq_idx, 322 xive_get_field32(NVP2_W2_IPB, nvp->w2), 323 xive_get_field32(NVP2_W0_PGOFIRST, nvp->w0)); 324 if (cache_line) { 325 g_string_append_printf(buf, " reporting CL:%016"PRIx64, cache_line); 326 } 327 328 /* 329 * When the NVP is HW controlled, more fields are updated 330 */ 331 if (xive2_nvp_is_hw(nvp)) { 332 g_string_append_printf(buf, " CPPR:%02x", 333 xive_get_field32(NVP2_W2_CPPR, nvp->w2)); 334 if (xive2_nvp_is_co(nvp)) { 335 g_string_append_printf(buf, " CO:%04x", 336 xive_get_field32(NVP2_W1_CO_THRID, nvp->w1)); 337 } 338 } 339 g_string_append_c(buf, '\n'); 340 } 341 342 void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uint32_t nvgc_idx, GString *buf) 343 { 344 uint8_t i; 345 346 if (!xive2_nvgc_is_valid(nvgc)) { 347 return; 348 } 349 350 g_string_append_printf(buf, " %08x PGoNext:%02x bklog: ", nvgc_idx, 351 xive_get_field32(NVGC2_W0_PGONEXT, nvgc->w0)); 352 for (i = 0; i <= XIVE_PRIORITY_MAX; i++) { 353 g_string_append_printf(buf, "[%d]=0x%x ", 354 i, xive2_nvgc_get_backlog(nvgc, i)); 355 } 356 g_string_append_printf(buf, "\n"); 357 } 358 359 static void xive2_end_enqueue(Xive2End *end, uint32_t data) 360 { 361 uint64_t qaddr_base = xive2_end_qaddr(end); 362 uint32_t qindex = xive_get_field32(END2_W1_PAGE_OFF, end->w1); 363 uint32_t qgen = xive_get_field32(END2_W1_GENERATION, end->w1); 364 365 uint64_t qaddr = qaddr_base + (qindex << 2); 366 uint32_t qdata = cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); 367 uint32_t qentries = xive2_end_get_qentries(end); 368 369 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdata), 370 MEMTXATTRS_UNSPECIFIED)) { 371 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: failed to write END data @0x%" 372 HWADDR_PRIx "\n", qaddr); 373 return; 374 } 375 376 qindex = (qindex + 1) & (qentries - 1); 377 if (qindex == 0) { 378 qgen ^= 1; 379 end->w1 = xive_set_field32(END2_W1_GENERATION, end->w1, qgen); 380 381 /* Set gen flipped to 1, it gets reset on a cache watch operation */ 382 end->w1 = xive_set_field32(END2_W1_GEN_FLIPPED, end->w1, 1); 383 } 384 end->w1 = xive_set_field32(END2_W1_PAGE_OFF, end->w1, qindex); 385 } 386 387 static void xive2_pgofnext(uint8_t *nvgc_blk, uint32_t *nvgc_idx, 388 uint8_t next_level) 389 { 390 uint32_t mask, next_idx; 391 uint8_t next_blk; 392 393 /* 394 * Adjust the block and index of a VP for the next group/crowd 395 * size (PGofFirst/PGofNext field in the NVP and NVGC structures). 396 * 397 * The 6-bit group level is split into a 2-bit crowd and 4-bit 398 * group levels. Encoding is similar. However, we don't support 399 * crowd size of 8. So a crowd level of 0b11 is bumped to a crowd 400 * size of 16. 401 */ 402 next_blk = NVx_CROWD_LVL(next_level); 403 if (next_blk == 3) { 404 next_blk = 4; 405 } 406 mask = (1 << next_blk) - 1; 407 *nvgc_blk &= ~mask; 408 *nvgc_blk |= mask >> 1; 409 410 next_idx = NVx_GROUP_LVL(next_level); 411 mask = (1 << next_idx) - 1; 412 *nvgc_idx &= ~mask; 413 *nvgc_idx |= mask >> 1; 414 } 415 416 /* 417 * Scan the group chain and return the highest priority and group 418 * level of pending group interrupts. 419 */ 420 static uint8_t xive2_presenter_backlog_scan(XivePresenter *xptr, 421 uint8_t nvx_blk, uint32_t nvx_idx, 422 uint8_t first_group, 423 uint8_t *out_level) 424 { 425 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 426 uint32_t nvgc_idx; 427 uint32_t current_level, count; 428 uint8_t nvgc_blk, prio; 429 Xive2Nvgc nvgc; 430 431 for (prio = 0; prio <= XIVE_PRIORITY_MAX; prio++) { 432 current_level = first_group & 0x3F; 433 nvgc_blk = nvx_blk; 434 nvgc_idx = nvx_idx; 435 436 while (current_level) { 437 xive2_pgofnext(&nvgc_blk, &nvgc_idx, current_level); 438 439 if (xive2_router_get_nvgc(xrtr, NVx_CROWD_LVL(current_level), 440 nvgc_blk, nvgc_idx, &nvgc)) { 441 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVGC %x/%x\n", 442 nvgc_blk, nvgc_idx); 443 return 0xFF; 444 } 445 if (!xive2_nvgc_is_valid(&nvgc)) { 446 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVGC %x/%x\n", 447 nvgc_blk, nvgc_idx); 448 return 0xFF; 449 } 450 451 count = xive2_nvgc_get_backlog(&nvgc, prio); 452 if (count) { 453 *out_level = current_level; 454 return prio; 455 } 456 current_level = xive_get_field32(NVGC2_W0_PGONEXT, nvgc.w0) & 0x3F; 457 } 458 } 459 return 0xFF; 460 } 461 462 static void xive2_presenter_backlog_decr(XivePresenter *xptr, 463 uint8_t nvx_blk, uint32_t nvx_idx, 464 uint8_t group_prio, 465 uint8_t group_level) 466 { 467 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 468 uint32_t nvgc_idx, count; 469 uint8_t nvgc_blk; 470 Xive2Nvgc nvgc; 471 472 nvgc_blk = nvx_blk; 473 nvgc_idx = nvx_idx; 474 xive2_pgofnext(&nvgc_blk, &nvgc_idx, group_level); 475 476 if (xive2_router_get_nvgc(xrtr, NVx_CROWD_LVL(group_level), 477 nvgc_blk, nvgc_idx, &nvgc)) { 478 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVGC %x/%x\n", 479 nvgc_blk, nvgc_idx); 480 return; 481 } 482 if (!xive2_nvgc_is_valid(&nvgc)) { 483 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid NVGC %x/%x\n", 484 nvgc_blk, nvgc_idx); 485 return; 486 } 487 count = xive2_nvgc_get_backlog(&nvgc, group_prio); 488 if (!count) { 489 return; 490 } 491 xive2_nvgc_set_backlog(&nvgc, group_prio, count - 1); 492 xive2_router_write_nvgc(xrtr, NVx_CROWD_LVL(group_level), 493 nvgc_blk, nvgc_idx, &nvgc); 494 } 495 496 /* 497 * XIVE Thread Interrupt Management Area (TIMA) - Gen2 mode 498 * 499 * TIMA Gen2 VP “save & restore” (S&R) indicated by H bit next to V bit 500 * 501 * - if a context is enabled with the H bit set, the VP context 502 * information is retrieved from the NVP structure (“check out”) 503 * and stored back on a context pull (“check in”), the SW receives 504 * the same context pull information as on P9 505 * 506 * - the H bit cannot be changed while the V bit is set, i.e. a 507 * context cannot be set up in the TIMA and then be “pushed” into 508 * the NVP by changing the H bit while the context is enabled 509 */ 510 511 static void xive2_tctx_save_ctx(Xive2Router *xrtr, XiveTCTX *tctx, 512 uint8_t nvp_blk, uint32_t nvp_idx, 513 uint8_t ring) 514 { 515 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 516 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 517 Xive2Nvp nvp; 518 uint8_t *regs = &tctx->regs[ring]; 519 520 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 521 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 522 nvp_blk, nvp_idx); 523 return; 524 } 525 526 if (!xive2_nvp_is_valid(&nvp)) { 527 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 528 nvp_blk, nvp_idx); 529 return; 530 } 531 532 if (!xive2_nvp_is_hw(&nvp)) { 533 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n", 534 nvp_blk, nvp_idx); 535 return; 536 } 537 538 if (!xive2_nvp_is_co(&nvp)) { 539 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not checkout\n", 540 nvp_blk, nvp_idx); 541 return; 542 } 543 544 if (xive_get_field32(NVP2_W1_CO_THRID_VALID, nvp.w1) && 545 xive_get_field32(NVP2_W1_CO_THRID, nvp.w1) != pir) { 546 qemu_log_mask(LOG_GUEST_ERROR, 547 "XIVE: NVP %x/%x invalid checkout Thread %x\n", 548 nvp_blk, nvp_idx, pir); 549 return; 550 } 551 552 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, regs[TM_IPB]); 553 nvp.w2 = xive_set_field32(NVP2_W2_CPPR, nvp.w2, regs[TM_CPPR]); 554 if (nvp.w0 & NVP2_W0_L) { 555 /* 556 * Typically not used. If LSMFB is restored with 0, it will 557 * force a backlog rescan 558 */ 559 nvp.w2 = xive_set_field32(NVP2_W2_LSMFB, nvp.w2, regs[TM_LSMFB]); 560 } 561 if (nvp.w0 & NVP2_W0_G) { 562 nvp.w2 = xive_set_field32(NVP2_W2_LGS, nvp.w2, regs[TM_LGS]); 563 } 564 if (nvp.w0 & NVP2_W0_T) { 565 nvp.w2 = xive_set_field32(NVP2_W2_T, nvp.w2, regs[TM_T]); 566 } 567 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 568 569 nvp.w1 = xive_set_field32(NVP2_W1_CO, nvp.w1, 0); 570 /* NVP2_W1_CO_THRID_VALID only set once */ 571 nvp.w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp.w1, 0xFFFF); 572 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 1); 573 } 574 575 static void xive2_cam_decode(uint32_t cam, uint8_t *nvp_blk, 576 uint32_t *nvp_idx, bool *valid, bool *hw) 577 { 578 *nvp_blk = xive2_nvp_blk(cam); 579 *nvp_idx = xive2_nvp_idx(cam); 580 *valid = !!(cam & TM2_W2_VALID); 581 *hw = !!(cam & TM2_W2_HW); 582 } 583 584 /* 585 * Encode the HW CAM line with 7bit or 8bit thread id. The thread id 586 * width and block id width is configurable at the IC level. 587 * 588 * chipid << 24 | 0000 0000 0000 0000 1 threadid (7Bit) 589 * chipid << 24 | 0000 0000 0000 0001 threadid (8Bit) 590 */ 591 static uint32_t xive2_tctx_hw_cam_line(XivePresenter *xptr, XiveTCTX *tctx) 592 { 593 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 594 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 595 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 596 uint8_t blk = xive2_router_get_block_id(xrtr); 597 uint8_t tid_shift = 598 xive2_router_get_config(xrtr) & XIVE2_THREADID_8BITS ? 8 : 7; 599 uint8_t tid_mask = (1 << tid_shift) - 1; 600 601 return xive2_nvp_cam_line(blk, 1 << tid_shift | (pir & tid_mask)); 602 } 603 604 static void xive2_redistribute(Xive2Router *xrtr, XiveTCTX *tctx, uint8_t ring) 605 { 606 uint8_t *regs = &tctx->regs[ring]; 607 uint8_t nsr = regs[TM_NSR]; 608 uint8_t pipr = regs[TM_PIPR]; 609 uint8_t crowd = NVx_CROWD_LVL(nsr); 610 uint8_t group = NVx_GROUP_LVL(nsr); 611 uint8_t nvgc_blk, end_blk, nvp_blk; 612 uint32_t nvgc_idx, end_idx, nvp_idx; 613 Xive2Nvgc nvgc; 614 uint8_t prio_limit; 615 uint32_t cfg; 616 uint8_t alt_ring; 617 uint32_t target_ringw2; 618 uint32_t cam; 619 bool valid; 620 bool hw; 621 622 /* redistribution is only for group/crowd interrupts */ 623 if (!xive_nsr_indicates_group_exception(ring, nsr)) { 624 return; 625 } 626 627 alt_ring = xive_nsr_exception_ring(ring, nsr); 628 target_ringw2 = xive_tctx_word2(&tctx->regs[alt_ring]); 629 cam = be32_to_cpu(target_ringw2); 630 631 /* extract nvp block and index from targeted ring's cam */ 632 xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &valid, &hw); 633 634 trace_xive_redistribute(tctx->cs->cpu_index, alt_ring, nvp_blk, nvp_idx); 635 636 trace_xive_redistribute(tctx->cs->cpu_index, ring, nvp_blk, nvp_idx); 637 /* convert crowd/group to blk/idx */ 638 if (group > 0) { 639 nvgc_idx = (nvp_idx & (0xffffffff << group)) | 640 ((1 << (group - 1)) - 1); 641 } else { 642 nvgc_idx = nvp_idx; 643 } 644 645 if (crowd > 0) { 646 crowd = (crowd == 3) ? 4 : crowd; 647 nvgc_blk = (nvp_blk & (0xffffffff << crowd)) | 648 ((1 << (crowd - 1)) - 1); 649 } else { 650 nvgc_blk = nvp_blk; 651 } 652 653 /* Use blk/idx to retrieve the NVGC */ 654 if (xive2_router_get_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, &nvgc)) { 655 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no %s %x/%x\n", 656 crowd ? "NVC" : "NVG", nvgc_blk, nvgc_idx); 657 return; 658 } 659 660 /* retrieve the END blk/idx from the NVGC */ 661 end_blk = xive_get_field32(NVGC2_W1_END_BLK, nvgc.w1); 662 end_idx = xive_get_field32(NVGC2_W1_END_IDX, nvgc.w1); 663 664 /* determine number of priorities being used */ 665 cfg = xive2_router_get_config(xrtr); 666 if (cfg & XIVE2_EN_VP_GRP_PRIORITY) { 667 prio_limit = 1 << GETFIELD(NVGC2_W1_PSIZE, nvgc.w1); 668 } else { 669 prio_limit = 1 << GETFIELD(XIVE2_VP_INT_PRIO, cfg); 670 } 671 672 /* add priority offset to end index */ 673 end_idx += pipr % prio_limit; 674 675 /* trigger the group END */ 676 xive2_router_end_notify(xrtr, end_blk, end_idx, 0, true); 677 678 /* clear interrupt indication for the context */ 679 regs[TM_NSR] = 0; 680 regs[TM_PIPR] = regs[TM_CPPR]; 681 xive_tctx_reset_signal(tctx, ring); 682 } 683 684 static uint64_t xive2_tm_pull_ctx(XivePresenter *xptr, XiveTCTX *tctx, 685 hwaddr offset, unsigned size, uint8_t ring) 686 { 687 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 688 uint32_t target_ringw2 = xive_tctx_word2(&tctx->regs[ring]); 689 uint32_t cam = be32_to_cpu(target_ringw2); 690 uint8_t nvp_blk; 691 uint32_t nvp_idx; 692 uint8_t cur_ring; 693 bool valid; 694 bool do_save; 695 uint8_t nsr; 696 697 xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &valid, &do_save); 698 699 if (!valid) { 700 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: pulling invalid NVP %x/%x !?\n", 701 nvp_blk, nvp_idx); 702 } 703 704 /* Invalidate CAM line of requested ring and all lower rings */ 705 for (cur_ring = TM_QW0_USER; cur_ring <= ring; 706 cur_ring += XIVE_TM_RING_SIZE) { 707 uint32_t ringw2 = xive_tctx_word2(&tctx->regs[cur_ring]); 708 uint32_t ringw2_new = xive_set_field32(TM2_QW1W2_VO, ringw2, 0); 709 memcpy(&tctx->regs[cur_ring + TM_WORD2], &ringw2_new, 4); 710 } 711 712 /* Active group/crowd interrupts need to be redistributed */ 713 nsr = tctx->regs[ring + TM_NSR]; 714 if (xive_nsr_indicates_group_exception(ring, nsr)) { 715 xive2_redistribute(xrtr, tctx, ring); 716 } 717 718 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && do_save) { 719 xive2_tctx_save_ctx(xrtr, tctx, nvp_blk, nvp_idx, ring); 720 } 721 722 /* 723 * Lower external interrupt line of requested ring and below except for 724 * USER, which doesn't exist. 725 */ 726 for (cur_ring = TM_QW1_OS; cur_ring <= ring; 727 cur_ring += XIVE_TM_RING_SIZE) { 728 xive_tctx_reset_signal(tctx, cur_ring); 729 } 730 return target_ringw2; 731 } 732 733 uint64_t xive2_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 734 hwaddr offset, unsigned size) 735 { 736 return xive2_tm_pull_ctx(xptr, tctx, offset, size, TM_QW1_OS); 737 } 738 739 #define REPORT_LINE_GEN1_SIZE 16 740 741 static void xive2_tm_report_line_gen1(XiveTCTX *tctx, uint8_t *data, 742 uint8_t size) 743 { 744 uint8_t *regs = tctx->regs; 745 746 g_assert(size == REPORT_LINE_GEN1_SIZE); 747 memset(data, 0, size); 748 /* 749 * See xive architecture for description of what is saved. It is 750 * hand-picked information to fit in 16 bytes. 751 */ 752 data[0x0] = regs[TM_QW3_HV_PHYS + TM_NSR]; 753 data[0x1] = regs[TM_QW3_HV_PHYS + TM_CPPR]; 754 data[0x2] = regs[TM_QW3_HV_PHYS + TM_IPB]; 755 data[0x3] = regs[TM_QW2_HV_POOL + TM_IPB]; 756 data[0x4] = regs[TM_QW1_OS + TM_ACK_CNT]; 757 data[0x5] = regs[TM_QW3_HV_PHYS + TM_LGS]; 758 data[0x6] = 0xFF; 759 data[0x7] = regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x80; 760 data[0x7] |= (regs[TM_QW2_HV_POOL + TM_WORD2] & 0x80) >> 1; 761 data[0x7] |= (regs[TM_QW1_OS + TM_WORD2] & 0x80) >> 2; 762 data[0x7] |= (regs[TM_QW3_HV_PHYS + TM_WORD2] & 0x3); 763 data[0x8] = regs[TM_QW1_OS + TM_NSR]; 764 data[0x9] = regs[TM_QW1_OS + TM_CPPR]; 765 data[0xA] = regs[TM_QW1_OS + TM_IPB]; 766 data[0xB] = regs[TM_QW1_OS + TM_LGS]; 767 if (regs[TM_QW0_USER + TM_WORD2] & 0x80) { 768 /* 769 * Logical server extension, except VU bit replaced by EB bit 770 * from NSR 771 */ 772 data[0xC] = regs[TM_QW0_USER + TM_WORD2]; 773 data[0xC] &= ~0x80; 774 data[0xC] |= regs[TM_QW0_USER + TM_NSR] & 0x80; 775 data[0xD] = regs[TM_QW0_USER + TM_WORD2 + 1]; 776 data[0xE] = regs[TM_QW0_USER + TM_WORD2 + 2]; 777 data[0xF] = regs[TM_QW0_USER + TM_WORD2 + 3]; 778 } 779 } 780 781 static void xive2_tm_pull_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 782 hwaddr offset, uint64_t value, 783 unsigned size, uint8_t ring) 784 { 785 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 786 uint32_t hw_cam, nvp_idx, xive2_cfg, reserved; 787 uint8_t nvp_blk; 788 Xive2Nvp nvp; 789 uint64_t phys_addr; 790 MemTxResult result; 791 792 hw_cam = xive2_tctx_hw_cam_line(xptr, tctx); 793 nvp_blk = xive2_nvp_blk(hw_cam); 794 nvp_idx = xive2_nvp_idx(hw_cam); 795 796 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 797 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 798 nvp_blk, nvp_idx); 799 return; 800 } 801 802 if (!xive2_nvp_is_valid(&nvp)) { 803 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 804 nvp_blk, nvp_idx); 805 return; 806 } 807 808 xive2_cfg = xive2_router_get_config(xrtr); 809 810 phys_addr = xive2_nvp_reporting_addr(&nvp) + 0x80; /* odd line */ 811 if (xive2_cfg & XIVE2_GEN1_TIMA_OS) { 812 uint8_t pull_ctxt[REPORT_LINE_GEN1_SIZE]; 813 814 xive2_tm_report_line_gen1(tctx, pull_ctxt, REPORT_LINE_GEN1_SIZE); 815 result = dma_memory_write(&address_space_memory, phys_addr, 816 pull_ctxt, REPORT_LINE_GEN1_SIZE, 817 MEMTXATTRS_UNSPECIFIED); 818 assert(result == MEMTX_OK); 819 } else { 820 result = dma_memory_write(&address_space_memory, phys_addr, 821 &tctx->regs, sizeof(tctx->regs), 822 MEMTXATTRS_UNSPECIFIED); 823 assert(result == MEMTX_OK); 824 reserved = 0xFFFFFFFF; 825 result = dma_memory_write(&address_space_memory, phys_addr + 12, 826 &reserved, sizeof(reserved), 827 MEMTXATTRS_UNSPECIFIED); 828 assert(result == MEMTX_OK); 829 } 830 831 /* the rest is similar to pull context to registers */ 832 xive2_tm_pull_ctx(xptr, tctx, offset, size, ring); 833 } 834 835 void xive2_tm_pull_os_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 836 hwaddr offset, uint64_t value, unsigned size) 837 { 838 xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW1_OS); 839 } 840 841 842 void xive2_tm_pull_phys_ctx_ol(XivePresenter *xptr, XiveTCTX *tctx, 843 hwaddr offset, uint64_t value, unsigned size) 844 { 845 xive2_tm_pull_ctx_ol(xptr, tctx, offset, value, size, TM_QW3_HV_PHYS); 846 } 847 848 static uint8_t xive2_tctx_restore_os_ctx(Xive2Router *xrtr, XiveTCTX *tctx, 849 uint8_t nvp_blk, uint32_t nvp_idx, 850 Xive2Nvp *nvp) 851 { 852 CPUPPCState *env = &POWERPC_CPU(tctx->cs)->env; 853 uint32_t pir = env->spr_cb[SPR_PIR].default_value; 854 uint8_t cppr; 855 856 if (!xive2_nvp_is_hw(nvp)) { 857 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is not HW owned\n", 858 nvp_blk, nvp_idx); 859 return 0; 860 } 861 862 cppr = xive_get_field32(NVP2_W2_CPPR, nvp->w2); 863 nvp->w2 = xive_set_field32(NVP2_W2_CPPR, nvp->w2, 0); 864 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 2); 865 866 tctx->regs[TM_QW1_OS + TM_CPPR] = cppr; 867 tctx->regs[TM_QW1_OS + TM_LSMFB] = xive_get_field32(NVP2_W2_LSMFB, nvp->w2); 868 tctx->regs[TM_QW1_OS + TM_LGS] = xive_get_field32(NVP2_W2_LGS, nvp->w2); 869 tctx->regs[TM_QW1_OS + TM_T] = xive_get_field32(NVP2_W2_T, nvp->w2); 870 871 nvp->w1 = xive_set_field32(NVP2_W1_CO, nvp->w1, 1); 872 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID_VALID, nvp->w1, 1); 873 nvp->w1 = xive_set_field32(NVP2_W1_CO_THRID, nvp->w1, pir); 874 875 /* 876 * Checkout privilege: 0:OS, 1:Pool, 2:Hard 877 * 878 * TODO: we only support OS push/pull 879 */ 880 nvp->w1 = xive_set_field32(NVP2_W1_CO_PRIV, nvp->w1, 0); 881 882 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, nvp, 1); 883 884 /* return restored CPPR to generate a CPU exception if needed */ 885 return cppr; 886 } 887 888 static void xive2_tctx_need_resend(Xive2Router *xrtr, XiveTCTX *tctx, 889 uint8_t nvp_blk, uint32_t nvp_idx, 890 bool do_restore) 891 { 892 XivePresenter *xptr = XIVE_PRESENTER(xrtr); 893 uint8_t ipb; 894 uint8_t backlog_level; 895 uint8_t group_level; 896 uint8_t first_group; 897 uint8_t backlog_prio; 898 uint8_t group_prio; 899 uint8_t *regs = &tctx->regs[TM_QW1_OS]; 900 Xive2Nvp nvp; 901 902 /* 903 * Grab the associated thread interrupt context registers in the 904 * associated NVP 905 */ 906 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 907 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 908 nvp_blk, nvp_idx); 909 return; 910 } 911 912 if (!xive2_nvp_is_valid(&nvp)) { 913 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 914 nvp_blk, nvp_idx); 915 return; 916 } 917 918 /* Automatically restore thread context registers */ 919 if (xive2_router_get_config(xrtr) & XIVE2_VP_SAVE_RESTORE && 920 do_restore) { 921 xive2_tctx_restore_os_ctx(xrtr, tctx, nvp_blk, nvp_idx, &nvp); 922 } 923 924 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2); 925 if (ipb) { 926 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, 0); 927 xive2_router_write_nvp(xrtr, nvp_blk, nvp_idx, &nvp, 2); 928 } 929 /* IPB bits in the backlog are merged with the TIMA IPB bits */ 930 regs[TM_IPB] |= ipb; 931 backlog_prio = xive_ipb_to_pipr(regs[TM_IPB]); 932 backlog_level = 0; 933 934 first_group = xive_get_field32(NVP2_W0_PGOFIRST, nvp.w0); 935 if (first_group && regs[TM_LSMFB] < backlog_prio) { 936 group_prio = xive2_presenter_backlog_scan(xptr, nvp_blk, nvp_idx, 937 first_group, &group_level); 938 regs[TM_LSMFB] = group_prio; 939 if (regs[TM_LGS] && group_prio < backlog_prio && 940 group_prio < regs[TM_CPPR]) { 941 942 /* VP can take a group interrupt */ 943 xive2_presenter_backlog_decr(xptr, nvp_blk, nvp_idx, 944 group_prio, group_level); 945 backlog_prio = group_prio; 946 backlog_level = group_level; 947 } 948 } 949 950 /* 951 * Compute the PIPR based on the restored state. 952 * It will raise the External interrupt signal if needed. 953 */ 954 xive_tctx_pipr_update(tctx, TM_QW1_OS, backlog_prio, backlog_level); 955 } 956 957 /* 958 * Updating the OS CAM line can trigger a resend of interrupt 959 */ 960 void xive2_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx, 961 hwaddr offset, uint64_t value, unsigned size) 962 { 963 uint32_t cam; 964 uint32_t qw1w2; 965 uint64_t qw1dw1; 966 uint8_t nvp_blk; 967 uint32_t nvp_idx; 968 bool vo; 969 bool do_restore; 970 971 /* First update the thead context */ 972 switch (size) { 973 case 4: 974 cam = value; 975 qw1w2 = cpu_to_be32(cam); 976 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4); 977 break; 978 case 8: 979 cam = value >> 32; 980 qw1dw1 = cpu_to_be64(value); 981 memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1dw1, 8); 982 break; 983 default: 984 g_assert_not_reached(); 985 } 986 987 xive2_cam_decode(cam, &nvp_blk, &nvp_idx, &vo, &do_restore); 988 989 /* Check the interrupt pending bits */ 990 if (vo) { 991 xive2_tctx_need_resend(XIVE2_ROUTER(xptr), tctx, nvp_blk, nvp_idx, 992 do_restore); 993 } 994 } 995 996 static int xive2_tctx_get_nvp_indexes(XiveTCTX *tctx, uint8_t ring, 997 uint32_t *nvp_blk, uint32_t *nvp_idx) 998 { 999 uint32_t w2, cam; 1000 1001 w2 = xive_tctx_word2(&tctx->regs[ring]); 1002 switch (ring) { 1003 case TM_QW1_OS: 1004 if (!(be32_to_cpu(w2) & TM2_QW1W2_VO)) { 1005 return -1; 1006 } 1007 cam = xive_get_field32(TM2_QW1W2_OS_CAM, w2); 1008 break; 1009 case TM_QW2_HV_POOL: 1010 if (!(be32_to_cpu(w2) & TM2_QW2W2_VP)) { 1011 return -1; 1012 } 1013 cam = xive_get_field32(TM2_QW2W2_POOL_CAM, w2); 1014 break; 1015 case TM_QW3_HV_PHYS: 1016 if (!(be32_to_cpu(w2) & TM2_QW3W2_VT)) { 1017 return -1; 1018 } 1019 cam = xive2_tctx_hw_cam_line(tctx->xptr, tctx); 1020 break; 1021 default: 1022 return -1; 1023 } 1024 *nvp_blk = xive2_nvp_blk(cam); 1025 *nvp_idx = xive2_nvp_idx(cam); 1026 return 0; 1027 } 1028 1029 static void xive2_tctx_accept_el(XivePresenter *xptr, XiveTCTX *tctx, 1030 uint8_t ring, uint8_t cl_ring) 1031 { 1032 uint64_t rd; 1033 Xive2Router *xrtr = XIVE2_ROUTER(xptr); 1034 uint32_t nvp_blk, nvp_idx, xive2_cfg; 1035 Xive2Nvp nvp; 1036 uint64_t phys_addr; 1037 uint8_t OGen = 0; 1038 1039 xive2_tctx_get_nvp_indexes(tctx, cl_ring, &nvp_blk, &nvp_idx); 1040 1041 if (xive2_router_get_nvp(xrtr, (uint8_t)nvp_blk, nvp_idx, &nvp)) { 1042 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 1043 nvp_blk, nvp_idx); 1044 return; 1045 } 1046 1047 if (!xive2_nvp_is_valid(&nvp)) { 1048 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 1049 nvp_blk, nvp_idx); 1050 return; 1051 } 1052 1053 1054 rd = xive_tctx_accept(tctx, ring); 1055 1056 if (ring == TM_QW1_OS) { 1057 OGen = tctx->regs[ring + TM_OGEN]; 1058 } 1059 xive2_cfg = xive2_router_get_config(xrtr); 1060 phys_addr = xive2_nvp_reporting_addr(&nvp); 1061 uint8_t report_data[REPORT_LINE_GEN1_SIZE]; 1062 memset(report_data, 0xff, sizeof(report_data)); 1063 if ((OGen == 1) || (xive2_cfg & XIVE2_GEN1_TIMA_OS)) { 1064 report_data[8] = (rd >> 8) & 0xff; 1065 report_data[9] = rd & 0xff; 1066 } else { 1067 report_data[0] = (rd >> 8) & 0xff; 1068 report_data[1] = rd & 0xff; 1069 } 1070 cpu_physical_memory_write(phys_addr, report_data, REPORT_LINE_GEN1_SIZE); 1071 } 1072 1073 void xive2_tm_ack_os_el(XivePresenter *xptr, XiveTCTX *tctx, 1074 hwaddr offset, uint64_t value, unsigned size) 1075 { 1076 xive2_tctx_accept_el(xptr, tctx, TM_QW1_OS, TM_QW1_OS); 1077 } 1078 1079 /* NOTE: CPPR only exists for TM_QW1_OS and TM_QW3_HV_PHYS */ 1080 static void xive2_tctx_set_cppr(XiveTCTX *tctx, uint8_t ring, uint8_t cppr) 1081 { 1082 uint8_t *regs = &tctx->regs[ring]; 1083 Xive2Router *xrtr = XIVE2_ROUTER(tctx->xptr); 1084 uint8_t old_cppr, backlog_prio, first_group, group_level; 1085 uint8_t pipr_min, lsmfb_min, ring_min; 1086 bool group_enabled; 1087 uint32_t nvp_blk, nvp_idx; 1088 Xive2Nvp nvp; 1089 int rc; 1090 uint8_t nsr = regs[TM_NSR]; 1091 1092 trace_xive_tctx_set_cppr(tctx->cs->cpu_index, ring, 1093 regs[TM_IPB], regs[TM_PIPR], 1094 cppr, nsr); 1095 1096 if (cppr > XIVE_PRIORITY_MAX) { 1097 cppr = 0xff; 1098 } 1099 1100 old_cppr = regs[TM_CPPR]; 1101 regs[TM_CPPR] = cppr; 1102 1103 /* Handle increased CPPR priority (lower value) */ 1104 if (cppr < old_cppr) { 1105 if (cppr <= regs[TM_PIPR]) { 1106 /* CPPR lowered below PIPR, must un-present interrupt */ 1107 if (xive_nsr_indicates_exception(ring, nsr)) { 1108 if (xive_nsr_indicates_group_exception(ring, nsr)) { 1109 /* redistribute precluded active grp interrupt */ 1110 xive2_redistribute(xrtr, tctx, ring); 1111 return; 1112 } 1113 } 1114 1115 /* interrupt is VP directed, pending in IPB */ 1116 regs[TM_PIPR] = cppr; 1117 xive_tctx_notify(tctx, ring, 0); /* Ensure interrupt is cleared */ 1118 return; 1119 } else { 1120 /* CPPR was lowered, but still above PIPR. No action needed. */ 1121 return; 1122 } 1123 } 1124 1125 /* CPPR didn't change, nothing needs to be done */ 1126 if (cppr == old_cppr) { 1127 return; 1128 } 1129 1130 /* CPPR priority decreased (higher value) */ 1131 1132 /* 1133 * Recompute the PIPR based on local pending interrupts. It will 1134 * be adjusted below if needed in case of pending group interrupts. 1135 */ 1136 again: 1137 pipr_min = xive_ipb_to_pipr(regs[TM_IPB]); 1138 group_enabled = !!regs[TM_LGS]; 1139 lsmfb_min = group_enabled ? regs[TM_LSMFB] : 0xff; 1140 ring_min = ring; 1141 group_level = 0; 1142 1143 /* PHYS updates also depend on POOL values */ 1144 if (ring == TM_QW3_HV_PHYS) { 1145 uint8_t *pool_regs = &tctx->regs[TM_QW2_HV_POOL]; 1146 1147 /* POOL values only matter if POOL ctx is valid */ 1148 if (pool_regs[TM_WORD2] & 0x80) { 1149 uint8_t pool_pipr = xive_ipb_to_pipr(pool_regs[TM_IPB]); 1150 uint8_t pool_lsmfb = pool_regs[TM_LSMFB]; 1151 1152 /* 1153 * Determine highest priority interrupt and 1154 * remember which ring has it. 1155 */ 1156 if (pool_pipr < pipr_min) { 1157 pipr_min = pool_pipr; 1158 if (pool_pipr < lsmfb_min) { 1159 ring_min = TM_QW2_HV_POOL; 1160 } 1161 } 1162 1163 /* Values needed for group priority calculation */ 1164 if (pool_regs[TM_LGS] && (pool_lsmfb < lsmfb_min)) { 1165 group_enabled = true; 1166 lsmfb_min = pool_lsmfb; 1167 if (lsmfb_min < pipr_min) { 1168 ring_min = TM_QW2_HV_POOL; 1169 } 1170 } 1171 } 1172 } 1173 1174 rc = xive2_tctx_get_nvp_indexes(tctx, ring_min, &nvp_blk, &nvp_idx); 1175 if (rc) { 1176 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: set CPPR on invalid context\n"); 1177 return; 1178 } 1179 1180 if (group_enabled && 1181 lsmfb_min < cppr && 1182 lsmfb_min < pipr_min) { 1183 /* 1184 * Thread has seen a group interrupt with a higher priority 1185 * than the new cppr or pending local interrupt. Check the 1186 * backlog 1187 */ 1188 if (xive2_router_get_nvp(xrtr, nvp_blk, nvp_idx, &nvp)) { 1189 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No NVP %x/%x\n", 1190 nvp_blk, nvp_idx); 1191 return; 1192 } 1193 1194 if (!xive2_nvp_is_valid(&nvp)) { 1195 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 1196 nvp_blk, nvp_idx); 1197 return; 1198 } 1199 1200 first_group = xive_get_field32(NVP2_W0_PGOFIRST, nvp.w0); 1201 if (!first_group) { 1202 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid NVP %x/%x\n", 1203 nvp_blk, nvp_idx); 1204 return; 1205 } 1206 1207 backlog_prio = xive2_presenter_backlog_scan(tctx->xptr, 1208 nvp_blk, nvp_idx, 1209 first_group, &group_level); 1210 tctx->regs[ring_min + TM_LSMFB] = backlog_prio; 1211 if (backlog_prio != lsmfb_min) { 1212 /* 1213 * If the group backlog scan finds a less favored or no interrupt, 1214 * then re-do the processing which may turn up a more favored 1215 * interrupt from IPB or the other pool. Backlog should not 1216 * find a priority < LSMFB. 1217 */ 1218 g_assert(backlog_prio >= lsmfb_min); 1219 goto again; 1220 } 1221 1222 xive2_presenter_backlog_decr(tctx->xptr, nvp_blk, nvp_idx, 1223 backlog_prio, group_level); 1224 pipr_min = backlog_prio; 1225 } 1226 1227 /* PIPR should not be set to a value greater than CPPR */ 1228 regs[TM_PIPR] = (pipr_min > cppr) ? cppr : pipr_min; 1229 1230 /* CPPR has changed, check if we need to raise a pending exception */ 1231 xive_tctx_notify(tctx, ring_min, group_level); 1232 } 1233 1234 void xive2_tm_set_hv_cppr(XivePresenter *xptr, XiveTCTX *tctx, 1235 hwaddr offset, uint64_t value, unsigned size) 1236 { 1237 xive2_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); 1238 } 1239 1240 void xive2_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx, 1241 hwaddr offset, uint64_t value, unsigned size) 1242 { 1243 xive2_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff); 1244 } 1245 1246 static void xive2_tctx_set_target(XiveTCTX *tctx, uint8_t ring, uint8_t target) 1247 { 1248 uint8_t *regs = &tctx->regs[ring]; 1249 1250 regs[TM_T] = target; 1251 } 1252 1253 void xive2_tm_set_hv_target(XivePresenter *xptr, XiveTCTX *tctx, 1254 hwaddr offset, uint64_t value, unsigned size) 1255 { 1256 xive2_tctx_set_target(tctx, TM_QW3_HV_PHYS, value & 0xff); 1257 } 1258 1259 /* 1260 * XIVE Router (aka. Virtualization Controller or IVRE) 1261 */ 1262 1263 int xive2_router_get_eas(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1264 Xive2Eas *eas) 1265 { 1266 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1267 1268 return xrc->get_eas(xrtr, eas_blk, eas_idx, eas); 1269 } 1270 1271 static 1272 int xive2_router_get_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1273 uint8_t *pq) 1274 { 1275 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1276 1277 return xrc->get_pq(xrtr, eas_blk, eas_idx, pq); 1278 } 1279 1280 static 1281 int xive2_router_set_pq(Xive2Router *xrtr, uint8_t eas_blk, uint32_t eas_idx, 1282 uint8_t *pq) 1283 { 1284 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1285 1286 return xrc->set_pq(xrtr, eas_blk, eas_idx, pq); 1287 } 1288 1289 int xive2_router_get_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 1290 Xive2End *end) 1291 { 1292 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1293 1294 return xrc->get_end(xrtr, end_blk, end_idx, end); 1295 } 1296 1297 int xive2_router_write_end(Xive2Router *xrtr, uint8_t end_blk, uint32_t end_idx, 1298 Xive2End *end, uint8_t word_number) 1299 { 1300 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1301 1302 return xrc->write_end(xrtr, end_blk, end_idx, end, word_number); 1303 } 1304 1305 int xive2_router_get_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 1306 Xive2Nvp *nvp) 1307 { 1308 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1309 1310 return xrc->get_nvp(xrtr, nvp_blk, nvp_idx, nvp); 1311 } 1312 1313 int xive2_router_write_nvp(Xive2Router *xrtr, uint8_t nvp_blk, uint32_t nvp_idx, 1314 Xive2Nvp *nvp, uint8_t word_number) 1315 { 1316 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1317 1318 return xrc->write_nvp(xrtr, nvp_blk, nvp_idx, nvp, word_number); 1319 } 1320 1321 int xive2_router_get_nvgc(Xive2Router *xrtr, bool crowd, 1322 uint8_t nvgc_blk, uint32_t nvgc_idx, 1323 Xive2Nvgc *nvgc) 1324 { 1325 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1326 1327 return xrc->get_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc); 1328 } 1329 1330 int xive2_router_write_nvgc(Xive2Router *xrtr, bool crowd, 1331 uint8_t nvgc_blk, uint32_t nvgc_idx, 1332 Xive2Nvgc *nvgc) 1333 { 1334 Xive2RouterClass *xrc = XIVE2_ROUTER_GET_CLASS(xrtr); 1335 1336 return xrc->write_nvgc(xrtr, crowd, nvgc_blk, nvgc_idx, nvgc); 1337 } 1338 1339 static bool xive2_vp_match_mask(uint32_t cam1, uint32_t cam2, 1340 uint32_t vp_mask) 1341 { 1342 return (cam1 & vp_mask) == (cam2 & vp_mask); 1343 } 1344 1345 static uint8_t xive2_get_vp_block_mask(uint32_t nvt_blk, bool crowd) 1346 { 1347 uint8_t block_mask = 0b1111; 1348 1349 /* 3 supported crowd sizes: 2, 4, 16 */ 1350 if (crowd) { 1351 uint32_t size = xive_get_vpgroup_size(nvt_blk); 1352 1353 if (size != 2 && size != 4 && size != 16) { 1354 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid crowd size of %d", 1355 size); 1356 return block_mask; 1357 } 1358 block_mask &= ~(size - 1); 1359 } 1360 return block_mask; 1361 } 1362 1363 static uint32_t xive2_get_vp_index_mask(uint32_t nvt_index, bool cam_ignore) 1364 { 1365 uint32_t index_mask = 0xFFFFFF; /* 24 bits */ 1366 1367 if (cam_ignore) { 1368 uint32_t size = xive_get_vpgroup_size(nvt_index); 1369 1370 if (size < 2) { 1371 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid group size of %d", 1372 size); 1373 return index_mask; 1374 } 1375 index_mask &= ~(size - 1); 1376 } 1377 return index_mask; 1378 } 1379 1380 /* 1381 * The thread context register words are in big-endian format. 1382 */ 1383 int xive2_presenter_tctx_match(XivePresenter *xptr, XiveTCTX *tctx, 1384 uint8_t format, 1385 uint8_t nvt_blk, uint32_t nvt_idx, 1386 bool crowd, bool cam_ignore, 1387 uint32_t logic_serv) 1388 { 1389 uint32_t cam = xive2_nvp_cam_line(nvt_blk, nvt_idx); 1390 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); 1391 uint32_t qw2w2 = xive_tctx_word2(&tctx->regs[TM_QW2_HV_POOL]); 1392 uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]); 1393 uint32_t qw0w2 = xive_tctx_word2(&tctx->regs[TM_QW0_USER]); 1394 1395 uint32_t index_mask, vp_mask; 1396 uint8_t block_mask; 1397 1398 if (format == 0) { 1399 /* 1400 * i=0: Specific NVT notification 1401 * i=1: VP-group notification (bits ignored at the end of the 1402 * NVT identifier) 1403 */ 1404 block_mask = xive2_get_vp_block_mask(nvt_blk, crowd); 1405 index_mask = xive2_get_vp_index_mask(nvt_idx, cam_ignore); 1406 vp_mask = xive2_nvp_cam_line(block_mask, index_mask); 1407 1408 /* For VP-group notifications, threads with LGS=0 are excluded */ 1409 1410 /* PHYS ring */ 1411 if ((be32_to_cpu(qw3w2) & TM2_QW3W2_VT) && 1412 !(cam_ignore && tctx->regs[TM_QW3_HV_PHYS + TM_LGS] == 0) && 1413 xive2_vp_match_mask(cam, 1414 xive2_tctx_hw_cam_line(xptr, tctx), 1415 vp_mask)) { 1416 return TM_QW3_HV_PHYS; 1417 } 1418 1419 /* HV POOL ring */ 1420 if ((be32_to_cpu(qw2w2) & TM2_QW2W2_VP) && 1421 !(cam_ignore && tctx->regs[TM_QW2_HV_POOL + TM_LGS] == 0) && 1422 xive2_vp_match_mask(cam, 1423 xive_get_field32(TM2_QW2W2_POOL_CAM, qw2w2), 1424 vp_mask)) { 1425 return TM_QW2_HV_POOL; 1426 } 1427 1428 /* OS ring */ 1429 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 1430 !(cam_ignore && tctx->regs[TM_QW1_OS + TM_LGS] == 0) && 1431 xive2_vp_match_mask(cam, 1432 xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2), 1433 vp_mask)) { 1434 return TM_QW1_OS; 1435 } 1436 } else { 1437 /* F=1 : User level Event-Based Branch (EBB) notification */ 1438 1439 /* FIXME: what if cam_ignore and LGS = 0 ? */ 1440 /* USER ring */ 1441 if ((be32_to_cpu(qw1w2) & TM2_QW1W2_VO) && 1442 (cam == xive_get_field32(TM2_QW1W2_OS_CAM, qw1w2)) && 1443 (be32_to_cpu(qw0w2) & TM2_QW0W2_VU) && 1444 (logic_serv == xive_get_field32(TM2_QW0W2_LOGIC_SERV, qw0w2))) { 1445 return TM_QW0_USER; 1446 } 1447 } 1448 return -1; 1449 } 1450 1451 bool xive2_tm_irq_precluded(XiveTCTX *tctx, int ring, uint8_t priority) 1452 { 1453 /* HV_POOL ring uses HV_PHYS NSR, CPPR and PIPR registers */ 1454 uint8_t alt_ring = (ring == TM_QW2_HV_POOL) ? TM_QW3_HV_PHYS : ring; 1455 uint8_t *alt_regs = &tctx->regs[alt_ring]; 1456 1457 /* 1458 * The xive2_presenter_tctx_match() above tells if there's a match 1459 * but for VP-group notification, we still need to look at the 1460 * priority to know if the thread can take the interrupt now or if 1461 * it is precluded. 1462 */ 1463 if (priority < alt_regs[TM_PIPR]) { 1464 return false; 1465 } 1466 return true; 1467 } 1468 1469 void xive2_tm_set_lsmfb(XiveTCTX *tctx, int ring, uint8_t priority) 1470 { 1471 uint8_t *regs = &tctx->regs[ring]; 1472 1473 /* 1474 * Called by the router during a VP-group notification when the 1475 * thread matches but can't take the interrupt because it's 1476 * already running at a more favored priority. It then stores the 1477 * new interrupt priority in the LSMFB field. 1478 */ 1479 regs[TM_LSMFB] = priority; 1480 } 1481 1482 static void xive2_router_realize(DeviceState *dev, Error **errp) 1483 { 1484 Xive2Router *xrtr = XIVE2_ROUTER(dev); 1485 1486 assert(xrtr->xfb); 1487 } 1488 1489 /* 1490 * Notification using the END ESe/ESn bit (Event State Buffer for 1491 * escalation and notification). Profide further coalescing in the 1492 * Router. 1493 */ 1494 static bool xive2_router_end_es_notify(Xive2Router *xrtr, uint8_t end_blk, 1495 uint32_t end_idx, Xive2End *end, 1496 uint32_t end_esmask) 1497 { 1498 uint8_t pq = xive_get_field32(end_esmask, end->w1); 1499 bool notify = xive_esb_trigger(&pq); 1500 1501 if (pq != xive_get_field32(end_esmask, end->w1)) { 1502 end->w1 = xive_set_field32(end_esmask, end->w1, pq); 1503 xive2_router_write_end(xrtr, end_blk, end_idx, end, 1); 1504 } 1505 1506 /* ESe/n[Q]=1 : end of notification */ 1507 return notify; 1508 } 1509 1510 /* 1511 * An END trigger can come from an event trigger (IPI or HW) or from 1512 * another chip. We don't model the PowerBus but the END trigger 1513 * message has the same parameters than in the function below. 1514 */ 1515 static void xive2_router_end_notify(Xive2Router *xrtr, uint8_t end_blk, 1516 uint32_t end_idx, uint32_t end_data, 1517 bool redistribute) 1518 { 1519 Xive2End end; 1520 uint8_t priority; 1521 uint8_t format; 1522 bool found, precluded; 1523 uint8_t nvx_blk; 1524 uint32_t nvx_idx; 1525 1526 /* END cache lookup */ 1527 if (xive2_router_get_end(xrtr, end_blk, end_idx, &end)) { 1528 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1529 end_idx); 1530 return; 1531 } 1532 1533 if (!xive2_end_is_valid(&end)) { 1534 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1535 end_blk, end_idx); 1536 return; 1537 } 1538 1539 if (xive2_end_is_crowd(&end) && !xive2_end_is_ignore(&end)) { 1540 qemu_log_mask(LOG_GUEST_ERROR, 1541 "XIVE: invalid END, 'crowd' bit requires 'ignore' bit\n"); 1542 return; 1543 } 1544 1545 if (!redistribute && xive2_end_is_enqueue(&end)) { 1546 trace_xive_end_enqueue(end_blk, end_idx, end_data); 1547 xive2_end_enqueue(&end, end_data); 1548 /* Enqueuing event data modifies the EQ toggle and index */ 1549 xive2_router_write_end(xrtr, end_blk, end_idx, &end, 1); 1550 } 1551 1552 /* 1553 * When the END is silent, we skip the notification part. 1554 */ 1555 if (xive2_end_is_silent_escalation(&end)) { 1556 goto do_escalation; 1557 } 1558 1559 /* 1560 * The W7 format depends on the F bit in W6. It defines the type 1561 * of the notification : 1562 * 1563 * F=0 : single or multiple NVP notification 1564 * F=1 : User level Event-Based Branch (EBB) notification, no 1565 * priority 1566 */ 1567 format = xive_get_field32(END2_W6_FORMAT_BIT, end.w6); 1568 priority = xive_get_field32(END2_W7_F0_PRIORITY, end.w7); 1569 1570 /* The END is masked */ 1571 if (format == 0 && priority == 0xff) { 1572 return; 1573 } 1574 1575 /* 1576 * Check the END ESn (Event State Buffer for notification) for 1577 * even further coalescing in the Router 1578 */ 1579 if (!xive2_end_is_notify(&end)) { 1580 /* ESn[Q]=1 : end of notification */ 1581 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 1582 &end, END2_W1_ESn)) { 1583 return; 1584 } 1585 } 1586 1587 /* 1588 * Follows IVPE notification 1589 */ 1590 nvx_blk = xive_get_field32(END2_W6_VP_BLOCK, end.w6); 1591 nvx_idx = xive_get_field32(END2_W6_VP_OFFSET, end.w6); 1592 1593 found = xive_presenter_notify(xrtr->xfb, format, nvx_blk, nvx_idx, 1594 xive2_end_is_crowd(&end), xive2_end_is_ignore(&end), 1595 priority, 1596 xive_get_field32(END2_W7_F1_LOG_SERVER_ID, end.w7), 1597 &precluded); 1598 1599 /* TODO: Auto EOI. */ 1600 1601 if (found) { 1602 return; 1603 } 1604 1605 /* 1606 * If no matching NVP is dispatched on a HW thread : 1607 * - specific VP: update the NVP structure if backlog is activated 1608 * - VP-group: update the backlog counter for that priority in the NVG 1609 */ 1610 if (xive2_end_is_backlog(&end)) { 1611 1612 if (format == 1) { 1613 qemu_log_mask(LOG_GUEST_ERROR, 1614 "XIVE: END %x/%x invalid config: F1 & backlog\n", 1615 end_blk, end_idx); 1616 return; 1617 } 1618 1619 if (!xive2_end_is_ignore(&end)) { 1620 uint8_t ipb; 1621 Xive2Nvp nvp; 1622 1623 /* NVP cache lookup */ 1624 if (xive2_router_get_nvp(xrtr, nvx_blk, nvx_idx, &nvp)) { 1625 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no NVP %x/%x\n", 1626 nvx_blk, nvx_idx); 1627 return; 1628 } 1629 1630 if (!xive2_nvp_is_valid(&nvp)) { 1631 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVP %x/%x is invalid\n", 1632 nvx_blk, nvx_idx); 1633 return; 1634 } 1635 1636 /* 1637 * Record the IPB in the associated NVP structure for later 1638 * use. The presenter will resend the interrupt when the vCPU 1639 * is dispatched again on a HW thread. 1640 */ 1641 ipb = xive_get_field32(NVP2_W2_IPB, nvp.w2) | 1642 xive_priority_to_ipb(priority); 1643 nvp.w2 = xive_set_field32(NVP2_W2_IPB, nvp.w2, ipb); 1644 xive2_router_write_nvp(xrtr, nvx_blk, nvx_idx, &nvp, 2); 1645 } else { 1646 Xive2Nvgc nvgc; 1647 uint32_t backlog; 1648 bool crowd; 1649 1650 crowd = xive2_end_is_crowd(&end); 1651 1652 /* 1653 * For groups and crowds, the per-priority backlog 1654 * counters are stored in the NVG/NVC structures 1655 */ 1656 if (xive2_router_get_nvgc(xrtr, crowd, 1657 nvx_blk, nvx_idx, &nvgc)) { 1658 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: no %s %x/%x\n", 1659 crowd ? "NVC" : "NVG", nvx_blk, nvx_idx); 1660 return; 1661 } 1662 1663 if (!xive2_nvgc_is_valid(&nvgc)) { 1664 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: NVG %x/%x is invalid\n", 1665 nvx_blk, nvx_idx); 1666 return; 1667 } 1668 1669 /* 1670 * Increment the backlog counter for that priority. 1671 * We only call broadcast the first time the counter is 1672 * incremented. broadcast will set the LSMFB field of the TIMA of 1673 * relevant threads so that they know an interrupt is pending. 1674 */ 1675 backlog = xive2_nvgc_get_backlog(&nvgc, priority) + 1; 1676 xive2_nvgc_set_backlog(&nvgc, priority, backlog); 1677 xive2_router_write_nvgc(xrtr, crowd, nvx_blk, nvx_idx, &nvgc); 1678 1679 if (backlog == 1) { 1680 XiveFabricClass *xfc = XIVE_FABRIC_GET_CLASS(xrtr->xfb); 1681 xfc->broadcast(xrtr->xfb, nvx_blk, nvx_idx, 1682 xive2_end_is_crowd(&end), 1683 xive2_end_is_ignore(&end), 1684 priority); 1685 1686 if (!xive2_end_is_precluded_escalation(&end)) { 1687 /* 1688 * The interrupt will be picked up when the 1689 * matching thread lowers its priority level 1690 */ 1691 return; 1692 } 1693 } 1694 } 1695 } 1696 1697 do_escalation: 1698 /* 1699 * If activated, escalate notification using the ESe PQ bits and 1700 * the EAS in w4-5 1701 */ 1702 if (!xive2_end_is_escalate(&end)) { 1703 return; 1704 } 1705 1706 /* 1707 * Check the END ESe (Event State Buffer for escalation) for even 1708 * further coalescing in the Router 1709 */ 1710 if (!xive2_end_is_uncond_escalation(&end)) { 1711 /* ESe[Q]=1 : end of escalation notification */ 1712 if (!xive2_router_end_es_notify(xrtr, end_blk, end_idx, 1713 &end, END2_W1_ESe)) { 1714 return; 1715 } 1716 } 1717 1718 if (xive2_end_is_escalate_end(&end)) { 1719 /* 1720 * Perform END Adaptive escalation processing 1721 * The END trigger becomes an Escalation trigger 1722 */ 1723 uint8_t esc_blk = xive_get_field32(END2_W4_END_BLOCK, end.w4); 1724 uint32_t esc_idx = xive_get_field32(END2_W4_ESC_END_INDEX, end.w4); 1725 uint32_t esc_data = xive_get_field32(END2_W5_ESC_END_DATA, end.w5); 1726 trace_xive_escalate_end(end_blk, end_idx, esc_blk, esc_idx, esc_data); 1727 xive2_router_end_notify(xrtr, esc_blk, esc_idx, esc_data, false); 1728 } /* end END adaptive escalation */ 1729 1730 else { 1731 uint32_t lisn; /* Logical Interrupt Source Number */ 1732 1733 /* 1734 * Perform ESB escalation processing 1735 * E[N] == 1 --> N 1736 * Req[Block] <- E[ESB_Block] 1737 * Req[Index] <- E[ESB_Index] 1738 * Req[Offset] <- 0x000 1739 * Execute <ESB Store> Req command 1740 */ 1741 lisn = XIVE_EAS(xive_get_field32(END2_W4_END_BLOCK, end.w4), 1742 xive_get_field32(END2_W4_ESC_END_INDEX, end.w4)); 1743 1744 trace_xive_escalate_esb(end_blk, end_idx, lisn); 1745 xive2_notify(xrtr, lisn, true /* pq_checked */); 1746 } 1747 1748 return; 1749 } 1750 1751 void xive2_notify(Xive2Router *xrtr , uint32_t lisn, bool pq_checked) 1752 { 1753 uint8_t eas_blk = XIVE_EAS_BLOCK(lisn); 1754 uint32_t eas_idx = XIVE_EAS_INDEX(lisn); 1755 Xive2Eas eas; 1756 1757 /* EAS cache lookup */ 1758 if (xive2_router_get_eas(xrtr, eas_blk, eas_idx, &eas)) { 1759 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Unknown LISN %x\n", lisn); 1760 return; 1761 } 1762 1763 if (!pq_checked) { 1764 bool notify; 1765 uint8_t pq; 1766 1767 /* PQ cache lookup */ 1768 if (xive2_router_get_pq(xrtr, eas_blk, eas_idx, &pq)) { 1769 /* Set FIR */ 1770 g_assert_not_reached(); 1771 } 1772 1773 notify = xive_esb_trigger(&pq); 1774 1775 if (xive2_router_set_pq(xrtr, eas_blk, eas_idx, &pq)) { 1776 /* Set FIR */ 1777 g_assert_not_reached(); 1778 } 1779 1780 if (!notify) { 1781 return; 1782 } 1783 } 1784 1785 if (!xive2_eas_is_valid(&eas)) { 1786 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: Invalid LISN %x\n", lisn); 1787 return; 1788 } 1789 1790 if (xive2_eas_is_masked(&eas)) { 1791 /* Notification completed */ 1792 return; 1793 } 1794 1795 /* TODO: add support for EAS resume */ 1796 if (xive2_eas_is_resume(&eas)) { 1797 qemu_log_mask(LOG_UNIMP, 1798 "XIVE: EAS resume processing unimplemented - LISN %x\n", 1799 lisn); 1800 return; 1801 } 1802 1803 /* 1804 * The event trigger becomes an END trigger 1805 */ 1806 xive2_router_end_notify(xrtr, 1807 xive_get_field64(EAS2_END_BLOCK, eas.w), 1808 xive_get_field64(EAS2_END_INDEX, eas.w), 1809 xive_get_field64(EAS2_END_DATA, eas.w), 1810 false); 1811 return; 1812 } 1813 1814 void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) 1815 { 1816 Xive2Router *xrtr = XIVE2_ROUTER(xn); 1817 1818 xive2_notify(xrtr, lisn, pq_checked); 1819 return; 1820 } 1821 1822 static const Property xive2_router_properties[] = { 1823 DEFINE_PROP_LINK("xive-fabric", Xive2Router, xfb, 1824 TYPE_XIVE_FABRIC, XiveFabric *), 1825 }; 1826 1827 static void xive2_router_class_init(ObjectClass *klass, const void *data) 1828 { 1829 DeviceClass *dc = DEVICE_CLASS(klass); 1830 XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); 1831 1832 dc->desc = "XIVE2 Router Engine"; 1833 device_class_set_props(dc, xive2_router_properties); 1834 /* Parent is SysBusDeviceClass. No need to call its realize hook */ 1835 dc->realize = xive2_router_realize; 1836 xnc->notify = xive2_router_notify; 1837 } 1838 1839 static const TypeInfo xive2_router_info = { 1840 .name = TYPE_XIVE2_ROUTER, 1841 .parent = TYPE_SYS_BUS_DEVICE, 1842 .abstract = true, 1843 .instance_size = sizeof(Xive2Router), 1844 .class_size = sizeof(Xive2RouterClass), 1845 .class_init = xive2_router_class_init, 1846 .interfaces = (const InterfaceInfo[]) { 1847 { TYPE_XIVE_NOTIFIER }, 1848 { TYPE_XIVE_PRESENTER }, 1849 { } 1850 } 1851 }; 1852 1853 static inline bool addr_is_even(hwaddr addr, uint32_t shift) 1854 { 1855 return !((addr >> shift) & 1); 1856 } 1857 1858 static uint64_t xive2_end_source_read(void *opaque, hwaddr addr, unsigned size) 1859 { 1860 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 1861 uint32_t offset = addr & 0xFFF; 1862 uint8_t end_blk; 1863 uint32_t end_idx; 1864 Xive2End end; 1865 uint32_t end_esmask; 1866 uint8_t pq; 1867 uint64_t ret; 1868 1869 /* 1870 * The block id should be deduced from the load address on the END 1871 * ESB MMIO but our model only supports a single block per XIVE chip. 1872 */ 1873 end_blk = xive2_router_get_block_id(xsrc->xrtr); 1874 end_idx = addr >> (xsrc->esb_shift + 1); 1875 1876 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1877 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1878 end_idx); 1879 return -1; 1880 } 1881 1882 if (!xive2_end_is_valid(&end)) { 1883 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1884 end_blk, end_idx); 1885 return -1; 1886 } 1887 1888 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 1889 END2_W1_ESe; 1890 pq = xive_get_field32(end_esmask, end.w1); 1891 1892 switch (offset) { 1893 case XIVE_ESB_LOAD_EOI ... XIVE_ESB_LOAD_EOI + 0x7FF: 1894 ret = xive_esb_eoi(&pq); 1895 1896 /* Forward the source event notification for routing ?? */ 1897 break; 1898 1899 case XIVE_ESB_GET ... XIVE_ESB_GET + 0x3FF: 1900 ret = pq; 1901 break; 1902 1903 case XIVE_ESB_SET_PQ_00 ... XIVE_ESB_SET_PQ_00 + 0x0FF: 1904 case XIVE_ESB_SET_PQ_01 ... XIVE_ESB_SET_PQ_01 + 0x0FF: 1905 case XIVE_ESB_SET_PQ_10 ... XIVE_ESB_SET_PQ_10 + 0x0FF: 1906 case XIVE_ESB_SET_PQ_11 ... XIVE_ESB_SET_PQ_11 + 0x0FF: 1907 ret = xive_esb_set(&pq, (offset >> 8) & 0x3); 1908 break; 1909 default: 1910 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB load addr %d\n", 1911 offset); 1912 return -1; 1913 } 1914 1915 if (pq != xive_get_field32(end_esmask, end.w1)) { 1916 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1917 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1918 } 1919 1920 return ret; 1921 } 1922 1923 static void xive2_end_source_write(void *opaque, hwaddr addr, 1924 uint64_t value, unsigned size) 1925 { 1926 Xive2EndSource *xsrc = XIVE2_END_SOURCE(opaque); 1927 uint32_t offset = addr & 0xFFF; 1928 uint8_t end_blk; 1929 uint32_t end_idx; 1930 Xive2End end; 1931 uint32_t end_esmask; 1932 uint8_t pq; 1933 bool notify = false; 1934 1935 /* 1936 * The block id should be deduced from the load address on the END 1937 * ESB MMIO but our model only supports a single block per XIVE chip. 1938 */ 1939 end_blk = xive2_router_get_block_id(xsrc->xrtr); 1940 end_idx = addr >> (xsrc->esb_shift + 1); 1941 1942 if (xive2_router_get_end(xsrc->xrtr, end_blk, end_idx, &end)) { 1943 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, 1944 end_idx); 1945 return; 1946 } 1947 1948 if (!xive2_end_is_valid(&end)) { 1949 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: END %x/%x is invalid\n", 1950 end_blk, end_idx); 1951 return; 1952 } 1953 1954 end_esmask = addr_is_even(addr, xsrc->esb_shift) ? END2_W1_ESn : 1955 END2_W1_ESe; 1956 pq = xive_get_field32(end_esmask, end.w1); 1957 1958 switch (offset) { 1959 case 0 ... 0x3FF: 1960 notify = xive_esb_trigger(&pq); 1961 break; 1962 1963 case XIVE_ESB_STORE_EOI ... XIVE_ESB_STORE_EOI + 0x3FF: 1964 /* TODO: can we check StoreEOI availability from the router ? */ 1965 notify = xive_esb_eoi(&pq); 1966 break; 1967 1968 case XIVE_ESB_INJECT ... XIVE_ESB_INJECT + 0x3FF: 1969 if (end_esmask == END2_W1_ESe) { 1970 qemu_log_mask(LOG_GUEST_ERROR, 1971 "XIVE: END %x/%x can not EQ inject on ESe\n", 1972 end_blk, end_idx); 1973 return; 1974 } 1975 notify = true; 1976 break; 1977 1978 default: 1979 qemu_log_mask(LOG_GUEST_ERROR, "XIVE: invalid END ESB write addr %d\n", 1980 offset); 1981 return; 1982 } 1983 1984 if (pq != xive_get_field32(end_esmask, end.w1)) { 1985 end.w1 = xive_set_field32(end_esmask, end.w1, pq); 1986 xive2_router_write_end(xsrc->xrtr, end_blk, end_idx, &end, 1); 1987 } 1988 1989 /* TODO: Forward the source event notification for routing */ 1990 if (notify) { 1991 ; 1992 } 1993 } 1994 1995 static const MemoryRegionOps xive2_end_source_ops = { 1996 .read = xive2_end_source_read, 1997 .write = xive2_end_source_write, 1998 .endianness = DEVICE_BIG_ENDIAN, 1999 .valid = { 2000 .min_access_size = 1, 2001 .max_access_size = 8, 2002 }, 2003 .impl = { 2004 .min_access_size = 1, 2005 .max_access_size = 8, 2006 }, 2007 }; 2008 2009 static void xive2_end_source_realize(DeviceState *dev, Error **errp) 2010 { 2011 Xive2EndSource *xsrc = XIVE2_END_SOURCE(dev); 2012 2013 assert(xsrc->xrtr); 2014 2015 if (!xsrc->nr_ends) { 2016 error_setg(errp, "Number of interrupt needs to be greater than 0"); 2017 return; 2018 } 2019 2020 if (xsrc->esb_shift != XIVE_ESB_4K && 2021 xsrc->esb_shift != XIVE_ESB_64K) { 2022 error_setg(errp, "Invalid ESB shift setting"); 2023 return; 2024 } 2025 2026 /* 2027 * Each END is assigned an even/odd pair of MMIO pages, the even page 2028 * manages the ESn field while the odd page manages the ESe field. 2029 */ 2030 memory_region_init_io(&xsrc->esb_mmio, OBJECT(xsrc), 2031 &xive2_end_source_ops, xsrc, "xive.end", 2032 (1ull << (xsrc->esb_shift + 1)) * xsrc->nr_ends); 2033 } 2034 2035 static const Property xive2_end_source_properties[] = { 2036 DEFINE_PROP_UINT32("nr-ends", Xive2EndSource, nr_ends, 0), 2037 DEFINE_PROP_UINT32("shift", Xive2EndSource, esb_shift, XIVE_ESB_64K), 2038 DEFINE_PROP_LINK("xive", Xive2EndSource, xrtr, TYPE_XIVE2_ROUTER, 2039 Xive2Router *), 2040 }; 2041 2042 static void xive2_end_source_class_init(ObjectClass *klass, const void *data) 2043 { 2044 DeviceClass *dc = DEVICE_CLASS(klass); 2045 2046 dc->desc = "XIVE END Source"; 2047 device_class_set_props(dc, xive2_end_source_properties); 2048 dc->realize = xive2_end_source_realize; 2049 dc->user_creatable = false; 2050 } 2051 2052 static const TypeInfo xive2_end_source_info = { 2053 .name = TYPE_XIVE2_END_SOURCE, 2054 .parent = TYPE_DEVICE, 2055 .instance_size = sizeof(Xive2EndSource), 2056 .class_init = xive2_end_source_class_init, 2057 }; 2058 2059 static void xive2_register_types(void) 2060 { 2061 type_register_static(&xive2_router_info); 2062 type_register_static(&xive2_end_source_info); 2063 } 2064 2065 type_init(xive2_register_types) 2066